1. * GB780019 (A)
Description: GB780019 (A) ? 1957-07-31
Improvements relating to electrical storage apparatus
Description of GB780019 (A)
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The EPO does not accept any responsibility for the accuracy of data
and information originating from other authorities than the EPO; in
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up-to-date or fit for specific purposes.
PATENT SPECIFICATION
Investor: EDGAR tFREERicaiK DIAwSiON Date of filing Complete
Specification: Dec. 1, 1955.
Application Date: Dec. 10, 1954.
No. 35845/54.
H a/ Complete Specification Published: July 31, 1957.
Index at acceptance: -Classes 40(6), T; and 106(1), C(1F: 2J: 2K).
International Classification:-G06f. H03f.
COMPLETE S1PECIFICATION Improvements relating to Electrical Storage
Apparatus We, THE [BRITISH THOMSON-JHOUSTON COMPANY LIMITED, a British
Company haying its registered office at Crown House, Aldwych, London,
W.C.2, do hereby declare the invention for which we pray that a patent
may be granted to us, and the method by which it is to be performed,
to be particularly described in and by the following statement:This
invention relates to electrical storage apparatus and more
particularly to storage systems for numerical data in binary form.

2. The main object of the invention is to provide improved storage
apparatus in which the data stored 'can be read without cancellation.
According to the present invention the storage apparatus comprises an
array of double base transistors and means for selectively triggering
the transistors by applying a bias voltage between the base electrodes
and concurrently applying between the trigger electrode and one of the
base electrodes of the selected transistor a voltage which is in such
a sense and of such magnitude relative to the bias voltage between the
base electrodes as to trigger the device and condition the collector
electrode to provide an indication.
The ternm 'double base transistor' implies a device comprising a rod
or blodk of semiconductor material having two base electrodes spaced
apart, a trigger electrode forming a p-n junction at a point
intermediate the base electrodes and a collector electrode also
forming a p-n junction at an intermediate point near to the trigger
electrode. The device is so arranged that if a potential difference is
applied between the base electrodes so as to form a potential gradient
along the semiconductor and the trigger electrode is at a potential
which is less positive than the potential existing in the adjacent
semi-conductor then substantially no current will flow through the p-n
junction. If however the potential applied to the trigger electrode
is, increased until it becomes substantially the same as that in the
adjacent semi-conductor a value will [Price 3s. 6d.] be reached at
which the p-n junction will suddenly become highly conductive and if
it is connected to one of the base electrodes through an external
circuit current will flow through this circuit and wiill cause the
collector electrode also to become conductive and to pass current if
connected through an external circuit.
- In applications to binary storage systems a number of double base
transistors, may be arranged in a matrix type array of rows and
columns, each transistor having one of the base electrodes connected
to earth or:a suitable reference potential whilst the other base
electrode is 'connected to an appropriate common,busbar extending
along the row in which the transistor -is located; the trigger
electrode is similarly connected to a busbar extending along the
appropriate 'column and the collector electrode is-adapted to be
connected to an external circuit to provide the necessary data storage
indication.
It will be appreciated that the arrangement is such that if an
operating potential is applied to a row busbar only or to a column
busbar only, none of the transistors will be triggered but if
operating potentials are applied simultaneously to a row busbar and a
column busbar a transistor at the intersection of the column and row
concerned will be triggered and will remain triggered until it is

3. returned to its original state provided the external circuits between
the base electrodes and between the trigger and base electrodes are
not broken.
Preferably the operating potentials are in pulse form.
In order that the invention may be more clearly understood reference
will now be made to the drawing accompanying the Provisional
Specification, in which:
Fig. 1 shows diagrammatically the arrangement of a trigger type
transistor.
Fig., 2 shows how such- transistors can be arranged in the lattice to
provide storage -information of binary data, and Fig. 3 is a graph
showing the junction 780,019 2 780,019 characteristics of a double
base transistor as shown in Fig. 1.
In Fig. 1 it will be seen that the transistors employed each comprise
a rod of semiconductor material extending between the base electrodes
B and D and with a trigger electrode A at an intermediate point,
whilst opposite the trigger electrode A is a collector electrode C.
Assuming that a bias voltage Eb is connected between the base
terminals B and D and that a trigger electrode A is connected to the
terminal D through a source of bias voltage V'a, the arrangement being
such that positive potentials are applied to A and to B, then so long
as the potential applied to the trigger electrode A is less than the
potential at an adjacent point in the transistor the device will
remain untriggered and no current will flow if the collector electrode
C is connected to an external circuit. If, howvever, either Va is
increased or Eb is reduced or both Va is increased and simultaneously
Eb is reduced, in all cases to an extent such that the potential at
the trigger electrode A is the same or slightly positive with respect
to the potential in the adjacent transistor, then the device will
trigger and a current Ia will flow through the external circuit to
which the trigger electrode is connected. If the collector electrode C
is connected to an external circuit, current will now flow through
this, indicating that data has been stored. These conditions are
illustrated graphically in Fig.
3 in which Ia is plotted against Va. So long as the device is
untriggered, i.e. so long as the voltage Va is to the left of point P
the current will lie along the section OP of the curve, in other words
there will be a very slight reverse junction current and current to
the collector will be substantially zero.
If now the voltage Va is increased to the point P the device will
trigger and the current will increase moving along the sections PS of
the graph which represents a negative resistance stage and finally
coming to rest along the section SQ. Clearly the device will remain
triggered even though Va is reduced unless it moves to the left of

4. point S.
Clearly instead of increasing Va the base electrode B could be made
less positive. This will reduce the voltage gradient along the
transistor between B and 1) and will have the effect of moving the
graph bodily to the left until the point P reaches the point R so that
the graph will be positioned, as shown by the dotted line, when the
device may be also triggered. In actual arrangements embodying the
invention triggering is effected by a positive pulse applied to the
trigger electrode simultaneously with a negative pulse applied to the
base electrode B the input pulse amplitudes being small so that
triggering cannot occur when only one input is applied.
Fig. 2 shows a storage matrix comprising an array of busbars arranged
in rows and columns. The base electrode B of each storage transistor
is connected to the appropriate row busbar and the trigger electrode A
to the appropriate column busbar. The terminal electrodes D are
earthed, whilst the collector electrode C provides an indication of
the data.
Thus, when trigger pulses are applied simultaneously to the first row
and the first column so that the trigger electrode All of the first 75
transistor receives a positive pulse and the base electrode B1 1
receives a negative pulse the device 11 will be triggered and the
collector electrode Cll will provide an indication as current will
flow if it is connected 80 to an external circuit. It follows that by
applying trigger potentials simultaneously to the appropriate row and
the appropriate column any desired transistor can be selected.
In this way digital information can be set 85 up in the matrix.
Thereafter the application of a further small pulse to the trigger
electrodes A will produce no output from the collector of the
transistors that have not been triggered as the collector p-n junction
will 90 not be conductive but it will produce pulse outputs from the
collectors of those that have been triggered. Thus the information
stored can be read out and this can be done without altering the
transistors from their triggered 95 state., According to one such
arrangement the collector electrodes may be arranged in rows and the
information will be read out by gating the collector outputs. 100 It
will be appreciated that whilst in the arrangement shown the upper
base electrodes B have been connected to the row busbars and the
trigger electrodes A to the column busbars, clearly these connections
may be interchanged. Furthermore, the upper base terminals B could
alternatively be earthed in which case it will be necessary to apply
steady negative potentials to the trigger electrodes and lower base
electrodes D. 110 The trigger electrode will still require a positive
impulse for triggering to occur, but in this case a simultaneous
positive trigger to the lower base electrode will be required.

5. The foregoing description refers to a trigger 115 transistor having a
base material of the ntype activation in which base conduction is due
to an excess of electrons. If p-type semiconductor material is used
for the base of this device it will be obvious that the 120 polarities
of all potentials mentioned must be reversed.
It will also be appreciated that whilst the transistors may be
triggered by pulses it is necessary to maintain external circuits both
125 between the base electrodes B and D and also between the
triggering electrode A and the base D (or B as the case may be) so
long as they are triggered but the voltage in such circuits may be
appreciably less than that re780,019 tending along the row in which
the transistor is located, the trigger electrode is similarly
connected to a busbar extending along the appropriate column and the
collector electrode is adapted to be connected to an external circuit
to provide the necessary data storage indication.
3. Storage apparatus as claimed in claim 1 or claim 2 including means
for triggering selected transistors by application of pulse voltages
to the appropriate electrodes and means for maintaining external
circuits through said electrodes at least during the period in which
said transistors are to remain triggered.
4. Storage apparatus for numerical data in binary form substantially
as described with reference to the drawing accompanying the
Provisional Specification.
J. W. RIIDDING, Chartered Patent Agent, 64-66, Coleman Street, London,
'E.C.2, Agent for the Applicant.
quired to change the transistor from the untriggered to the triggered
state.
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* 5.8.23.4; 93p