VHDL - Thầy Lê Hải Sâm

6. Các mức trừu tượng trong mô tả phần cứng Behavioral Logic RTL Layout Ít chi tiết hơn, thiết kế và mô phỏng nhanh hơn Chi tiết hơn, phụ thuộc công nghệ, thiết kế và mô phỏng chậm hơn DFF AND_OR2 CLB_R5C5 CLB_R5C6 F

7. Sự chồng chéo trong VHDL Behavioral Logic RTL Layout Place & Route Utility FPGA Vendor Library Synthesizable Code Hardware Model Sum <= A + B after 3 ns ; Sum <= A + B ; component Xlx_add2 port ( A: in bit ; B: in bit ; Sum: out bit ); end component ;

10. Cấu trúc Top - Down A[3:0] entity Add_4 B[3:0 ] C_in SUM [3:0] C_out C_out Sum A B C_in entity Full_Add A B entity Half_Add Sum Carry Leaf Cell Macro

29. Ví dụ về Hierarchy : DFF entity DFF is port (D, Clock : in std_logic ; Reset : in std_logic ; Q : out std_logic) ; end entity DFF ; architecture RTL of DFF is begin process (Clock, Reset) begin If (Reset = ‘1’ ) then Q <= ‘0’ ; elsif (Clock’event and Clock = ‘1’) then Q <= D ; end if ; end process ; end architecture RTL ; Clock Reset D Q

30. Ví dụ về Hierarchy : REG-4 entity REG_4 is port (D_in : in std_logic_vector (3 downto 0); Clk, Rst : in std_logic ; Q_out : out std_logic_vector (3 downto 0)); end REG_4; architecture Structural of REG_4 is component DFF port ( D, Clock : in std_logic ; Reset : in std_logic; Q : out std_logic ) ; end component ; begin U3 : DFF port map ( D_in(3), Clk, Rst, Q_out(3)); U2 : DFF port map ( D_in(2), Clk, Rst, Q_out(2)); U1 : DFF port map ( D_in(1), Clk, Rst, Q_out(1)); U0 : DFF port map ( D_in(0), Clk, Rst, Q_out(0)); end Structural ; Clk Rst D_in(3) D_in(2) D_in(1) D_in(0) Q_out(3) Q_out(2) Q_out(1) Q_out(0) DFF DFF DFF DFF U3 U0 U1 U2 REG_4

58. Records Record là nhóm các phần tử đơn có kiểu ban đầu có thể khác nhau . type OPCODE is record PARITY : bit; ADDRESS : std_logic_vector ( 0 to 3 ); DATA_BYTE : std_logic_vector ( 7 downto 0 ); NUM_VALUE : integer range 0 to 6; STOP_BITS : bit_vector (1 downto 0); end record ; . . . signal TX_PACKET, RX_PACKET : OPCODE ; PARITY ADDRESS DATA_BYTE NUM_VALUE STOP_BITS . . . T X _ P A C K E T

59. String String là array của các character signal Warning1: string (1 to 30) := “ Unexpected Outputs Detected” ; --declared within the architecture variable Warning2: string (1 to 30) := “ Unstable, Aborting Now” ; --declared within the process constant Warning3: string (1 to 20) := “ Entering FSM State2” ; --declared within the package or architecture process ( A_sig , B_sig, C_sig ) begin if ( A_sig and B_sig ) /= ‘1’ then report Warning1 ; elsif ( A_sig and C_sig ) = ‘1’ then report Warning2 & “ Problem Mod2 “; end if ; end process ; process ( A_sig , B_sig, C_sig ) begin assert ( A_sig and B_sig ) /= ‘1’ then report Warning1 ; severity note ; end if ; end process ; process ( A_sig , B_sig, C_sig ) begin if ( A_sig and B_sig ) /= ‘1’ then report “ Unexpected Outputs…” ; elsif ( A_sig and C_sig ) = ‘1’ then report “ I need a vacation “; end if ; end process ;

67. Sử dụng kiểu con trong VHDL type My_State is ( Load, Jump, Add, Sub, Div, Mult , StorA, StorB) ; signal Curr_State, Next_State : My_State ; Label Base Type Constraint subtype Arith_Ops is My_State range Add to Mult ; subtype My_OHE_State is std_logic_vector ( 3 downto 0 ) ; constant Init_St0 : My_OHE_State := “0001” ; constant Load_St1 : My_OHE_State := “0010” ; constant Jump_St2 : My_OHE_State := “0100” ; constant Stor_St3 : My_OHE_State := “1000” ;

72. Các toán tử Logic với biến kiểu Array Quy tắc sử dụng với biến kiểu Array 1. Các array phải có cùng kiểu (type) 2. Các array phải có cùng kích thước 3. Phép toán thực hiện với các phần tử cùng vị trí trong mỗi array, từ trái sang phải signal A_vec, B_vec, C_vec : bit_vector ( 7 downto 0 ) ; B_vec (7) A_vec (7) C_vec (7) B_vec (6) A_vec (6) C_vec (6) B_vec (5) A_vec (5) C_vec (5) B_vec (0) A_vec (0) C_vec (0) . . . C_vec <= A_vec and B_vec ;

91. Các thành phần của Process architecture Behave of DFF is begin . . . Reg1 : process ( Clock, Reset ) begin if Reset = ‘1’ then Q <= ‘0’ ; elsif ( Clock ’event and Clock = ‘1’ ) then Q <= D ; end if ; end process ; . . . end Behave ; Optional Label Signals in sensitivity list create implied “wait” condition Signal updated with new value when process suspends All statements within the process are handled sequentially, in order Keyword Keywords “end” and “process”

92. Bên trong và bên ngoài Process architecture ... process ( ) begin Out1 <= A; Out1 <= B; . . . end process ; end architecture ; architecture . . . begin Out1 <= A; Out1 <= B; . . . end architecture ; B B Chỉ có phép gán cuối cùng là có hiệu lực Out1 ? Out1 A Cần phải có một hàm resolution cho tín hiệu ra ‘Out1’

97. Scheduling Events Simulation discrete time steps t t+1 t+2 t+3 D1 D+n D+2 D+1 t+4 . . . Delta cycles D1 D+2 D+1 . . . Delta cycles Transaction Queue t + 3 t + 4 t + 5 . . . . . . Int <= ‘1’ Data<= ‘0’ Out1 <= ‘1’ ; Out2 <= ‘0’ ; . . . Int <= ‘1’ after 1 ns; . . . Data <= ‘0’ after 2 ns; . . . . . . Out2<= ‘0’ Out1<= ‘1’ ns Discrete Time Delta Cycles

100. Building Registers process ( Clk) begin if (Clk’ event and Clk = ‘1’) then C <= A and B ; end if; end process; Mọi phép gán tín hiệu xảy ra sau mệnh đề: if clock’event and clock = ‘1’ then... đều tạo ra một cấu trúc thanh ghi (register) C Clk B A

104. Phép gán với Signal entity Count_1 is port (Clk, D : in bit ; Q : out integer range...); end Count_1; architecture WRONG of Count_1 is begin process (Clk) begin If Clk’ event and Clk =‘1’ then Q <= Q + 1; end if ; end process ; Q Internal_Cnt Will produce compiler error architecture RTL of Count_1 is signal Internal_Cnt : integer range ... ; begin process (Clk) begin If Clk’ event and Clk =‘1’ then Internal_Cnt <= Internal_Cnt + 1 ; end if ; end process ; Q <= Internal_Cnt ; Counter

106. Variable trong các Process có Clock process ( Clk ) variable B, C, D : bit := ‘1’ ; begin If ( Clk ’event and Clk =‘1’) then B := A ; C := B ; D := C ; end if ; end process ; Clk A D process ( Clk ) variable B, C, D : bit := ‘1’ ; begin If ( Clk ’event and Clk =‘1’ ) then D := C ; C := B ; B := A ; end if ; end process ; Clk A C B D

107. entity Count_1 is port (Clk, D : in std_logic ; Q : out std_logic_vector ...); end Count_1; architecture WRONG of Count_1 is begin process (Clk) begin If Clk’ event and Clk =‘1’ then Q <= Q + 1; end if ; end process ; Q Internal_Cnt Alternate Solution Will produce compiler error architecture RTL of Count_1 is begin process (Clk) variable Internal_Cnt : std_logic_vector .. begin If Clk’ event and Clk =‘1’ then Internal_Cnt := Internal_Cnt + 1 ; Q <= Internal_Cnt ; end if ; end process ; Counter

108. Các lệnh điều khiển chương trình trong VHDL Bài 6