The document provides a block diagram and overview of the components and classifications of microcontrollers. It shows that a microcontroller contains an ALU, registers, RAM, ROM, CPU, interrupt circuit, timer/counter, program counter, stack pointer, clock circuit, and input/output ports. It then classifies microcontrollers based on bits, memory, instruction set, architecture, family, and according to memory devices.

1. Block Diagram of Microcontroller
ALU
(ArithmeHc Logic Unit)
Registers
(Accumulator &
General Purpose)
I RAM
I ROM
[ CPU
Interrupt
Circuit
Timer / Counter
I
I
]
0
Program Counter
(PC)
Stack Pointer
(SP)
Clock
Circuit
Input / Output Ports

2. CLASSIFICATION OF MICROCON'fROJ.J.ER
Bits Memory Instruction Set Architecture
0
• CISC • Von-neumann
• 4 bit • External Memory
• 8 bit • Embedded Memory • RISC • Harvard
• 16 bit Family
• 32 bit
t
l I I I I l
8051 Motorola PIC Texas National ARM Other
I I I I
INTEL Atmel Dallas Phillips Siemens

3. CLASmf'ICATION ACCORDIN6 TO errs
• 8 bits microcontroller : executes logic & arithmetic
op~rations. example: Intel 8031/8051 .
• 16 bits microcontroller: executes with greater accuracy and
performance in contrast to 8-bit. example: Intel 8096.
• 32 bits microcontroller: is employed mainly in automatically
controlled appliances such as office machines, implantable
medical appliances, etc. It requires 32-bit instructions to carry
out any logical or arithmetic function.

4. C~IFICATION ACC TO MEMOR~DEflCES
0
• External Memory Microcontroller
• Embedded Memory Microcontroller

5. INSl'RUCfION SET
• CISC (complex instruction set computer): it allows the
user to apply 1 instruction as an alternative to many simple
instructions.
• RISC (Reduced Instruction Set Computers): RISC
reduces the operation time by shortening the clock cycle per
instruction.
i

6. MEMORl'ARCB.fl'ECTURE
0
• Harvard Memory Architecture
• Von Neumann Memory Architecture

7. Von Neumann Memory Architecture
Input
Device
0
Central Processing Unit
Control Unit
IArtthmetk:Jloglc Unit I
Memory Unit
Output
Device

8. Harvard Memory Architecture
Instruction Clnllll
¢✓i
Data
memory . . . 0 memory
D
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