Modelsim Training in Phagwara Jalandhar

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The main motive of industrial training institute is to educate desired students about the industry and the online trends in the world of IT. As we know, IT industry keeps on changing – and it always is a good idea to learn and grow in a great ambiance where you can learn better about the field regarding different prospects.
Why to Enroll for Industrial Training Courses?
Create & Develop a LIVE Project
Enhance your skills and become employable by hands-on training
Get Corporate Exposure & interact with industry experts
Get Technology Certification & Project Experience
Project based training is an important aspect of any training program and an integral part of the curriculum of all engineering and technical courses. Moreover, a student gets a chance to work on live project to sharpen his knowledge and skills. Many prestigious universities have included 6 months training program in their curriculum to help students learning and reaching their goals.
E2MATRIX Provide industrial training for all those students who want to learn software languages and methodology. We have all types of training programs as per the requirements of students. Our 6 Months Industrial Training Program is especially for last semester students of MCA, B. Tech., BE, M.sc, B.sc. Diploma etc. Students will work on LIVE PROJECTS during their 6 monthsindustrial training. So why just go to any institute for training if you have an opportunity to learn from it experts

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Modelsim Training in Phagwara Jalandhar

  1. 1. MODELSIM Training in Phagwara E2MATRIX CALL: +91 9041262727, 9779363902 WEB: WWW.E2MATRIX.COM EMAIL: SUPPORT@E2MATRIX.COM E2MATRIX
  2. 2. Outline Command Line Simulation ◦ Compile and Simulate ◦ Add Signals to Wave ◦ Applying Inputs Interactive Simulation 2
  3. 3. Command Line Simulation Make sure Modelsim exists in the path by doing the following ◦Windows: ◦ Start run -> cmd ◦ In cmd window: vsim -version ◦Linux: ◦ In any shell: vsim -version 3
  4. 4. Command Line Simulation Create VHDL file ◦ Edit the file my_demo1.vhd ◦ Insert the text and save 4 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY andgate IS port (a, b: in std_logic_vector(2 downto 0); c: out std_logic_vector(2 downto 0) ); END ENTITY; ARCHITECTURE behav OF andgate IS BEGIN c <= a and b; END ARCHITECTURE;
  5. 5. Compile and Simulate vlib work vcom <VHDL files> vsim <top level> 5 • vlib: creates a library to compile and simulate the code with • vcom: compiles VHDL files, the files should be ordered in a hierarchal way [leaf level first then top] • vsim: starts the simulator to simulate the top level module
  6. 6. Add signals to Wave RMB on any signal in the Objects window  Add  to Wave  signals in Region Now start applying inputs and monitor outputs 6
  7. 7. Applying Inputs RMB on input port  force 7 • In the “value” field, insert an appropriate value OK • Apply inputs to other inputs
  8. 8. Run Simulation Press run button Monitor the output 8
  9. 9. Make Files On Unix: If you changed the code you will have to recompile the design files again. A make file is used to do repetitive compilation and simulation tasks; “Make” knows which files have been edited and automatically compiles only changed files. ModelSim offers a simple way to automatically generate a Makefile for your design hierarchy. vmake work > Makefile To recompile code at anytime just type make 9
  10. 10. Interactive Simulation File  new project Insert project name and location; leave other fields with defaults 10
  11. 11. Interactive Simulation In “Add items to the project” window choose “Create new file” Insert file name Make sure to select VHDL 11
  12. 12. Interactive Simulation Create VHDL file ◦ Edit the file my_demo1.vhd ◦ Insert the text and save 12 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY andgate IS port (a, b: in std_logic_vector(2 downto 0); c: out std_logic_vector(2 downto 0) ); END ENTITY; ARCHITECTURE behav OF andgate IS BEGIN c <= a and b; END ARCHITECTURE;
  13. 13. Compile VHDL files Select the file  RMB  compile selected 13
  14. 14. Simulation Simulate menu  Start Simulation Expand work library and select andgate  OK 14

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