A set of waveforms applied to two D flip-flops is shown in Figure 4-56. These waveforms are applied to the flip-flops shown along with the values of their timing parameters. (a) List the time(s) at which there are timing violations in signal D1 for flip-flop 2. (b) List the time(s) at which there are timing violations in signal D2 for flip-flop 2. Solution flip flop 1 is a positive edge triggered flop. The inputs should be seen at the rising edge of the clock for signal D1, at the fourth rising edge i.e t = 28ns, violation occurs. D1 is rising at the same edge, it should be stable for Ts = 1ns before and Th =0.5ns after the edge. 2) flipflop 2 is a negative edge triggered. At second negative edge i.e t = 16ns and third negative edge i.e t = 24ns, D2 signal viloates the timing requirements of flop2.

1. A set of waveforms applied to two D flip-flops is shown in Figure 4-56. These waveforms are
applied to the flip-flops shown along with the values of their timing parameters.
(a) List the time(s) at which there are timing violations in signal D1 for flip-flop 2.
(b) List the time(s) at which there are timing violations in signal D2 for flip-flop 2.
Solution
flip flop 1 is a positive edge triggered flop.
The inputs should be seen at the rising edge of the clock
for signal D1, at the fourth rising edge i.e t = 28ns, violation occurs.
D1 is rising at the same edge, it should be stable for Ts = 1ns before and Th =0.5ns after the
edge.
2)
flipflop 2 is a negative edge triggered.
At second negative edge i.e t = 16ns and third negative edge i.e t = 24ns, D2 signal viloates the
timing requirements of flop2