Vhdl presentation about the invention of this technology and its specifications

1. CASE versus IF:
1-IF Statement:
• The if statement in VHDL is similar to those in many programming languages. It follows a sequential
execution structure.
• It's suitable for making decisions based on a single condition or a few conditions sequentially.
• Example: if condition1 then
-- Do something
elsif condition2 then
-- Do something else
else
-- Default action
end if;
2-Case Statement:
• The case statement in VHDL is particularly helpful when there are multiple conditions to be
checked against a single variable. It's a bit more structured and cleaner when dealing with multiple
possibilities.

2. • Example:case variable_name is
when value1 =>
-- Action for value1
when value2 =>
-- Action for value2
when others =>
-- Default action
end case;
CASE versus WHEN:
CASE and WHEN are very similar. However, while one is concurrent (WHEN), the other is
sequential (CASE).
1-when Statement:
Example: WITH sel SELECT
x <= a WHEN "000",
b WHEN "001",
c WHEN "010",
UNAFFECTED WHEN OTHERS;

3. 2-Case Statement:
• Example:case variable_name is
when value1 =>
-- Action for value1
when value2 =>
-- Action for value2
when others =>
-- Default action
end case;
Signal versus variable:
1-signals:
• Signals represent physical connections between components in the hardware description. They are
used to model interconnection between different parts of the design.
• They can be assigned using the <= assignment operator within concurrent code.

4. • Example:SIGNAL name : type [range] [:=initial_value];
• temp <= 0;
2-Variable:
• Variables are used for temporary storage of data within a process or a block of sequential
code.
• Variables cannot be used for inter-process communication.
• They are assigned using the := assignment operator within sequential code, like inside a
process.
• Example:VARIABLE y: STD_LOGIC_VECTOR (7 DOWNTO 0)
• temp := temp + 1;
3-constant:
• Constants in VHDL are used to define fixed values that remain unchanged throughout the
simulation or synthesis. Here are some key aspects about constants in VHDL:

5. • Example:CONSTANT set_bit : BIT := '1' ;
CONSTANT datamemory : memory := (( '0' , '0' , '0' , '0' ),
( '0' , '0' , '0' , '1' ),
( '0' , '0' , '1' , '1' ));

6. Featured Presenters
Moaz abdeljalil salah
Nour eldin fares
Hadeer ibrahim
Yassmin emad
Sec:3