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Education
Indraprastha Institute of Information Technology-Delhi
M.Tech
2015- Till Present
UIET, Kurukshetra University, Kurukshetra
B.Tech(ECE)
2009 – 2013
CGPA- 7.54
Percentage: 68
Kapil Vidhya Mandir, Mohindergarh
XII th (Haryana state board)
2008 – 2009
GPA: 8.6
Kapil Vidhya Mandir, Mohindergarh
X th (Haryana state board)
2006 – 2007
GPA: 8.8
Skills
Expertise Area Analog and Digital Electronics, Communication, Circuit Theory
Programming
Language
C++, JAVA, Verilog, System-C,MATLAB
Tools SPICE TOOLS(Cadence virtuoso, Eldo), MATLAB, ADS(Advanced Design
System), COMSOL
Technical
Electives
Engineering Optimization, VLSI, Mix-Signal Design, RF Circuit Design, Analog
System Design
Internship
Projects
RFID based TollTax design with fabrication of antenna
(MINI PROJECT)- B.Tech
(This was extended to layout design and fabrication.)
Guide: Mr. C C Tripathi (HOD, UIET)
Team Size-2
VISHAV VIKASH
MT15117, Email: vishav15117@iiitd.ac.in
DOB: Nov. 13, 1992
Address: Near Central Bank Of India, Shekhawat
colony, Railway Road, Mohindergarh (HR)-123029
Title: Summer training (Embedded System, Introduction to Microcontrollers )
Conducted by D`COP Pvt. Ltd(Noida).
NOC Router design
(The Design of low power NOC Router was successfully implemented using
Verilog.
Simulation Environment: Xilinx ISE design suite and Synopsis.)
Guide: Dr. Sujay Deb
Team Size-3
Reconfigurable Matching Circuit designs Team Size-2
(Introduction to MEMS and using MEMS switches we have drawn a stub type
capacitor to make the circuit properties reconfigurable.
Simulation Environment: ADS 2015 and COMSOL )
Guide: Dr. M S Hashmi
Low power Flash ADC design and propose new architecture Team Size-3
(Using the Inverter as a single bit comparator and with a new Encoder scheme
We here developed a new configuration of ADC which consumes a very little power
on the cost of minimized accuracy.
Simulation Environment: Cadence- Virtuoso)
Guide: Dr. Vishwasharan
Designing a Noval Biomedical Amplifier Team Size-1
(Ongoing)- I am supposed to write a literature review and Design
a new differential type OTA with high gain.
Guide : Dr. P. Ganga Bahubalindruni
Positions of Responsibility and Achievements
 ONE YEAR experience in SBI Life Insurance as Advisor and as CBD(From July 2013-December
2014)
 Student Senet Member (From April 1, 2016, till present)
 Currently Represented M.Tech (2015) in academics as an active student council member
 Placement Community Member for(2016-Today)
 TA(Teaching Assistant) for two subjects including Digital Circuits and Signals and System
 Organized more than five times workshops in B.Tech (Technical)
 Coordinator in College Cultural Fest- UIET(KUK)-2012
Interests and Hobbies
 Playing Badminton and Volleyball
Declaration: The above information is correct to the best of my knowledge.
Vishav Vikash
Date: July 02, 2016

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MTECH_VISHAVVIKASH

  • 1. Education Indraprastha Institute of Information Technology-Delhi M.Tech 2015- Till Present UIET, Kurukshetra University, Kurukshetra B.Tech(ECE) 2009 – 2013 CGPA- 7.54 Percentage: 68 Kapil Vidhya Mandir, Mohindergarh XII th (Haryana state board) 2008 – 2009 GPA: 8.6 Kapil Vidhya Mandir, Mohindergarh X th (Haryana state board) 2006 – 2007 GPA: 8.8 Skills Expertise Area Analog and Digital Electronics, Communication, Circuit Theory Programming Language C++, JAVA, Verilog, System-C,MATLAB Tools SPICE TOOLS(Cadence virtuoso, Eldo), MATLAB, ADS(Advanced Design System), COMSOL Technical Electives Engineering Optimization, VLSI, Mix-Signal Design, RF Circuit Design, Analog System Design Internship Projects RFID based TollTax design with fabrication of antenna (MINI PROJECT)- B.Tech (This was extended to layout design and fabrication.) Guide: Mr. C C Tripathi (HOD, UIET) Team Size-2 VISHAV VIKASH MT15117, Email: vishav15117@iiitd.ac.in DOB: Nov. 13, 1992 Address: Near Central Bank Of India, Shekhawat colony, Railway Road, Mohindergarh (HR)-123029 Title: Summer training (Embedded System, Introduction to Microcontrollers ) Conducted by D`COP Pvt. Ltd(Noida).
  • 2. NOC Router design (The Design of low power NOC Router was successfully implemented using Verilog. Simulation Environment: Xilinx ISE design suite and Synopsis.) Guide: Dr. Sujay Deb Team Size-3 Reconfigurable Matching Circuit designs Team Size-2 (Introduction to MEMS and using MEMS switches we have drawn a stub type capacitor to make the circuit properties reconfigurable. Simulation Environment: ADS 2015 and COMSOL ) Guide: Dr. M S Hashmi Low power Flash ADC design and propose new architecture Team Size-3 (Using the Inverter as a single bit comparator and with a new Encoder scheme We here developed a new configuration of ADC which consumes a very little power on the cost of minimized accuracy. Simulation Environment: Cadence- Virtuoso) Guide: Dr. Vishwasharan Designing a Noval Biomedical Amplifier Team Size-1 (Ongoing)- I am supposed to write a literature review and Design a new differential type OTA with high gain. Guide : Dr. P. Ganga Bahubalindruni Positions of Responsibility and Achievements  ONE YEAR experience in SBI Life Insurance as Advisor and as CBD(From July 2013-December 2014)  Student Senet Member (From April 1, 2016, till present)  Currently Represented M.Tech (2015) in academics as an active student council member  Placement Community Member for(2016-Today)  TA(Teaching Assistant) for two subjects including Digital Circuits and Signals and System  Organized more than five times workshops in B.Tech (Technical)  Coordinator in College Cultural Fest- UIET(KUK)-2012 Interests and Hobbies  Playing Badminton and Volleyball Declaration: The above information is correct to the best of my knowledge. Vishav Vikash Date: July 02, 2016