CMOS Digital Integrated Circuit Device Modeling Report
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SPICE Model of TC74AC244F in SPICE PARK. This SPICE Model is PSpice Model Using Digital library.
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CMOS Digital Integrated Circuit Device Modeling Report
- 1. Device Modeling Report COMPONENTS : CMOS DIGITAL INTEGRATED CIRCUIT PART NUMBER : TC74AC244F MANUFACTURER : TOSHIBA Bee Technologies Inc. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 2. SPICE MODEL _ U1 1G VCC 1A1 2G 2Y4 1Y1 1A2 2A4 2Y3 1Y2 1A3 2A3 2Y2 1Y3 1A4 2A2 2Y1 1Y4 GND 2A1 74AC244 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 3. Truth Table Circuit simulation result Evaluation circuit _ U1 1G VCC LO 1A1 2G LO LO 2Y4 1Y1 1A2 2A4 LO LO 2Y3 1Y2 1A3 2A3 LO LO R1 V1 2Y2 1Y3 1MEG 1A4 2A2 LO LO 5 2Y1 1Y4 GND 2A1 LO 74AC244 0 Comparison table Input Output %Error G An Yn (Measurement) Yn (Simulation) L L L L 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 4. Truth Table Circuit simulation result Evaluation circuit _ U1 1G VCC LO _ HI 1A1 2G LO 2Y4 1Y1 HI 1A2 2A4 HI 2Y3 1Y2 HI 1A3 2A3 HI R1 V1 2Y2 1Y3 1MEG 1A4 2A2 HI HI 5 2Y1 1Y4 GND 2A1 HI 74AC244 0 Comparison table Input Output %Error G An Yn (Measurement) Yn (Simulation) L H H H 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 5. Truth Table Circuit simulation result Evaluation circuit _ U1 HI 1G VCC _ 1A1 2G HI 2Y4 1Y1 1A2 2A4 X 2Y3 1Y2 1A3 2A3 X V1 R1 2Y2 1Y3 1MEG DSTM1 CLK 1A4 2A2 5 OFFTIME = .2uS 2Y1 1Y4 ONTIME = .2uS GND 2A1 74AC244 0 Comparison table Input Output %Error G An Yn (Measurement) Yn (Simulation) H X Z Z 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 6. High Level and Low Level Input Voltage Circuit simulation result Output Input Evaluation circuit _ U1 1G VCC LO _ 1A1 2G LO 2Y4 1Y1 OUT 1A2 2A4 2Y3 1Y2 V2 V1 = 0 V2 = 5.5 V1 1A3 2A3 TD = 0.5m R3 TR = 0.1m 2Y2 1Y3 5.5 TF = 0.1m 1MEG PW = 1m 1A4 2A2 PER = 2m 2Y1 1Y4 GND 2A1 74AC244 0 Comparison table VCC = 5.5V Measurement Simulation %Error VIH (V) 3.85 3.9328 2.151 VIL (V) 1.65 1.6447 -0.321 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 7. High Level and Low Level Output Voltage Circuit simulation result Output Input Evaluation circuit _ U1 1G VCC LO _ 1A1 2G LO 2Y4 1Y1 VOH 1A2 2A4 2Y3 1Y2 V2 V1 = 0.8 V2 = 2.2 V1 1A3 2A3 TD = 0.5m TR = 3n 2Y2 1Y3 3 TF = 3n I2 PW = 1m 1A4 2A2 PER = 2m -50u 2Y1 1Y4 GND 2A1 74AC244 0 Comparison table VCC = 4.5V Measurement Simulation %Error VOH (V) 4.5 4.4988 -0.027 VOL (V) 0 0 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 8. Propagation Delay Time Circuit simulation result Output Input Evaluation circuit _ U1 1G VCC LO _ 1A1 2G LO tplh 2Y4 1Y1 1A2 2A4 2Y3 1Y2 V1 = 0 V2 = 5 1A3 2A3 TD = 0.2u V1 V2 TR = 3.8n 2Y2 1Y3 R1 C1 TF = 3.8n PW = 0.5u 1A4 2A2 500 50p PER = 1u 5 2Y1 1Y4 GND 2A1 74AC244 0 Comparison table CL = 50 pF, RL = 500 Ω VCC = 5 V, tr = tf = 3 ns Measurement Simulation %Error tPLH (ns) 5.2 5.3997 3.840 tPHL (ns) 5.2 5.3093 2.102 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 9. Output enable time, high impedance (off) to high output (tPZH) Output disable time, high to high impedance (off) output (tPHZ) Circuit simulation result Output Input Evaluation circuit _ U1 1G VCC _ 1A1 2G HI HI tpzh_tphz 2Y4 1Y1 1A2 2A4 2Y3 1Y2 V1 = 0 V2 = 5 1A3 2A3 TD = 0.2u V1 C1 V2 TR = 3.8n 2Y2 1Y3 R1 R2 TF = 3.8n 50p PW = 0.5u 1A4 2A2 500 500 PER = 1u 5 2Y1 1Y4 GND 2A1 74AC244 0 Comparison table CL = 50 pF, RL = 500 Ω VCC = 5 V, tr = tf = 3 ns Measurement Simulation %Error tPZH (ns) 5.9 5.9927 1.571 tPHZ (ns) 5.5 5.5810 1.473 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 10. Output enable time, high impedance (off) to low output (tPZL) Output disable time, low to high impedance (off) output (tPLZ) Circuit simulation result Output Input Evaluation circuit _ U1 1G VCC _ 1A1 2G tpzl_tplz R2 LO HI 2Y4 1Y1 1A2 2A4 500 2Y3 1Y2 V1 = 0 V2 = 5 1A3 2A3 TD = 0.2u V1 C1 V2 V3 TR = 3.8n 2Y2 1Y3 R1 TF = 3.8n 50p PW = 0.5u 1A4 2A2 500 PER = 1u 10 5 2Y1 1Y4 GND 2A1 74AC244 0 Comparison table CL = 50 pF, RL = 500 Ω VCC = 5 V, tr = tf = 3 ns Measurement Simulation %Error tPZL (ns) 5.9 5.9775 1.314 tPLZ (ns) 5.5 5.5675 1.227 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005