1. PERFORMANCE ANALYSIS OF
A NETWORK BASED, ULTRAFAST
CENTRALIZED FAULT IDENTIFICATION AND
LOCATION SYSTEM
Advisor: Dr. Ming Yu
Co-advisor: Dr. Michael Steurer
Committee member: Dr. Hui Li
7/12/2016 1
Presenter: Shravan Tamaskar
M.S. Thesis Defense: 6 June 2016
2. Outline
Overview
– Motivation
– Objective and key contribution
Introduction to Centralized Fault identification and Location (CFL) system
architecture
Performance modeling of CFL system
Analyzing the factors affecting the CFL system performance
Validation: CFL demonstration and implementation
Conclusion and Future work
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3. Motivation: CFL
Fault management in
medium voltage direct
current (MVDC)
shipboard power system
(SPS) aimed to be
accomplished in 8 ms
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A need for
fast fault
identification
system
necessary
This led to the
development of
centralized fault
identification and
location (CFL)
system
8 ms
4. Objective
■ To develop a testbed for
an ultrafast fault
identification system for
the MVDC SPS
■ To model, analyze and
validate the performance
of the CFL system
■ To analyze the scaling
and the factors affecting
the CFL system
performance
Key Contribution
■ Modeling of
– EtherCAT Frame
– CFL decision time
■ Scaling of CFL system based on
– Frame
– Cycle time
■ Performance parameters
– Topology
– Preliminary noise analysis
■ Developed a CFL testbed and
implemented using different
system configurations
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5. 7/12/2016 5
Fault Management in MVDC SPS
Fault Management in MVDC SPS
Rapid fault identification
Fault
Identification
Fault Clearing
highly-coordinated interaction
Detect and
localize fault
Re-energize
system
De-energize
system
Isolate
faulted
segment
Detect &
locate
8 ms
6. Introduction to CFL architecture
■ CFL architecture
■ Differential protection scheme
■ CFL process description
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7. CFL architecture
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CS- Cable Section
PGM- Power Generation Module
Disconnect Switch
CS1 CS2 CS3
CS4
CS5CS6CS7
CS8
PG
M
PG
M
Load
Load
CFL
Power System
8. No Fault
Differential protection scheme
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Operates based on
Percentage Differential Protection (PDP) scheme
CS- Cable Section DS- Disconnect Switch
LIF test case
Slope diagram of protection scheme
DSA
DSA DS B
DS BCS
CS
Normal
Operation
During Fault
A
B
Time
msΔI
+Ia
-Ib
| 𝑛=2
𝑛
𝐼 𝑛| − 𝑆 . 𝑛=2
𝑛
|𝐼 𝑛| ≥ 𝐼𝑚𝑖𝑛
9. 7/12/2016 CAPS, FSU 9
Main parts of CFL system
A master unit with fault protection algorithm
Several slave units that perform data acquisition and send digitized
current data to master unit for decision making
A communication (EtherCAT) protocol governing master- slave
topology
Master
(Algorithm)
Line topology
Slave nSlave 1 Slave 2
Generic CFL system Architecture
EtherCAT Hardware CAPS Capability In-use
Master 1 1
I/O nodes 20 9
Slaves 6 6
13. Frame Modeling
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𝐷𝐺 𝑝𝑙 = (𝑛 𝐹𝑂 x 𝐿 𝐹𝑂 + 𝑛 𝐴𝐼 x 𝐿 𝐴𝐼 + 𝑛 𝐷𝑂 x 𝐿 𝐷𝑂 )
𝐿 𝐷𝐺 = 𝐷𝐺=1
𝐷𝐺
(𝐷𝐺 𝐻 + 𝐷𝐺 𝑝𝑙 + 𝐷𝐺 𝑤𝑘𝑐 )
𝐿 𝐹𝑟𝑎𝑚𝑒 = 𝐸 𝑇𝑦𝑝𝑒 + 𝐿 𝑐𝑚𝑑 + 𝐸𝑐𝑎𝑡 𝐻 + 𝐿 𝐷𝐺
Description Abbreviation Size (Byte)
EtherType 𝐸 𝑇𝑦𝑝𝑒 2
Commands 𝐿 𝑐𝑚𝑑 10
EtherCAT Header 𝐸𝑐𝑎𝑡 𝐻 2
Datagram Header 𝐷𝐺 𝐻 10
No. of Slaves 𝑛 𝑠𝑙𝑎𝑣𝑒𝑠 6
No. of Analog Input
channel
𝑛 𝐴𝐼
No. of Digital Output
channel
𝑛 𝐷𝑂
No. of Fiber Optic
connecter
𝑛 𝐹𝑂
Size of Analog Input 𝐿 𝐴𝐼 4
Size of Digital Output 𝐿 𝐷𝑂 3
Size of Fiber Optic
connecter
𝐿 𝐹𝑂 2
Datagram working
counter
𝐷𝐺 𝑤𝑘𝑐 2
14. Simulated number of frames
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𝑇𝑓𝑟𝑎𝑚𝑒 =
𝐿 𝑓𝑟𝑎𝑚𝑒 × 8
𝑏𝑤
Frame transmission time
nFrame = ceiling (
𝐿𝑒𝑛𝑔𝑡ℎ 𝑜𝑓 𝐹𝑟𝑎𝑚𝑒
1500
)
Time taken by the controller
to transmit the bits in the
frame
15. Cycle Time
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𝑇𝑐 = 2 × (( 𝑁 𝑇 + 1) × 𝑇𝑝+ 𝑇 𝑀
𝑓
+ (𝑁 𝑇 × 𝑇𝑆
𝑓
) + 𝑇𝑐
𝑝
)
Master
Slave
1
Slave
2
Slave
n
Defined as the time
necessary for the
exchange of input/output
data between the
controller and all
networked devices once
Simulated cycle time
Measured cycle timeMeasured cycle time
20.22 µs
16.73 µs
Number of slaves
Minimumcycletime(µs)
20.96 µs
16. Communication
System
Power System
CFL Testbed
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RTDS
SPS
Simulation
Slaves
AI, DO
Master
(Protection
algorithm)
Analog
Signals
Digital
Signals
Simulates
Fault
Initiates fault
clearing sequence
EtherCAT Packet
Simulation timestep- 50 µs
Cycle
Time
50 µs
M ss s
CS4
CS8
PGM Load
PGM Load
17. CFL decision time-
RTDS processing
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tRTDS = nproc step x tSimulationTimeStep
Time taken by RTDS (tRTDS) to process the
simulation logic and generate a signal which
goes out of RTDS analog output
Decision time
• RTDS
processing
• Beckhoff
processing
• Synchronization
mismatch
18. CFL Decision Time-
Beckhoff Processing
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The time taken by the beckhoff (tbeckhoff)
system to read the signals and compute the
algorithm and generate a response signal.
Cycle time (tct) 50 µsCycle time (tct) 100 µs
tbeckhoff = (niter + 1) x tct
600 µs
5 iterations (niter) for fault
identification,
(n+1) 6 timesteps
fault initiation signal
fault detection by CFL
300 µs
Yellow
-
Blue-
19. CFL Decision Time-
Synchronization mismatch
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19
Additional time added to the system operation due to simulation
delays and delays in the logic processing and hardware interfacing
tmismatch = thsm+ tbpd
RTDS
SPS
Simulation
Slaves
AI, DOAnalog
Signals
No sync
Beckhoff
processing
delay
(tbpd)
Hardware
Synchronization
Mismatch
(thsm)
Worst timing
2 cycle time
1 cycle
time Best
timing
20. CFL Decision Time
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Decision time is the sum of all the individual timings to detect a fault in the SPS
td = tRTDS + tbeckhoff + tmismatch
Fault initialization
RTDS output to slaves
CFL decision out
RTDS trip signal
Time (µs)
22. 1. Topology
– Line
– Ring
2. Jitter
3. Bandwidth
4. Network propagation time
5. Noise
– AWGN / SNR
– Noise on CFL System
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Performance parameters
23. Performance parameters- Topology
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Master Slave 1 Slave 2 Slave n
Ring topology
Additional/ return path
Master Slave 1 Slave 2 Slave n
Line topology
Return path
Tcycle = Tframe + Tnetwork
Advantages of Ring
topology
1. Resilient to 1
cable cut
condition
2. Additional path
for packet flow
3. Better cycle time
for large
systems
Theoretical minimum cycle time
24. Performance parameters- Jitter
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J = |Tc − Tcm|
TC - set cycle time
(eg. 50 µs)
Tcm - measured cycle time
Causes-
• Network
congestion
• Improper queuing
• Configuration
errors
Jitter can be described as latencies in the network
components which may result in the variation of the cycle
time
Jitter (simulated) per slave during the execution of the CFL
system configured at 50 µs
25. Performance parameters-
Bandwidth
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NRB =
|Tc − MCT|
Tc
× 100
MCT- Minimum cycle time
TC – set cycle time value
NRB- Non-realtime bandwidth
Line
Topology
Theoretical extrapolation showing the comparison of Fast Ethernet and gigabit Ethernet
The affect of bandwidth on
cycle time with respect to
slaves
Number of slaves
Minimumcycletime(µs)
Line
Topology
Number of slaves
Minimumcycletime(µs)
Fast Ethernet 100 Mbps
Gigabit Ethernet 1 Gbps
26. Performance parameters-
Network propagation time
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• Forwarding delays produced by slave devices
• Cable propagation delays
Theoretical network propagation time
networkpropagationtime(µs)
Number of slaves
27. Performance parameters-
Noise
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Additive White Gaussian noise SNR = 20 × log10(
𝑉 𝑠𝑖𝑔𝑛𝑎𝑙
𝑉 𝑛𝑜𝑖𝑠𝑒
)
Higher the SNR
Lower the noise in the
signal
Better the
measurement reading
Definition:
Noise is a random,
undesirable energy that
enters the
communication system
via the communicating
medium and interferes
with the transmitted
message
Preliminary analysis: Focused on
the effect of noise on the CFL
detection before the fault occurs.
Question:
Can noise create a false
identification?
Noise
Signal
Receiver
Signal +
Noise
31. SPS model
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1 MW PGM is interfaced to 5 kV MVDC bus
CS1 CS2 CS3
CS4
CS5CS6CS7
CS8
F I O
FIO
F
IO
F I O
F
I
O
Master
F
I
O
LOADInput signals (Current) from RTDS to Analog Input
Output signal from Digital Output to RTDS GTDI
Master Slave Connection (Fiber)
Disconnect Switch
CS- Cable Section
I –Analog Input Terminal
O–Digital Output Terminal
F –Fiber optic converter junction
F
I
O
Slave
UnitMMC LOAD
MMC 1
PG
M
PG
M
Load
Load
32. CFL Demonstration
7/12/2016 CAPS, FSU 32
t0 – RTDS simulation
logic processing
t1 – CFL decision time
t2 – synchronization
mismatch and
simulation logic
processing
CHIL implementation
of CFL system
t0
t1 t2
750 µs
time (ms)
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85
time (ms)
Fault Simulation
RTDS trip signal
33. Implementation
Condition Type Time (µs)
Fault impedance Low impedance fault
300
High impedance fault
Power system
configuration
Open ring
Closed ring
Loading condition 0.544 MW
0.125 MW
Operating modes VSM- CSM
VSM- VSM
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VSM- Voltage source mode
CSM- Current source mode
34. ■ Models to determine the performance and scaling of CFL
system were developed
■ Analyzed and discussed the factors affecting the CFL
performance
■ The effectiveness of the model has been verified.
■ A CFL, based on percentage differential protection,
demonstrates fault detection time of ~300 µs.
■ The CFL system was tested for various system operating
conditions and the results demonstrate its desired
performance
■ The ultrafast fault identification system paves the way to
accomplish fault management in the desired 8 ms time
frame
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Conclusion
35. ■ Hardware Implementation of a ring topology
■ Validating the system resiliency for cable cut condition
■ System level control
■ Exhaustive Noise analysis
■ Integrating multiple CFL units
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Future Work
36. References
1. Shravan Tamaskar, Harsha Ravindra, Mike Sloderbeck, Ruturaj Soman, and Michael Steurer.
"CHIL-based Demonstration of Centralized Fault Location Strategy for a MVDC Shipboard Power
System."
2. Qiu Deng, Xing Liu, Ruturaj Soman, Michael Steurer, and Roger A. Dougal. "Primary and backup
protection for fault current limited MVDC shipboard power systems." In Electric Ship Technologies
Symposium (ESTS), 2015 IEEE, pp. 40-47. IEEE, 2015.
3. Michael J. Thompson, "Percentage restrained differential, percentage of what?." In Protective
Relay Engineers, 2011 64th Annual Conference for, pp. 278-289. IEEE, 2011.
4. https://www.ethercat.org/
5. http://infosys.beckhoff.com/
6. Ziyuan Cai, and Ming Yu. "Modeling and Simulation of a Real-time Ethernet Protocol for Smart
Grids." International Journal Of Intelligent Control And Systems 17, no. 3 (2012): 69-78.
7. Mladen Knezic, Branko Dokic, and Zeljko. Ivanovic. "Topology aspects in EtherCAT networks."
In Proceedings of 14th International Power Electronics and Motion Control Conference EPE-
PEMC 2010. 2010.
8. B. P. Lathi (1968). Communication systems. New York, Wiley.
9. J. A. Betts (1970). Signal processing, modulation and noise. London, English Universities.
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Power system model, applying a fault identification system on the PS
Overlay of CFL system
Operating current is the vector sum of all the currents
Restraint current is the magnitude sum of all the currents in the particular system.
Experimental and theory differentiate in slides
Master configuration-
Understands the number of slaves connected in the topology,
The function of each slave (read/write,/ read&write)
Within the frames, the Working Counter enables the information in each datagram to be monitored for consistency. Every node that is addressed by the datagram and whose memory is accessible increments the Working Counter automatically. The master is then able to cyclically confirm if all nodes are working with consistent data. If the Working Counter has a different value than it should, the master does not forward this datagram’s data to the control application. The master device is then able to automatically detect the reason for the unexpected behavior with help from status and error information from the nodes as well as the Link Status.
Graph helps us understand the number of EtherCAT frames required wrt number of slaves in the system
Time taken by the controller to transmit the bits in the frame
Why the need?
This time is defined as the time necessary for the exchange of input/output data between the controller and all networked devices once, and is highly dependent on the used network topology.
I/O read/write
A/D conversion
Frame transmission
Network propagation
Why the need?
Round trip cycle time can help in understanding of the effects of number of slaves and cycle time
𝑇 𝑓 = ( 𝑁 𝐹 × 𝑆 𝐹𝐻 + 𝑆 𝐼𝐹𝐺 + 𝑁 𝑇 × 𝑆 𝑇𝐻 + 𝑆 𝑇 )× 𝑇 𝐵