RISC-V architecture introduction and its FreeBSD support

1. Arun Thomas: RISC-V Berkeley Hardware for your Berkeley
Software Distribution
notes by Scott Tsai
Outline
● Tour of ISA and ecosystem
● RISC-V 101
● hardware landscape (SoCs)
● software landscape
RISC-V
● uC to supercomputers, modular ISA
Origin of the ISA
● Krste et al wanted a common research ISA
● summer of 2010
● Frozen user specification May 2014
● Foundation, Aug 2015
(Of the foundation members, Mediatek and ANDES are Taiwanese companies)
ISA
● modular: simple base ISA plus extensions
● 32, 64, 128-bit (128-bit ISA has interest from Google and other cloud providers)
● <50 instructions in base
● Designed for extension/customization
ISA Overview
● base integer ISAs: 32I, 64I, 128I
● standard extensions: M(int mul/div), A(atomic), F, D(precision floating point), G(general purpose, equiv.
of IMAFD)
Reg File
● 32 GPRs (x0-x31)
● x0: zero reg
● x1: return address (used by jump and link etc)
● x2: SP
● x8: FP
● pc
Privilege Levels
● 0 User
● 1 Supervisor
● 2 Reserved (originally planned for hypervisor but the hypervisor model has since changed)
● 3 Machine (M-mode) firmware
○ only required level
Virtual Memory Architecture
● Paging for CPUs that support S-mode
● 4 level page tables
● Hardware TLBs. MMU hardware walks page table on TLB miss
● 32-bit, 39-bit, 48-bit Virtual Address
CSR: Control and Status Registers
● used for low-level programming
● Diff regs for OS(S-mode), firmware(M-mode)
Specs
● https://github.com/riscv/riscv-isa-manual

2. ● Userspace spec frozen, System level spec still undergoing development
Books
● Abacus and Quantitative Approach books etc by Patterson
Hardware Landscape
Free Chips Project (FCP)
● “Apache Foundation for chips”
● Rocket Core - 5 stage pipeline, single issue
Berkeley
● BOOM: out of order core
● Sodor: education (1-5 stage pipeline)
Rocketchip SoC Generator
● Parameterized SoC generator
● Written in Chisel HDL
● Can target C++ compiler and be built as a software simulator, FPGA or ASIC
SiFive Hardware
● Formed by RISC-V creators
● Cores (uC, multicore S-mode capable)
● FPGA devel kits
HiFive 1
● Arduino IDE support
● $59 USD
SiFive Freedom U500 Dev Board (Q1 2018)
● S-mode capable: good for operating system work
● 4x64-bit U54 gp cores and 1xE51 minicore
LowRISC
● completely open source SoC
● See Alex Bradbury’s FOSDOM2015 talk
● https://github.com/lowrisc
Shakti (IIT Madras)
● $60M funding to build 6 open-source cores
● Bluespec SystemVerilog HDL
More Cores
● PULPino
● PicoRV32
● SiFive, BlueSpec, MicroSemi etc
● Nvidia GPUs to include RISC-V uC
Software Landscape
Emulator/Simulator
● Spike (riscv-isa-sim) “golden model”
● QEMU
● RISCVEMU by Fabrice Bellard, in browser
● gem5
Spike vs QEMU
● Use Spike for hardware prototyping
○ easy to add instructions
● Use QEMU for software development
○ but there’s some work to be done
Toolchains
● binutils, upstream as of 2.28
● gcc, upstream as of 7.1
● clang/LLVM: rapidly progressing
○ Andes contributions (scott: Kito Cheng was in the room)
OS and Firmware
● Firmware: coreboot, UEFI

3. ● BSD: FreeBSD, NetBSD (work to be done)
● Linux
● Others: seL4, Genode, HelenOS, Zephyr, FreeRTOS, RTEMS, MyNewt etc
FreeBSD Port
● Ruslan Bukin
● Upstream as of 11.0
● RV64G and Sv39
● Uses gcc for now, looking to switch to clang
FreeBSD Resources
● wiki.freebsd.org/riscv
● #freebsd-riscv
● Ruslan’s RISC-V workshop talk
Resources
● Microprocessor Report articles
● ...
Summary
Question for Arun
● Where would you direct volunteer software development time in the RISC-V software ecosystem?
○ A: QEMU, LLVM