Micro controller

1. Microcontroller Architecture

2. ARM
2

3. What Is ARM?
• Advanced RISC Machine
• First RISC microprocessor
for commercial use
• Market-leader for low-power
and cost-sensitive embedded applications
3

4. RISC vs CISC
CICS
MULT 2:3, 5:2
RISC
LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A
CSE 477 Introduction to Microcontrollers 4

5. ARM Powered Products
5

6. Features
Architectural simplicity which allows
• Very small implementations which result in Very low power
consumption
• ARM processors are widely used in customer electronic devices such
as smart phones, tablets, multimedia players and other mobile
devices, such as wearable. Because of their reduced to instruction
set, they need fewer transistors, which enable a smaller die size of the
integrated circuitry (IC). The ARM processors, smaller size reduced
difficulty and lower power expenditure makes them suitable for
increasingly shrunk devices.
6

7. ARM Architecture
• Typical RISC architecture:
• Large register file
• Load/store architecture
• Simple addressing modes
• Uniform and fixed-length instruction fields
7

8. ARM Architecture (2)
• Enhancements:
• Each instruction controls the ALU and shifter
• Auto-increment
and auto-decrement addressing modes
• Multiple Load/Store
• Conditional execution
8

9. ARM Architecture (3)
• Results:
• High performance
• Low code size
• Low power consumption
• Low silicon area
9

10. Pipeline Organization
• Increases speed –
most instructions executed in single cycle
• Versions:
• 3-stage (ARM7TDMI and earlier)
• 5-stage (ARMS, ARM9TDMI)
• 6-stage (ARM10TDMI)
10

11. Pipeline Organization (2)
• 3-stage pipeline: Fetch – Decode - Execute
• Three-cycle latency,
one instruction per cycle throughput
11
cycle
Fetch Decode Execute
Fetch Decode Execute
Fetch Decode Execute
i
n
s
t
r
u
c
t
i
o
n
t t+1 t+2 t+3 t+4
i
i+1
i+2

12. Pipeline Organization (3)
• 5-stage pipeline:
• Reduces work per cycle =>
allows higher clock frequency
• Separates data and
instruction memory =>
reduction of CPI
(average number
of clock Cycles Per Instruction)
• Stages:
12
Write-back
Buffer/data
Execute
Decode
Fetch

13. Pipeline Organization (4)
• 6-stage (ARM10TDMI) of ARM7 comprises of following stages
1. Fetch: Cache access
2. Issue: Initiate instruction decode
3. Decode: Final instruction decode, register read for ALU
4. Execute: Data address calculation
5. Memory: Data cache access
6. Write: Register writes

14. Check Number of cycle required for this code
• int main()
• {
• int a, b, c;
• cout << "Enter two integers to addn";
• cin >> a >> b;
• c = a + b;
• cout <<"Sum of the numbers: " << c <<
endl;
• return 0;
• }

15. Interfacing

16. 16
• Embedded system functionality aspects
• Processing
• Transformation of data
• Implemented using processors
• Storage
• Retention of data
• Implemented using memory
• Communication
• Transfer of data between processors and memories or peripherals.
• Implemented using buses
• Called interfacing

17. 17
A simple bus
bus structure
Processor Memory
rd'/wr
enable
addr[0-11]
data[0-7]
bus
• Wires:
• Uni-directional or bi-directional
• One line may represent multiple wires
• Bus
• Set of wires with a single function
• Address bus, data bus
• Or, entire collection of wires
• Address, data and control
• Associated protocol: rules for
communication

18. 18
Ports
• Conducting device on periphery
• Connects bus to processor or memory
• Often referred to as a pin
• Actual pins on periphery of IC package that plug into socket on printed-circuit
board
• Sometimes metallic balls instead of pins
• Single wire or set of wires with single function
• E.g., 12-wire address port
bus
Processor Memory
rd'/wr
enable
addr[0-11]
data[0-7]
port

19. 19
Timing Diagrams
write protocol
rd'/wr
enable
addr
data
tsetup twrite
• Most common method for describing a
communication protocol
• Time proceeds to the right on x-axis
• Control signal: low or high
• May be active low (e.g., go’, /go, or go_L)
• Use terms assert (active) and deassert
• Asserting go’ means go=0
• Data signal: not valid or valid
• Protocol may have sub protocols
• Called bus cycle, e.g., read and write
• Each may be several clock cycles
• Read example
• rd’/wr set low, address placed on addr for at
least tsetup time before enable asserted,
enable triggers memory to place data on data
wires by time tread
read protocol
rd'/wr
enable
addr
data
tsetup tread

20. 20
Basic protocol concepts
• Actor: master initiates, servant (slave) respond
• Direction: sender, receiver
• Addresses: special kind of data
• Specifies a location in memory, a peripheral, or a register within a peripheral
• Time multiplexing
• Share a single set of wires for multiple pieces of data
• Saves wires at expense of time
data
serializing
address/data
muxing
Master Servant
req
data(8)
data(15:0) data(15:0)
mux demux
Master Servant
req
addr/data
req
addr/
data
addr data
mux
demux
addr data
req
data 15:8 7:0 addr data
Time-multiplexed data transfer

21. 21
Strobe protocol Handshake protocol
Master Servant
req
ack
req
dat
a
Master Servant
data
req
data
taccess
req
dat
a
ack
1. Master asserts req to
receive data
2. Servant puts data on bus
within time taccess
1
2
3
4
3. Master receives data and
deasserts req
4. Servant ready for next request
1
2
3
4
1. Master asserts req to
receive data
2. Servant puts data on bus and
asserts ack
3. Master receives data and
deasserts req
4. Servant ready for next request

22. 22
Advanced communication principles
• Layering
• Break complexity of communication protocol into pieces easier to design and
understand
• Lower levels provide services to higher level
• Lower level might work with bits while higher level might work with packets of data
• Physical layer
• Lowest level in hierarchy
• Medium to carry data from one actor (device or node) to another
• Parallel communication
• Physical layer capable of transporting multiple bits of data
• Serial communication
• Physical layer transports one bit of data at a time
• Wireless communication
• Physical interface with the wireless device/Antenna

23. 23
Serial communication
• Single data wire, possibly also control and power wires
• Words transmitted one bit at a time
• Higher data throughput with long distances
• Less average capacitance, so more bits per unit of time
• Cheaper, less bulky
• More complex interfacing logic and communication protocol
• Sender needs to decompose word into bits
• Receiver needs to recompose bits into word
• Control signals often sent on same wire as data increasing protocol
complexity

24. 24
Parallel communication
• Multiple data, control, and possibly power wires
• One bit per wire
• High data throughput with short distances
• Typically used when connecting devices on same IC or same circuit board
• Bus must be kept short
• long parallel wires result in high capacitance values which requires more time to charge/discharge
• Data misalignment between wires increases as length increases
• Higher cost, bulky

25. Parallel and Serial Communication
The basic difference between a parallel and a serial
communication channel is the number of electrical
conductors used at the physical layer to convey bits.
Parallel communication implies more than one such
conductor.

26. For example, an 8-bit parallel channel will convey eight bits (or a byte)
simultaneously, whereas a serial channel would convey those same bits
sequentially, one at a time. If both channels operated at the same clock
speed, the parallel channel would be eight times faster.

28. Comparison
• Speed
• Cable length
• Complexity (in terms of data transfer)

29. 29
Wireless communication
• Infrared (IR)
• Electronic wave frequencies just below visible light spectrum
• Diode emits infrared light to generate signal
• Infrared transistor detects signal, conducts when exposed to infrared light
• Cheap to build
• Need line of sight, limited range
• NFC
• Bluetooth
• Radio frequency (RF)
• Electromagnetic wave frequencies in radio spectrum
• Analog circuitry and antenna needed on both sides of transmission
• Line of sight not needed, transmitter power determines range

30. IR Communication

31. GSM Shield

32. Design Example
Temperature (i.e heating and cooling) control system of
a specified space without human intervention using
microcontroller which control the appliances according
to the change in environmental temperature and
buzzer and LCD to indicate the highest and lowest
condition.

35. Design Example
Design an appliances control system of your home, use mobile
application to control the devices even if your are not at home. Also
provide proper way of microcontroller communication with each
peripheral device. Incase of any extreme condition like fire, notification
will send at your phone.

36. 36
Error detection and correction
• Often part of bus protocol
• Error detection: ability of receiver to detect errors during transmission
• Error correction: ability of receiver and transmitter to cooperate to correct problem
• Typically done by acknowledgement/retransmission protocol
• Bit error: single bit is inverted
• Burst of bit error: consecutive bits received incorrectly
Parity: extra bit sent with word used for error detection
• Odd parity: data word plus parity bit contains odd number of 1’s
• Even parity: data word plus parity bit contains even number of 1’s
• Always detects single bit errors, but not all burst bit errors
Checksum: extra word sent with data packet of multiple words
• e.g., extra word contains XOR sum of all data words in packet

37. 37
Serial protocols: I2C
• I2C (Inter-IC)
• Two-wire serial bus protocol developed by Philips Semiconductors
Enables peripheral ICs to communicate using simple communication
hardware
• Data transfer rates up to 100 kbits/s and 7-bit addressing possible in
normal mode
• 3.4 Mbits/s and 10-bit addressing in fast-mode
• Common devices capable of interfacing to I2C bus:
• EPROMS, Flash, and some RAM memory, real-time clocks, sensors, timers,
and microcontrollers

38. 38
I2C bus structure
SCL
SDA
Micro-
controller
(master)
EEPROM
(servant)
Temp.
Sensor
(servant
Addr=0x
02
LCD-
controller
(servant)
Addr=0x0
3
< 400
pF
Addr=0x01
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
Start
condition
Sending 0 Sending 1 Stop
condition

39. Advantages of I2C
• Only 2 wires required for many devices
• Addressing set up by software allowing extra devices to be readily
added to system.
• Protocol requires acknowledge from slave so corrective action possible
if acknowledgement not received
Disadvantages of I2C Only suitable for short distances
• Relatively slow speeds/bandwidth
• Clock speed relatively slow
• Flexible addressing introduces significant overhead.
• No error checking.

40. 40
Serial protocols: CAN
• CAN (Controller area network)
• Protocol for real-time applications
• Developed by Robert Bosch GmbH
• Originally for communication among components of cars
• Applications now using CAN include:
• elevator controllers, copiers, telescopes, production-line control systems, and
medical instruments
• Data transfer rates up to 1 Mbit/s and 11-bit addressing
• Common devices interfacing with CAN:
• 8051-compatible 8592 processor and standalone CAN controllers