1. Phu Ho
Email: phudaiho@yahoo.com
Cellular Phone : (832)517-0104
12010 Dashwood Dr
Houston, TX 77072
KEY AREAS OF EXPERTISE
Technologies: Microsoft .Net frameworks 4.5.1, Visual Studio 2013, SQL Server 2012, Asp.net, MVC, Razor,
LINQ, Entity Framework, Object Oriented Concept, Agile methodologies, experienced with JQuery and AJAX.
Languages: C#, Javascript, T-SQL, HTML5, CSS3, VB, Perl, Verilog, VHDL, TCK.
PROFESSIONAL EXPERIENCE
Web Developer, February 2011 to Nov 2015, Dentex, Houston, TX
Primary responsibilities included:
• Implemented interactive and responsive web pages with AJAX.
• Experienced with generating views HTML5, CSS3, Razor, Bootstrap.
• Built web applications using Microsoft ASP.NET MVC Framework with C#, LINQ, EF in Visual Studio
2013.
• Created T-SQL queries with Microsoft SQL Server 2012.
Application Test Engineer, October 2008 to November 2010, DTM, Sugar Land, TX
Primary responsibilities included:
• Developed practical strategies for automating functional and regression testing.
• Designed, created, executed and maintained test cases and test plans.
• Participated in requirements reviews.
• Identified, isolated, reported and tracked defects in the defect tracking system.
Digital Hardware Engineer, January 2001 to August 2008, Teradyne, Minneapolis, MN
Primary responsibilities included:
♦ Modified existing ASIC designs to meet new requirements.
♦ Developed test plans, including creation of requirements, designs and documentation.
♦ Generated chip level and system level tests for new designs, documented test results and reported to
engineers following schedule guideline.
♦ Verified the design logic of the Behavioral, Register Transfer Level (RTL) and Gate levels to ensure each
level was equivalent to the others using Synopsys tool.
♦ Created boundary and internal scan test benches to verify package pins and registers function correctly.
♦ Generated vectors to test ASIC on Teradyne testers.
♦ Designed and thoroughly tested FPGA’s logic as required in simulation environments. Placed and routed the
logic, checked timing paths. Programmed FPGA, attached it to circuit boards and performed tests against
FPGA in real hardware environment to ensure requirements met.
EDUCATION
♦ Master of Information System Management, Keller Graduate School of Management of DeVry University,
Minneapolis, MN, April 2008
♦ Bachelor of Science, Computer Engineering – University of Minnesota: Institute of Technology,
Minneapolis, MN, December 2000
REFERENCES
Tai La Dentex Manager 832-878-6969
Manh Nguyen DTM INC Manager 281-564-7997
Edward Pulscher Teradyne Project Engineer 763-586-9010