1. The Impact of Timer Resolution in the Efficiency
Optimization of Synchronous Buck Converters
Pedro Amaral

2. Content
 Problem
 Proposed Solutions
 Motivation
 Hypothesis
 Analysis of Dead Time Optimization
 Experimental Implementation
 Conclusions

3. Content
 Problem
 Proposed Solutions
 Motivation
 Hypothesis
 Analysis of Dead Time Optimization
 Experimental Implementation
 Conclusions

4. Problem
 Synchronous Buck Converter
 DC to DC converter
 Voltage step down
 Current step up
 PWM driven (fs)
 Control switch
 Synchronous switch
 Feedback control

5. Problem
 CS conducts for ton
 SS conducts for toff
 Body diode conducts for td,r+td,f
 𝐷𝐶 = 𝑡 𝑜𝑛
𝑇𝑠
 𝑇𝑠 = 𝑡 𝑜𝑛 + 𝑡 𝑜𝑓𝑓 + 𝑡 𝑑,𝑟 + 𝑡 𝑑,𝑓

6. Problem
td too short td too long
 Dead time is necessary
 avoid short circuit
 avoid damage MOSFETs
 Dead time is harmful
 𝑃𝑐𝑜𝑛𝑑,𝐷 ≫ 𝑃𝑐𝑜𝑛𝑑,𝑄
 power efficiency reduction

7. Content
 Problem
 Proposed Solutions
 Motivation
 Hypothesis
 Analysis of Dead Time Optimization
 Experimental Implementation
 Conclusions

8. Proposed Solutions
Methods Advantages Disadvantages
Fixed Dead Time
• Easy
• Safe
• Non-optimized
Switching Current Sensing
• Optimized • Expensive current sensors
• Added components
Switching Voltage Sensing
(adaptive)
• Simple
• Optimized
• Added components
• Ineffective at high 𝑓𝑠
Switching Voltage Sensing
(predictive)
• Effective at high 𝑓𝑠
• Optimized
• Added components
• Complex
Sensorless
• No added components
• Optimized
• Slow optimization

9. Content
 Problem
 Proposed Solutions
 Motivation
 Hypothesis
 Analysis of Dead Time Optimization
 Experimental Implementation
 Conclusions

10. Motivation
 Digitalization of power supplies
 Explore new features:
 Diagnostics
 Communications
 Efficiency
 New answers for old questions
 Dead time problem
 Pressing global energy crisis

11. Content
 Problem
 Proposed Solutions
 Motivation
 Hypothesis
 Analysis of Dead Time Optimization
 Experimental Implementation
 Conclusions

12. Hypothesis
HRPWM
duty cycle (ton)
efficiency

13. Content
 Problem
 Proposed Solutions
 Motivation
 Hypothesis
 Analysis of Dead Time Optimization
 Experimental Implementation
 Conclusions

14. Analysis of Dead Time Optimization
 Average voltage across inductor L at steady state is 0 over a single period:
0
𝑇𝑠
𝑉𝐿 𝑑𝑡 = 0 ↔
𝑡 𝑑,𝑟
−𝑉𝐷 − 𝑉𝑜𝑢𝑡 𝑑𝑡 +
𝑡 𝑜𝑛
𝑉𝑖𝑛 − 𝑉𝑜𝑢𝑡 𝑑𝑡 +
𝑡 𝑑,𝑓
−𝑉𝐷 − 𝑉𝑜𝑢𝑡 𝑑𝑡 +
𝑡 𝑜𝑓𝑓
−𝑉𝑜𝑢𝑡 𝑑𝑡 = 0

15. Analysis of Dead Time Optimization
𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛
𝑡 𝑜𝑛
𝑇𝑠
− 𝑉𝐷
𝑡 𝑑
𝑇𝑠
output voltage
dead time
duty cycle
output voltage

16. Analysis of Dead Time Optimization
 Steps of any generic dead time optimization algorithm:
 𝑡 𝑘−1: ∆𝑡 𝑜𝑛 = 0 → ∆𝑉𝑜𝑢𝑡 = 𝑉𝐷
∆𝑡 𝑑
𝑇𝑠
 𝑡 𝑘: ∆𝑡 𝑑 = 0 → ∆𝑡 𝑜𝑛 = 𝑇𝑆
∆𝑉𝑜𝑢𝑡
𝑉 𝑖𝑛
 𝑡 𝑘+1: ∆𝑉𝑜𝑢𝑡 = 0 → ∆𝑡 𝑑 = ∆𝑡 𝑜𝑛
𝑉 𝑖𝑛
𝑉 𝐷
Algorithm operation point: (∆𝒕 𝒐𝒏, ∆𝒕 𝒅, ∆𝑽 𝒐𝒖𝒕)

17. Analysis of Dead Time Optimization
 Set of possible algorithm operation points of
the optimization algorithm:
𝒓 = ∆𝑡 𝑜𝑛, ∆𝑡 𝑑, ∆𝑉𝑜𝑢𝑡 = ∆𝑡 𝑜𝑛 ∙ 1,
𝑉𝑖𝑛
𝑉𝐷
,
𝑉𝑖𝑛
𝑇𝑠
∈ ℝ3

18. Analysis of Dead Time Optimization
 But variations are limited by the resources of the
controller (number of bits in ADC and timer):
 ∆𝑡 𝑜𝑛, ∆𝑡 𝑑 ≥ 𝑡 𝑚𝑖𝑛 → ∆𝑡 𝑜𝑛, ∆𝑡 𝑑 ≥
𝑇𝑠
2 𝑁 𝑡𝑖𝑚𝑒𝑟
 ∆𝑉𝑜𝑢𝑡 ≥ 𝑉 𝑚𝑖𝑛 → ∆𝑉𝑜𝑢𝑡 ≥
𝑉 𝐹𝑆
2 𝑁 𝐴𝐷𝐶
 Minimum O.P. → maximum algorithm resolution
 ∆𝑡 𝑑,𝑚𝑖𝑛 = 𝑇𝑆
𝑉 𝑖𝑛
𝑉 𝐷
max 2−𝑁 𝑡𝑖𝑚𝑒𝑟,
𝑉 𝐹𝑆
𝑉 𝑖𝑛
2−𝑁 𝐴𝐷𝐶

19. Analysis of Dead Time Optimization
 ∆𝑡 𝑑,𝑚𝑖𝑛 = 𝑇𝑆
𝑉 𝑖𝑛
𝑉 𝐷
max 2−𝑁 𝑡𝑖𝑚𝑒𝑟,
𝑉 𝐹𝑆
𝑉 𝑖𝑛
2−𝑁 𝐴𝐷𝐶
 𝜑 = 2−𝑁 𝑡𝑖𝑚𝑒𝑟 −
𝑉 𝐹𝑆
𝑉 𝑖𝑛
2−𝑁 𝐴𝐷𝐶
 𝜑 > 0
 operation point defined by 2−𝑁 𝑡𝑖𝑚𝑒𝑟
 timer restrained optimization
 ADC bits unused
 𝜑 < 0
 operation point defined by
𝑉 𝐹𝑆
𝑉𝑖𝑛
2−𝑁 𝐴𝐷𝐶
 ADC restrained optimization
 timer bits unused
timer restrained
optimization
ADC restrained
optimization

20. Analysis of Dead Time Optimization
 Resource usage is important… But what about power efficiency improvement?
 Initial power losses due to the existence of dead time:
 𝑃𝑙𝑜𝑠𝑠,𝑖 ≈ 𝑃 𝐷,𝑐𝑜𝑛𝑑= 𝑉𝐷 𝐼 𝑜𝑢𝑡 𝑓𝑠 𝑡 𝑑,𝑖
 For the minimum variation ∆𝑡 𝑑,𝑚𝑖𝑛:
 ∆𝑃𝑙𝑜𝑠𝑠,𝑚𝑖𝑛 = 𝑉𝐷 𝐼 𝑜𝑢𝑡 𝑓𝑠 ∆𝑡 𝑑,𝑚𝑖𝑛

21. Analysis of Dead Time Optimization
 Let 𝚿 be the ratio of eliminated and initial
power losses:
 Ψ =
𝑃 𝑙𝑜𝑠𝑠,𝑒𝑙𝑖𝑚
𝑃 𝑙𝑜𝑠𝑠,𝑖
 𝚿 in terms of the characteristics of the
controller:
 Ψ = 1 −
𝑇 𝑆
𝑉 𝑖𝑛
𝑉 𝐷
max 2−𝑁 𝑡𝑖𝑚𝑒𝑟,
𝑉 𝐹𝑆
𝑉 𝑖𝑛
2−𝑁 𝐴𝐷𝐶
2𝑡 𝑑,𝑖

22. Content
 Problem
 Proposed Solutions
 Motivation
 Hypothesis
 Analysis of Dead Time Optimization
 Experimental Implementation
 Conclusions

23. Experimental Implementation
 𝑉𝑖𝑛 = 12𝑉, 𝑉𝑜𝑢𝑡 = 1.8𝑉, 𝐼 𝑚𝑎𝑥 = 5𝐴, 𝑃𝑚𝑎𝑥 = 9𝑊, 𝑓𝑆 = 320𝑘𝐻𝑧, 𝑅 𝐿 = 0.5Ω

24. Experimental Implementation
 CCU8 (Capture and Compare Unit )
 12.5 nanosecond / 8 bits
 HRPWM (High Resolution Pulse Width Modulation)
 150 picosecond / 14.3 bits
 VADC (Versatile Analog-to-Digital Converter)
 NVIC (Nested Vectored Interrupt Controller)
 GPIO (General Purpose Input/Output)
Low Resolution
High Resolution

25. Experimental Implementation
 Output voltage control loop:
 sense 𝑽 𝒐𝒖𝒕 and compare to 𝑽 𝒔𝒆𝒕 = 𝟏. 𝟖 𝑽
 PI controller outputs new duty cycle
 add current dead time
 shadow transfer registers
 executed every ~𝟐𝟎 𝝁𝒔

26. Experimental Implementation
 Dead time optimization loop:
 compute average duty cycle (moving avg. filter)
 trigger at load change
 run twice (rising and falling edge dead time)
 start from 200ns fixed dead time
 gradient signs → region
 cross border → decrease step ∆𝑡 𝑑, change direction
 stopping condition ∆𝐷𝐶 < 𝜀 → controls precision/speed
 user defined minimum 𝑻𝑫 𝒎𝒊𝒏 → ensure safety

27. Experimental Implementation
duty cycle
falling edge
dead time
rising edge
dead time
rising edge dead
time optimization
falling edge dead
time optimization

28. Experimental Implementation
AfterBefore
PWM (CS)PWM (SS)Switching node voltage

29. Experimental Implementation

30. Experimental Implementation
Variable Low Resolution PWM
(12.5 𝑛𝑠)
High Resolution PWM
(150 𝑝𝑠)
𝑁𝐴𝐷𝐶 12 𝑏𝑖𝑡𝑠 12 𝑏𝑖𝑡𝑠
𝑁𝑡𝑖𝑚𝑒𝑟 8 𝑏𝑖𝑡𝑠 14.3 𝑏𝑖𝑡𝑠
𝑡 𝑑,𝑟,𝑜𝑝𝑡𝑖𝑚𝑢𝑚 25 𝑛𝑠 27.5 𝑛𝑠
𝑡 𝑑,𝑓,𝑜𝑝𝑡𝑖𝑚𝑢𝑚 25 𝑛𝑠 31.25 𝑛𝑠
𝑃 𝐷,𝑙𝑜𝑠𝑠,𝑒𝑙𝑖𝑚𝑖𝑛𝑎𝑡𝑒𝑑 72 % 98.6 %
∆𝜇 𝑐𝑜𝑛𝑣𝑒𝑟𝑡𝑒𝑟+𝑐𝑜𝑛𝑡𝑟𝑜𝑙 2.5 % 3.6 %
∆𝜇 𝑐𝑜𝑛𝑣𝑒𝑟𝑡𝑒𝑟 3.6 % 4.9 %
𝜇 𝑓𝑖𝑛𝑎𝑙,𝑐𝑜𝑛𝑣𝑒𝑟𝑡𝑒𝑟 95.1 % 96.1 %

31. Content
 Problem
 Proposed Solutions
 Motivation
 Hypothesis
 Analysis of Dead Time Optimization
 Experimental Implementation
 Conclusions

32. Conclusions
 First dead time optimization method using microcontroller unit
 Study of the influence of digital controller resources (timer) on dead time power efficiency
optimization
 Design of a simple, computationally light, no extra hardware and effective algorithm
 𝟓 % improvement over a fixed dead time solution
 𝟏 % improvement over low resolution solution

33. Thank you.