PavanKumar S

Hyderabad Area, India India

Experienced in Digital Design Verification (SoC & IP) using SV-OVM/UVM

Electronics / Computer Hardware

Experience in SoC Functional verification at both block and system level. Hands on experience on System Verilog based test bench development. Experience in Functional coverage and code coverage. Experience in RTL/Gate level verification and debugging. Involved in two chip tape-outs (PSoC3 & PSoC5). Worked on Assertion based verification. Experience working with teams across the globe. Experience in Perl/Shell scripting.