1. ISSN 1688-2784
Universidad de la República
Facultad de Ingeniería
RF Power Ampliers with Built-In
Test and Calibration in Nanometer
CMOS
Tesis presentada a la Facultad de Ingeniería de la
Universidad de la República por
Nicolás Barabino Espinosa
en cumplimiento parcial de los requerimientos
para la obtención del título de
Doctor en Ingeniería Eléctrica.
Director de Tesis
Prof. Fernando Silveira Noguerol...... Universidad de la República
Tribunal
Prof. Adoración Rueda Rueda (Revisor Externo) ... Universidad de
Sevilla (España)
Prof. Carlos Galup-Montoro (Revisor Externo)....... Universidade
Federal de Santa Catarina (Brasil)
Prof. Agdo. Alfredo Arnaud Maceira ..... Universidad Católica del
Uruguay
Director Académico
Prof. Fernando Silveira Noguerol...... Universidad de la República
Montevideo
2 de Marzo de 2015

2. Abstract
This thesis deals with the design of RF Power Ampliers (RFPAs) in nanometer
CMOS technologies, in the context of ultra low power wireless applications. The
current trend of designing CMOS RF Systems-on-Chip (SoCs) enables a new era
of low cost RF systems. However, along with its benets of integration density and
higher operation frequencies, nanometer CMOS processes present several challenges
like strong process variability, that require a variability aware design.
A method for designing RFPAs is presented, which aims to speed-up the design
process and provide insight to the designer, by using a semiempirical MOSFET
model extracted from simulations. The method considers transistor character-
istics normalized to the transistor width (considering minimum length devices),
and the parasitics of the passive components. This method was tested on IEEE
802.15.4/Bluetooth Low Energy 2.4 GHz compatible RFPAs in 90 nm CMOS. The
measurements show that the characteristics can be accurately predicted and opti-
mized, thus reducing design iterations. The fabricated designs also contribute to
the state of the art showing that higher eciencies can be achieved.
Due to the strong process variability a stringent RF production testing is re-
quired in nanometer CMOS. This has fueled the advent of RF Built-in-Self-Test
(BiST), which intends to replace the external testing instruments with internal
measurements, thus reducing costs. This technique is also encouraged by the avail-
ability of plenty of digital resources in current SoCs, which provide means to control
and analyze the self test. Furthermore, the self test can lead to self healing by im-
plementing Built-in-Self-Calibration (BiSC).
In this work it was studied the RF Amplitude Detector block, which is funda-
mental for the implementation of BiST/BiSC. A novel method for modeling and
optimizing a detector design is proposed, which is also based on semiempirical
MOSFET models. Additionally, a new digital correction technique is also proposed,
which allows extending the dynamic range with high tolerance to process varia-
tions. This technique relies in extensive statistical data obtained by simulations.
The dynamic range extension was shown experimentally with several samples of a
90 nm design, showing that the detector area, power consumption and variability
tolerance can be improved considerably.
Finally, BiST and BiSC for an RFPA with minimal area and power overhead are
experimentally demonstrated. This illustrates the convenience of these techniques
in low-power wireless SoCs, a segment where, up to the best of our knowledge there
are very few BiST/BiSC enabled systems.