121802.Electra4

www.sti-america.com enabling advanced integrated circuits
Electra BGAElectra BGA™™ – Coreless Flip Chip Substrates– Coreless Flip Chip Substrates
December 2002December 2002
www.sti-america.comwww.sti-america.com enabling advanced integrated circuitsenabling advanced integrated circuits

Future Device ConsiderationsFuture Device Considerations
Feature / YearFeature / Year 2002 2003 2004 2005 2006 2010
Min. BGA Solder
Ball Pitch (mm)
1.00 0.80 0.80 0.65 0.65 0.50
Average Body Size
(mm)
37.5 33.0 33.0 29.0 29.0 27.0
Maximum Substrate
I/O Count
1,369 1,600 1,600 1,936 1,936 2,809
Min. In-Line Pad
Pitch (micron)
35/35 30/30 25/25 20/20 20/20 20/20
Flip Chip market divisible into three segments
Form Factor driven (portable devices with limited I/O)
Electrical performance driven (high speed devices with signal integrity and power distribution
challenges)
Density driven (logic devices with higher I/O counts)
Main obstacle to deployment is cost penalty (target >$0.005 per I/O) relative to wire bond
Majority of performance and cost obstacles lie within substrate infrastructure
Highlights from 2001 SIA Roadmap
Orange boxes = probable flip chip / White boxes = flip chip is inevitable

Challenges For Sub 200 μm Flip Chip Pitches
Density
Must duplicate die pad pitch at 1st
interface level
Must provide low-cost, reliable micro-vias for I/O distribution
Must provide multiple layers for I/O & Power/Ground distribution
Must satisfy co-planarity requirements of assembly process
Must deliver density at a high yield (multilayer >90%)
Performance – Electrical and Thermal
Maintain signal integrity through different materials sets
Provide clean power and ground reference planes
Integrate thermal management to ensure die performance
Mechanics
Shorten paths to termination within substrate
Provide structural options to accommodate secondary thermal mgmt
Cost
Substrate ChallengesSubstrate Challenges

Electra BGA Value PropositionElectra BGA Value Proposition
Coreless high speed structure incorporating stacked via-on-pad
Unique additive circuitization process delivering sub 30µm line/space
Optimized “Managed Yield” process flow for maximum cost control
Custom AttributesCustom Attributes
Cost effective design and tooling charges
Standardized process, material and manufacturing equipment set
Highly repeatable / controllable process
Base technology applicable to future needs
Incremental capacity easily added and supported
Mass ProductionMass Production AttributesAttributes
To deliver high performance, application specific substrates in a
format compatible with existing assembly infrastructure, using mass
production techniques that maximize performance to cost ratios.
ObjectiveObjective

Electra BGA PlatformElectra BGA Platform
Inverted “additive” circuitization process
Stacked 90µm laser vias
Large panel fabrication (18" x 21")
Solid vias for maximized I/O distribution
One to six circuit layers
Build-up on Build-up layering – no glass cores
Drivers: Cost/Density Performance
4 Metal Layer Structure
Additive Circuit
Stacked Via

Electra Process HighlightsElectra Process Highlights
Layer Pair CombinationLayer Pair Combination
Via Formation and InterconnectVia Formation and Interconnect Platform Release and Final FinishPlatform Release and Final Finish
Layer Pairing and CureLayer Pairing and CureAdditive Circuit FormationAdditive Circuit Formation
Dielectric Application and Circuit EmbedDielectric Application and Circuit Embed

Electra Platform Material SelectionElectra Platform Material Selection
Dielectric Material
Properties Test Method Typical value
Electrical
Dielectric constant (Dk)
500 Mhz 3.4
2.9 Ghz 3.4
10 Ghz 3.4
20 Ghz 3.3
40 Ghz 3.3
Loss Tangent (Df)
500 Mhz 0.008
2.9 Ghz 0.008
10 Ghz 0.008
20 Ghz 0.008
40 Ghz 0.008
Mechanical
Tensile modulus @ 25C (77F) 12.2 Gpa
Moisture absorption 24 hr immersion @ 20C 0.17% w/w
Peel strength (17 micron copper) IPC TM650 method 2.4.9 0.6 Kg/cm (3.2 lb/in)
Coeficient of thermal expansion (CTE) TMA (-55 to +125C) 19 ppm/C (X,Y,Z)
Thermal
Glass transition temperature (Tg) TMA 220C (428F)
Thermal conductivity ASTM E 1530 @ 20C 0.46 W/m*C
Flammability UL 94 VO

Stiffener material
Property Alloy
Density (Lbs/cu” @68°F) 0.322
Modulus of Elasticity (psi) 17 E+ 6
Electrical Conductivity (%IACS @68°F) 60
Thermal Conductivity (BTU/sq ft/hr/F@68°F) 150
Coefficient of Therm Expan (In/°F from 68°F to 572°F 9.7 E- 6
Tensile Strength (x1000 psi) 60 – 70
Yield Strength (x1000 psi) 60
Elongation (nom. % in 2”) 7
Nominal Composition (99% min Cu)

Property Unit Condition Typical value
Cured thickness µm (mils) ----- 120 (4.7)
Tensile Modulus Mpa (ksi) -40°C (-40°F) 210 (30)
24°C (75°F) 64 (9.2)
110°C (230°F) 12 (1.7)
200°C(392°F) 6.5 (0.9)
Dielectric constant (Dk) ----- 1 Mhz-LCR method 2.0
Loss Tangent (Df) ----- 1 Mhz-LCR method 0.008
Resin flow mm 130°C; 1 mPa; 2 sec 0.03
(mils) 293°F; 145 psi; 2 sec) (1.2)
Peel strength n/cm 180° peel 12
(lb/in) 35µm ED foil (6.9)
Volatile content wt % 160°C, 15 min 0.10
Flammability ----- UL-94 VTM-0
Tg °C (°F) TMA 155 (311)
Solder heat resistance ----- 260°C, 30 sec Pass
(500°F, 30 sec)
CTE ppm/°C TMA 55
Stiffener attach adhesive

Surface finish
ENTEK ENTEK + 1 reflow
T-life
Initial compliant resistance
Max change 1000 hrs
1.5 mΩ
<+0.9 mΩ
1.5 mΩ
<+1.0 mΩ
Humidity cycle
Max change 500 hrs
1.4mΩ
<+0.6mΩ
1.6 mΩ
<+0.8 mΩ
MFG
Max change 10 days
1.5 mΩ
<+0.6mΩ
1.5 mΩ
<+0.7mΩ
IR humidity
Final 500 hrs
>.50,000
25,000
>.50,000
25,000
Resistance Per
IPC SIR
Initial
Biased
24 hr
Biased
96 hr
Biased
168 hr
Biased
Control 7.29 X 10 9
1.19 X 10 10
1.38 X 10 10
1.44 X 10 10
Entek 106-A 3.88 X 10 10
2.14 X 10 10
2.41 X 10 10
2.09 X 10 10
Entek106+1reflow 9.36 X 10 9
1.36 X 10 10
1.59 X 10 10
1.27 X 10 10
ANSI/EIA-364-C
Thermal life: 1000 hours at 105 °C
Humidity cycle: 500 hours at 25-65°C and over 90% RH
Mixed flowing gas: 10 days at 30°C and 70% RH
IR humidity: 500 hours at 85°C, 85% RH and 100 V bias

EFC - Formed Feature CapabilityEFC - Formed Feature Capability
Note: Picture depicts 3 rows distributed on die interface layer.
Inner rows distributed with non-stacked via.
H

EFC - Die Interface OptionsEFC - Die Interface Options
Number Max rout lines
of bump In-line Row Staggered Bump pad Via capture Line Space between pads
Conf. Name pad rows pitch pitch pitch diameter Outer Internal Outer Internal Outer Internal outer lyr
A Single row , in-line pitch
1 115 um 85 um 100 um 30 um 30 um 0
B
Tw o row , in-line pitch
w /via offset
2 150 um 115 um 85 um 100 um 160 um 30 um 40 um 30 um 50 um 0
C Tw o row , in-line pitch
D
Tw o row , staggered
pitch
2 175 um 85 um 85 um 85 um 100 um 160 um 30 um 40 um 30 um 50 um 1
E
Three row , in-line pitch
w /via offset
F Three row , in-line pitch
G
Three row , staggered
pitch 3 235 um 115 um 57.5 um 85 um 100 um 160 um 30 um 40 um 30 um 50 um 2
Sample routing capabilities - 2003Sample routing capabilities - 2003










Development
Development
Development
Development
Development
Development
Development
Development
Development
0.190 mm
0.100 mm
1.00 mm
2 Per Layer
0.160 mm
0.090 mm
0.030 / 0.030
Laser
Electra
0.180 mm
0.090 mm
0.80 mm
2 Per Layer
0.150 mm
0.080 mm
0.030 / 0.030
Laser
Electra
0.155 mm
0.080 mm
0.65 mm
2 Per Layer
0.140 mm
0.0750 mm
0.025 / 0.025
Laser
Electra
0.140 mm
0.080 mm
0.50 mm
2 Per Layer
0.120 mm
0.050 mm
0.020 / 0.020
Laser
Electra
20022002 20032003 20042004 2005 20062005 2006Feature / Year
Bump Pad Pitch
Bump Capture Pad Diameter
Solder Ball Pitch
Internal Via Capture Pad Diameter
Via Diameter
Circuit Line/Space Dimensions
Via Formation Method
Circuit Formation Method





Bump Pads For
Die Attach –
Copper/OSP
Or Solder
Finish
Solder Ball
Pads –
OSP, Silver or
Tin
Finish
Electra FCBGA Feature Road MapElectra FCBGA Feature Road Map

$0.00
$2.00
$4.00
$6.00
$8.00
$10.00
$12.00
$14.00
$16.00
$18.00
$20.00
2000 2001 2002 2003 2004 2005
SIA Min SIA Max Electra Lo Electra Hi
SIA 1,000 I/O Assembled Package Versus Electra FC 1,000 I/O SubstrateSIA 1,000 I/O Assembled Package Versus Electra FC 1,000 I/O Substrate
Electra FCBGA™ Substrate PricingElectra FCBGA™ Substrate Pricing
Electra Lo = 35 mm substrate, 2+2 Layers
Electra Hi = 35 mm substrate, 2+2+2 Layers
SIA Forecasted Price
(Substrate + Assembly)
High End
Low End

Program MilestonesProgram Milestones
Milestone Available Date
Reliability and Integrity
Precondition MSL Level III December 5, 2002
Temperature Cycle Condition B
500 hours January 24, 2003
1000 hours February 13, 2003
96 Hour Bias HAST January 31, 2003
96 Hour PCT January 17, 2003
1000 Hour HTS February 13, 2003
Design Rules – Initial Release December 19, 2002
Release Pricing Matrix March 15, 2003
Customer Sampling – Production Site Q2 2003
Production Site Qualification Q3 2003

Electra Substrate ConclusionElectra Substrate Conclusion
Controlled dimensional stability for large panel process
Unique interconnect scheme eliminates mechanical via
Additive circuit process results in high yield at density
Variety of affordable dielectric platforms
Buried “via-under-pad” approach maximizes rout room
Thin structures for decreased inductance & impedance
Optimized electrical performance thru dielectric options
Planer circuit technology gives maximum line integrity
Core-less structure for optimized routing and
performance
Low capital expense manufacturing process
Scalable up or down based on I/O requirements
Tailorable for die-up or die-down applications, and flip
chip or wire bond interconnect
Cost AdvantagesCost Advantages
Performance AdvantagesPerformance Advantages
Scalability AdvantagesScalability Advantages

121802.Electra4

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