Justin Yuan is an electrical engineer seeking new opportunities. He has a Master's degree from Wright State University and a Bachelor's from Dalian Jiaotong University. His projects include designing an 8-bit ALU and optimizing a 32-bit adder/subtractor. He has work experience as an English instructor and university assistant. Yuan has strong skills in digital design, circuits, FPGA, and software tools like Cadence and Xilinx. He actively participated in student organizations to share his cultural experiences.

1. Justin Yuan
1150 White pine Terrace, Sunnyvale, CA
Phone: 937-432-8872
Email: yuan.15@wright.edu
Education
Wright State University, Dayton, Ohio September 2013 – July 2015
Master of Science in Electrical Engineering
Dalian Jiaotong University, Liaoning, China September 2009 – July 2013
Bachelor of Science in Electrical Engineering and Automation
Projects
8-bit Arithmetic-Logic-Unit Design
 Designed 8-bit Arithmetic-Logic-Unit (ALU) schematic by using transistor level (TSMC 180nm).
 Used arithmetic extenders and logic extenders to modify logic operations.
 Demonstrated success as the ALU performed the basic arithmetic and logic operations in a microprocessor.
Booth Multiplier Design and Time Optimization
 Implemented transistor level (TSMC 180nm) as the fundamental building blocks.
 Optimized the sizing of each transistor-level circuit block and handcrafted layout to decrease area.
 Simulated the waveform to determine propagation delay and verify function.
Optimization of 32-bit Adder/Subtractor
 Designed a 32-bit Adder/Subtractor with carry-in and carry-out by transistor level (TSMC 180nm).
 Implemented 32-bit Adder/Subtractor by 1-bit 28-T adder and 1-bit mirror adder for decreasing delay.
 Applied critical path Isolation method to boost the clock frequency by 20% and scale down overall power consumption
by 15%.
Sequential Circuit Testing
 Applied Iterative Logic Array (ILA) multiple time-frame method for sequential circuit test generation.
 Used Synopsys TetraMax to determine test patterns of the Iterative Logic Array time-frame circuit.
Work Experience
Right Education May 2014 – June 2014
English Instructor Shenyang, Liaoning
 Prepared class materials and lesson plans for Middle School and High School students.
 Lectured English Linguistics with a focus in pronunciation and listening skills.
 Demonstrated strong improvements with 70% satisfaction rate in Speaking and Listening, as well as a 60% increase in
exam grades.
Dalian Jiaotong University September 2011 -– June 2013
Assistant & Translator Dalian, Liaoning
 Assisted in administrative duties for the Director of International Communication Department.
 Translated syllabus and course materials from Wright State University.
 Received exchange students from Wright State University and provided necessary support such as cultural education.
Skills
Specialties: CMOS VLSI Digital Design, Circuit Design (Analog and Digital Circuits), FPGA (Xilinx Virtex 6)
Tools: Cadence 6.1.5, VHDL, Verilog, Xilinx ISE (FPGA), Synopsys TetraMax, MATLAB, C/C++, Linux, Microsoft Office.
Activities
 Served as student representative from Dalian Jiaotong University while studying at Wright State University and
exchanged learning experience with local students.
 Participated in the Guitar Spirit Club and performed at Graduation Ceremonies.
 Organized Holiday parties as well as other group activities for exchange students.
 Participated in WSU-CSSA dragon dance team which provided an excellent opportunity to introduce Chinese culture
to the student communities.
 Introduced various cultural identities by preparing traditional Chinese food at Dayton International Affair, which
attracted more than 30 students and faculties to join the Chinese Club.