This document discusses a proposed novel design for a FIR filter using a hybrid adder and Booth multiplier based on the Gate Diffusion Input (GDI) technique. FIR filters are commonly used in digital signal processing due to their linear phase response and inherent stability compared to IIR filters. The proposed design aims to reduce power dissipation by using GDI techniques in the adder and multiplier circuits to lower switching activity, as traditional Wallace and Booth multiplier designs have higher power consumption due to multiple addition stages in the partial products. The performance of the proposed GDI-based FIR filter will be analyzed and compared to a traditional design using Cadence simulation tools.

2. Abstract
• In this paper, a novel FIR filter is designed using GDI technique-based hybrid adder and booth
multiplier.
• Digital filters are classified into two types namely, Finite Impulse Response (FIR) and Infinite
Impulse Response (IIR).
• Due to the linear phase response and inherent stability, FIR filters are more commonly used than
IIR filters.
• The digital filter primarily separates the unwanted signal from the wanted signal.
• Hybrid adder is the combination of two adders or having a logic style design in the existing adder.
• The multiplier using the Booth algorithm is a well-known technique for high-speed and low-cost
multipliers.
• The FIR filter design will compared with Modified FIR Filter design(GDI Method).
• The Performance analysis done by cadence virtuoso schematic tools.

3. Introduction
• Hardware with high efficiency are required to cope up with the rapid
growth in digital signal processing applications.
• Digital filters are used for computation, band selection, signal
preconditioning, signal analysis and estimation, etc. Digital filters are
classified into two types namely, Finite Impulse Response (FIR) and
Infinite Impulse Response (IIR).
• Due to the linear phase response and inherent stability, FIR filters are
more commonly used than compared to IIR filters.
• The digital filter primarily separates the unwanted signal from the
wanted signal

4. Existing system
• Fir filter adders and multiplier designed by convolutional methods.
• Booth and Wallace multiplier algorithm will be used

5. FIR Filter design
𝑦 =
𝑘=0
𝑀
ℎ 𝑘 𝑥(𝑛 − 𝑘)
Y = output response
H = coefficient
X = Input signal
N = no of Tap filter

6. Convolutional cmos circuit
AND GATE OR GATE XOR GATE

7. 7
Multiplication Algorithm*

8. 8
Tree Multipliers

9. Problem statement
• Wallace and booth multiplier have more power dissipation due to
more stages of addition in partial products.
• Convolutional cmos logic will consum more switching activity.

10. Proposed system
• In this project we are going design FIR filter with GDI techniques.
• We are using GDI techniques in adder and multiplier circuit to reduce
switching activities.

11. GDI technique circuit

12. Cadence design results

13. Applications
• DSP applications
• Memory applications
• 5G applications