1. 1www.siliconaccess.com ISQED - March 25, 2003
The iFlow Design Factory:
Evolving Chip Design from an Art to a Process,
through Adaptive Resource Management,
and Qualified Data Exchange.
Gilles-Eric Descamps, Satish Bagalkotkar, Subramanian Ganesan,
Sridhar Subramaniam, Hem Hingarh
{First-Name.Lastname}@SiliconAccess.com

2. 2www.siliconaccess.com ISQED - March 25, 2003
Challenges
 Fast-growing startup
– Multi-site Design Teams
 Meet time-to-market
 iPP Design Complexity
– 20 Gb/s network processor, 12.8 Gbps links
– 256 simultaneous threads by 32 NPUs
– large memory blocks (SRAM & CAM)
– 175M transistors, 17M gates, 333MHz
 + iAP, +iAC, + iCL, +...

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Design Data Growth
 First design in Oct’00 used 17GB
 Last Design in Apr’02 using 1024GB

4. 4www.siliconaccess.com ISQED - March 25, 2003
Principles
 PDCA (Plan, Do, Check, Act)
– comes from Total Quality Management
 CMM (Capability Maturity Model)
– 1: firefighting, Heroics
– 2: Repeatable
– 3: documented stable Standard process
– 4: Managed, instrumented
– 5: Optimizing, remove waste

5. 5www.siliconaccess.com ISQED - March 25, 2003
Deployed two techniques
 Adaptative Resource Management
– shift on the fly
– managed, optimizing
 Qualified Data Exchange
– stable, instrument, document

6. 6www.siliconaccess.com ISQED - March 25, 2003
Adaptative Resource Management
 storage
 compute
 tools
 social factors

7. 7www.siliconaccess.com ISQED - March 25, 2003
Storage
 Highly available
– no breakdown, no maintenance
 Robust
– quota, snapshot
 Transparent
– Unix / MS-Windows, mirroring
 We used
– NetApp, Linux/IDE/RAID/LVM/ReiserFS

8. 8www.siliconaccess.com ISQED - March 25, 2003
Compute
 Chosen on EDA tool availability & cost
 Abstract Hardware
– from: rlogin goliath to:
– run -r “sun7 RAM/20000 Apollo” myjob
– Describe needs
 Job Persistency

9. 9www.siliconaccess.com ISQED - March 25, 2003
Environment / Tools
 Environment
– normalized
– one place for each thing
– one company
– one CAD team
 Tools
– Gather statistics
– Global License Broker
•Platform LSF, or rtda FT/NC

10. 10www.siliconaccess.com ISQED - March 25, 2003
Usage improvement

11. 11www.siliconaccess.com ISQED - March 25, 2003
Social Factors
 Intranet website
– company documents
– project overview
 Single shared VNC environment
– collaboration, take-home, hand-over
 Capture knowledge in scripts
 Reporting tools

12. 12www.siliconaccess.com ISQED - March 25, 2003
Qualified Data Exchange
 Exchange / Release
 Automation & Knowledge Capture
 Metrics
 Thresholds & Color-Coding
 Dig-around Overview

13. 13www.siliconaccess.com ISQED - March 25, 2003
Exchange / Release
 No more email attachments
 publishing procedure
– remove ownership of file when published
 track 4W
– Who, When, What, Why
 documented -> mirrored

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Automation & Knowledge Capture
 No more: “go ask George”
 capture best practices
 reactive support/CAD team
 ensure use
 scripted, fully automated

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Metrics
 No EDA-standard metrics
 Defined our own
– # gates, # nets
– utilization
– slack, clock skew
 Instrument
 Test Cases
– spectrum, regression

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Thresholds & Color-Coding
 After instrumenting, qualifying
 experts define thresholds
 color-coding
– good, bad

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Dig-around Overview
 Webpage simple & effective
 color-coded overviews
– streamlining
 availability
 information drill-down

18. 18www.siliconaccess.com ISQED - March 25, 2003
Application
 IP core/macro catalog
 RTL nightbuild
 Physical Design Flow

19. 19www.siliconaccess.com ISQED - March 25, 2003
IP core/macro catalog
 Several hundred hard macros
 dozen of chips
 several engineering teams
– layout, schematic, logic
 need:
– a tracking mechanism
– but also a training device
– status / certification
– simplify work

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Single Core Overview
 Document, Track, Qualify
 autogenerated views
 Queue jobs (QA, gen)

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All cores overview per project

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RTL nightbuilds
 a software engineering practice
 RTL = software QA
– lint
 Synthesis build = metrics
 Verification
– daily fresh base
 Project Status for all / Visibility

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Daily liveness status

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Single-click access

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Physical Design Flow
 Knowledge Capture
– dozen of complex tools
– lots of steps
 Full Automation
 Dependency / Status graph
 Exits / Release
 web status

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physical block flow graph
 r t d a Flowtracer

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Physical Block Overview

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Spice clock slew mapped to layout

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Chip Integration
 iPP final GDS = 8 GB
 need 64-bit everything
 trusted change control
 distribution & parallelism
 no unexpected surprises
– on-time, on-schedule

30. 30www.siliconaccess.com ISQED - March 25, 2003
Conclusion
 Two quality enhancement techniques
– adaptative resource management
– qualified data exchange
 closed-loop practices
 no-cost status updates
 ALL four complex chips shipping for
revenue from first-silicon
 predictable schedule