1. Training course for Artlink
2014.07.22
MM1 蔡嘉洋
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2. Outline
 Display Port introducing
 (e)DP2LVDS introducing
 DP2VGA introducing
 RTD tool using introduction
 Q&A
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3. Display Port Introducing
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4. Display Port Introducing
• VGA and DVI are to be replaced by DisplayPort
• The PC industry plans to phase out VGA and DVI over the next
few years.
• Now integrated into all main-stream GPU’s and integrated GPU
chip sets
• Being applied to other interface applications
• Embedded DisplayPort (eDP) is the new interface for internal
display panels, replacing LVDS
• DisplayPort is being enabled in hand-held applications
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5. Display Port Introducing
• Application within PC and consumer electronic (CE) devices
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6. Display Port Introducing
• Main Link：uni-directional, used to transport isochronous data
streams
• AUX CH：half-duplex bidirectional, used for link management and
device control
• Hot Plug Detect ：serves as an interrupt request by the Sink
Device.
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7. Display Port Introducing
Main Link
• Lane Count：1, 2 and 4 lanes
• Rate：
 High Rate：2.7Gbps
 Low Rate：1.62Gbps
• Code Rule：8B/10B
• Component bit depths：6, 8, 10, 12, and 16
• Formats： RGB, YCbCr 4:4:4 / 4:2:2
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8. Display Port Introducing
Aux CH
• Channel coding： Manchester II
• Rate：1Mbps
• Link Services：Link discovery, Configuring, Maintenance
 Link capability read
 Link configuration (training)
 Link status read
• AUX CH Device Services：EDID, MCCS
 EDID read (Extended Display Identification Data)
 MCCS control (Monitor Control Command Set)
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9. Display Port Introducing
Hot Plug Detect
• Signal provided by the Sink (display) to the Source (GPU)
• Typically 0V or 3.3V signal (bi-level).
• “High” signal (3.3V) indicates Sink presence.
• “Low” signal (0V) > 2 msec indicates Sink absence Low signal (0V)
• “Low” signal of 0.5 to 1ms indicates “interrupt” from Sink (request
to read Sink DPCD registers)
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10. Display Port Introducing
• DisplayPort uses a layered protocol for Isochronous AV Stream
Transport
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11. Display Port Introducing
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12. Display Port Introducing – Link Training
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13. Display Port Introducing – TP1
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14. Display Port Introducing – TP2
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15. (e)DP2LVDS introducing
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16. (e)DP2LVDS introducing
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17. (e)DP2LVDS introducing
eDP-to-LVDS
CPUeDP-to-VGA
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18. (e)DP2LVDS introducing
PLANDVLMP
Common Features
 Content protection (ASSR)
 LVDS spread spectrum
 Emb. oscillator
RTD2132R
 1 Lane DP & 1 Port LVDS
 1440x900@60Hz
 QFN32 (5x5)
RTD2136R
 2 Lane DP & 2 Port LVDS
 1920x1200@60Hz (RB)
 EEPROM Free by internal ROM
 Ultra-low power (by SWR mode)
 Support LDO mode to save inductor
 Support 1-A panel power supply
 Embedded Level Shifter
 Pin compatible with RTD2136S
 QFN48 (6x6)
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19. (e)DP2LVDS introducing – RTD2136
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20. (e)DP2LVDS introducing – RTD2136
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21. (e)DP2LVDS introducing – RTD2136
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22. (e)DP2LVDS introducing – RTD2136
 Schematic check list
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23. (e)DP2LVDS introducing – RTD2136
 Layout check list
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24. (e)DP2LVDS introducing – RTD2136
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25. DP2VGA introducing
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26. DP2VGA introducing
PLANDVLMP
RTD2168
 2-Lane DP1.2/eDP1.4 Compliant Rx
 Triple 210MHz 8bit DAC
 Max Resolution: 1920x1200@60Hz
 ASSR Support
 EEPROM Free by internal ROM
 Ultra-low Active/Stand-by Power
Design
 Embedded 3.3V-to-1.2V Regulator
 Crystal-less Design
 8KV ESD Protection
 QFN32 (5x5)
VGA
port
CPU
DP to VGA
Translator
DP to VGA
Translator
DP VGA
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27. DP2VGA introducing
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28. DP2VGA introducing
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29. DP2VGA introducing
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30. DP2VGA introducing
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31. DP2VGA introducing
 Schematic check list
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32. DP2VGA introducing
 Layout check list
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33. RTD tool using introduction
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34. Q&A
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35. Thanks
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