PBL1-v1-014e.pptx
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IMAX3: Amazing Dataflow-Centric CGRA and its Applications I present this slide to all hungry engineers who are tired of CPU, GPU, FPGA, tensor core, AI core, who want some challenging one with no black box inside, and who want to improve by themselves.
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PBL1-v1-014e.pptx
- 1. CPU GPU Ultimate CGRA w/ high-speed compiler CGRA for Energy-efficient Cryptography Beyond-Neuromorphic Systems Non-Deterministic Computing 20210401 1 IMAX3: Amazing Dataflow-Centric CGRA and its difference from CPU/Vector ep.14
- 2. Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 80-loops ALUALU I-Cache ALU ALU D-Cache Registers I-Cache ALU ALU D-Cache Regs. Regs. D-Cache Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 All instructions are executed. I-Cache ALU ALU D-Cache Registers 2 Vect.Insn.1 Vect.Insn.2 Vect.Insn.3 Vect.Insn.4 Vect.Insn.5 Vect.Insn.6 Vect.Insn.7 Vect.Insn.8 Vector Registers Register File 20210401 2 CPU ⇒ SIMD(vector) ⇒ MISD(CGRA) "GoogleのTPUにも使われたシストリックアレイアー キテクチャとDeep Learningについて", 富士通研究 所技術講演会, Jul. (2017) "プログラマビリティを維持できる限界に向けて”, SONY本社研究紹介, Mar. (2020) "Deep Learningに向けたApproximate Computingと シストリックアレイアーキテクチャ", 革新的コン ピューティングの研究開発戦略検討会, CRDS/JST, Jul. (2017) "Approximate Computingとシストリックアレイ", ジス クソフト技術講演会, Dec. (2017) "99%メモリなアクセラレータIMAX(In Memory Accelerator eXtension)", CAE計算環境研究会@関 西シスラボ 第8回シンポジウム, Mar. (2017) "Systolic Arrays as The Last Frontiers", Invited talk in IPB Seminar and UI seminar @ Indonesia, Jan. (2019) “IMAX2: A CGRA with FPU+Multithreading+Chiplet", Panel: CGRA and their Opportunities as Application Accelerators, ASAP2021, invited panel, Jul. (2021) “コンピュータ(データセンタ)の消費電力低減策 意見交換会”, LCS/JST, Jul. (2021) "非ノイマン型の世界 -CGRAを含む最近の研究紹 介-", JEITAデバイス技術分科会招待講演, Nov. (2021) "CGRAのJITコンパイル化と高機能化の魔法教え ます", 回路とシステムワークショップ招待講演, Aug. (2022)
- 3. Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 for { iter=0 iter=1 iter=2 iter=3 iter=4 iter=5 iter=6 iter=7 } Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Super Scalar, VLIW I-Cache ALU ALU D-Cache Registers EAG EAG 20210401 3
- 4. for { iter=0 iter=1 iter=2 iter=3 iter=4 iter=5 iter=6 iter=7 } Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 VECTOR Insn.1 Insn.1 Insn.1 Insn.1 Insn.1 Insn.1 Insn.1 Insn.1 I-Cache ALU ALU D-Cache / Main Memory Registers EAG V-insn.1 ALU ALU ALU ALU ALU ALU V-insn.2 Insn.2 Insn.2 Insn.2 Insn.2 Insn.2 Insn.2 Insn.2 Insn.2 20210401 4
- 5. for { iter=0 iter=1 iter=2 iter=3 iter=4 iter=5 iter=6 iter=7 } CGRA Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Insn.1 Insn.2 Insn.3 Insn.4 Insn.5 Insn.6 Insn.7 Insn.8 Local Memory Registers EAG ALU ALU Local Memory Registers EAG ALU ALU Local Memory Registers EAG ALU ALU Local Memory Registers EAG ALU ALU Insn.1 Insn.2 Insn.3 Insn.4 Insn.1 Insn.2 Insn.1 Insn.2 Insn.5 Insn.6 Insn.3 Insn.4 Insn.1 Insn.2 Insn.3 Insn.4 Insn.1 Insn.2 Insn.1 Insn.2 Insn.7 Insn.8 Insn.5 Insn.6 Insn.3 Insn.4 Insn.1 Insn.2 Insn.5 Insn.6 Insn.3 Insn.4 Insn.1 Insn.2 Insn.3 Insn.4 Insn.1 Insn.2 Insn.1 Insn.2 20210401 5
- 6. 20210401 6 You can modify IMAX for your application by yourself
Editor's Notes
- Computing Architecture Laboratory in Nara Institute of Science and Technology is now targeting at power efficient computers to suppress global warming. I present this video to all hungry engineers who are tired of CPU, GPU, FPGA, tensor core, AI core, who want some challenging one with no black box inside, and who want to improve by themselves. This video follows episode 13, and focuses on the difference from CPU and Vector.
- CPU and GPU execute instructions in order. However, in CGRA, ALUs and data path are reconfigured, data go through the network, and the results are stored every cycle.
- Let’s see from the program’s view point. In the case of CPU, the machine instructions are executed in order among each loop iterations. Superscalar and VLIW execute multiple instructions simultaneously, but basically the scope is relatively small.
- Vector is a model for simultaneous execution of instructions across multiple iterations. Long vector processors can eliminate the loop structure itself.
- On the other hand, CGRA has a lot of registers and ALUs, and you can paste the instructions in the loop structure as they are. CGRA executes instructions across multiple iterations but differs from vector processors. In case of CPU, data dependencies between instructions stop the pipelining of superscalars and VLIWs. However, CGRA does not stall the pipeline even if there are data dependencies. Similarly, vectors require an alignment mechanism that connects the main memory address of continuous data with the start of the vector register when executing multiple iterations simultaneously. However, CGRA pipelines multiple iterations and does not require complicated alignment mechanisms. A drawback of CGRA is that if the number of instructions in the loop structure exceeds the number that can be mapped at once, it should be split. However, by adopting high-density instructions such as CISC, and by adopting a ring structure that eliminates positional restrictions, these drawbacks can be overcome.
- The motivation of IMAX is to overcome the drawbacks of CPU and Vector. You can modify IMAX for your applications by yourself. The source code of IMAX compiler and simulator will help your development. Thank you for your attention.