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CO-DEVELOPMENT MANUFACTURING INNOVATION & SUPPORT
Akbar Pamungkas Sukasdi
Final Internship Presentation
Agenda
 3T BV Company Profile
 Introduction
 Assignment
 Project Summary
 Design Block Diagram
 Design Layout
 Results
 Recommendations
25 October 2015www.3t.eu 2
 Founded in 1982, 3T since 1994
 45 – 50 employees (mainly MSc/BSc)
 Offices in Enschede (HQ) & Eindhoven
 Does co-development, product innovation & support
25 October 2015www.3t.eu 3
Introduction
 Born in Batam, Riau Islands, Indonesia
 3rd year student of EPA Elektrotechniek
 Sep 2014 – Jan 2015 : 1st Internship Period in 3T BV
 2012 – 2016 : Bachelor of Electrical & Electronic
Engineering in Saxion University of Applied Sciences
25 October 2015www.3t.eu 4
Assignment
 Construct and test a DC/DC Converter using push pull
topology scheme (incorporating galvanic isolation).
 Topology : Push Pull Topology
 Input : 18 – 36 VDC
 Output : +/- 15 VDC
 Output Voltage Ripple : 150 mV peak-to-peak
 Efficiency : ≥ 89 %
 Output Power : 40 W
 Isolation
25 October 2015www.3t.eu 5
Project Summary
 The project has investigated why custom DC-DC
converter should be made
 The project has considered that high efficiency and low
noise operation should be part of the final design
 The project has recommended to give more attention to
the components selection and careful PCB layout
25 October 2015www.3t.eu 6
Design (Block Diagram)
25 October 2015www.3t.eu 7
Design (PCB Layout)
25 October 2015www.3t.eu 8
 All components are on the top
 Short traces
 Compact size (143 mm x 56.5 mm)
 Most SMD components are used
 Provides heatsink
 Isolation
Design (PCB Layout)
 Component top:
 Top Layer (Signal Layer):
25 October 2015www.3t.eu 9
Design (PCB Layout)
 Second Layer (Ground Plane):
• Barrier width : 1.5 mm
 Third Layer (Power Plane)
25 October 2015www.3t.eu 10
Design (PCB Layout)
25 October 2015www.3t.eu 11
 Bottom Layer (Signal Layer):
Results
 Stable +/- 15 VDC dual output voltages
 Low ripple output voltages (17.60 mV p-p)
 High efficiency up to 92% (Full Load)
25 October 2015www.3t.eu 12
Results
 Thermal picture:
25 October 2015www.3t.eu 13
Recommendations
 Integrated Heatsink (Thermal Management)
 Use Thermal Blind / Buried Vias (Thermal Management)
 Package Development (Thermal Management)
 MOSFETs w/ ultra low gate charge (Qg) (Efficiency)
 Ultra low forward voltage Schottky diodes (Efficiency)
 Use lead wire instead of solid copper wire (Efficiency)
25 October 2015www.3t.eu 14
3T B.V.
Institutenweg 6 Esp 401
7521 PK Enschede 5633 AJ Eindhoven
The Netherlands The Netherlands
T. +31 53 4 33 66 33
F. +31 53 4 33 68 69
E. info@3t.nl
W. www.3t.eu

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Co-Development Manufacturing Innovation & Support

  • 1. CO-DEVELOPMENT MANUFACTURING INNOVATION & SUPPORT Akbar Pamungkas Sukasdi Final Internship Presentation
  • 2. Agenda  3T BV Company Profile  Introduction  Assignment  Project Summary  Design Block Diagram  Design Layout  Results  Recommendations 25 October 2015www.3t.eu 2
  • 3.  Founded in 1982, 3T since 1994  45 – 50 employees (mainly MSc/BSc)  Offices in Enschede (HQ) & Eindhoven  Does co-development, product innovation & support 25 October 2015www.3t.eu 3
  • 4. Introduction  Born in Batam, Riau Islands, Indonesia  3rd year student of EPA Elektrotechniek  Sep 2014 – Jan 2015 : 1st Internship Period in 3T BV  2012 – 2016 : Bachelor of Electrical & Electronic Engineering in Saxion University of Applied Sciences 25 October 2015www.3t.eu 4
  • 5. Assignment  Construct and test a DC/DC Converter using push pull topology scheme (incorporating galvanic isolation).  Topology : Push Pull Topology  Input : 18 – 36 VDC  Output : +/- 15 VDC  Output Voltage Ripple : 150 mV peak-to-peak  Efficiency : ≥ 89 %  Output Power : 40 W  Isolation 25 October 2015www.3t.eu 5
  • 6. Project Summary  The project has investigated why custom DC-DC converter should be made  The project has considered that high efficiency and low noise operation should be part of the final design  The project has recommended to give more attention to the components selection and careful PCB layout 25 October 2015www.3t.eu 6
  • 7. Design (Block Diagram) 25 October 2015www.3t.eu 7
  • 8. Design (PCB Layout) 25 October 2015www.3t.eu 8  All components are on the top  Short traces  Compact size (143 mm x 56.5 mm)  Most SMD components are used  Provides heatsink  Isolation
  • 9. Design (PCB Layout)  Component top:  Top Layer (Signal Layer): 25 October 2015www.3t.eu 9
  • 10. Design (PCB Layout)  Second Layer (Ground Plane): • Barrier width : 1.5 mm  Third Layer (Power Plane) 25 October 2015www.3t.eu 10
  • 11. Design (PCB Layout) 25 October 2015www.3t.eu 11  Bottom Layer (Signal Layer):
  • 12. Results  Stable +/- 15 VDC dual output voltages  Low ripple output voltages (17.60 mV p-p)  High efficiency up to 92% (Full Load) 25 October 2015www.3t.eu 12
  • 13. Results  Thermal picture: 25 October 2015www.3t.eu 13
  • 14. Recommendations  Integrated Heatsink (Thermal Management)  Use Thermal Blind / Buried Vias (Thermal Management)  Package Development (Thermal Management)  MOSFETs w/ ultra low gate charge (Qg) (Efficiency)  Ultra low forward voltage Schottky diodes (Efficiency)  Use lead wire instead of solid copper wire (Efficiency) 25 October 2015www.3t.eu 14
  • 15. 3T B.V. Institutenweg 6 Esp 401 7521 PK Enschede 5633 AJ Eindhoven The Netherlands The Netherlands T. +31 53 4 33 66 33 F. +31 53 4 33 68 69 E. info@3t.nl W. www.3t.eu