1. Variation Designer
• chieve better designs with
A
reduced variation risk in less time
Variation Designer is the first truly scalable and extensible solution specifically
• ystematic and consistent flow for
S
developed to address variation challenges at the transistor level. Along
PVT Corners, Statistical or Proximity
with Solido’s PVT (process, voltage, temperature), Statistical and Proximity design
applications packages, Variation Designer can be deployed for transistor-
level design to account for global, local, environmental
and proximity related variation effects. Using these solutions,
customers are able to achieve better designs with reduced
variation risk in less time.
Better Design
Designs that do not adequately account for variation effects Extensive
are typically over or under-designed. Traditional methods to Simulation
prevent over or under-design are inefficient and result in lost
Analysis
productivity.
Variation Designer is used across the transistor level design
cycle – from PVT corner simulations to statistical analysis – to
determine mismatch effects or yield. The platform is also useful
for post-layout verification and, if required, for silicon debug. Heuristics-based
Intuitive to learn and easy to use, this interactive tool puts the Design
designer in control. Variation Designer provides a systematic
and consistent variation design flow for various transistor level
design types (analog/RF, IO, memory or standard cell digital)
that can be integrated with various simulator and design Faster
Better designs with reduced variation risk in less time
environments, providing a consistent interface to designers
irrespective of their specific tool environments.
Schematic/Netlist
Nominal Sizing
Over Design Under Design Variation Designer
Ex: Excessive Guard-band to Spec Ex: Insufficient Margin to Spec Statistical Package
PVT Corners
Yield Area
Power Mismatch Analysis Variation Designer
Power Statistical Package
Area Yield
Proximity Package
Yield Analysis
Layout, RCX
• Meets performance specs • Fails performance specs
• Consumes too much power • Yield loss – higher die cost
• Wastes area – higher die cost • Causes mask re-spins Post Layout Verification Variation Designer
• Product not competitive • Slow ramp to production PVT Corner Package
Statistical Package
Post Silicon Debug Proximity Package
Over or Under Design
Solido SPICE-based variation design tools span the design cycle
• Seamless integration with Cadence Virtuoso ADE and • Supports high-capacity requirements imposed by large
HSPICE Netlist circuits with thousands of active devices
• Works with Spectre, HSPICE, Analog FastSPICE, Spectre/ • Built-in multiprocessor LSF support
HSPICE-compatible simulators, and in-house simulators • Integrates with Matlab and Octave for post-processing
• Runs on most Linux and Solaris systems
www.solidodesign.com

2. Variation Designer
• chieve better designs with
A
reduced variation risk in less time
Variation Designer is a platform for which new applications can be developed to
• ystematic and consistent flow for
S
handle current and future random and systematic process variation challenges. PVT Corners, Statistical or Proximity
Once the Variation Design platform is integrated into a customers design environ- design
ment, new applications can be plugged into the platform and designers can use
them immediately.
Variation Designer is bundled with three applications that allow designers to ana-
lyze, identify and fix variation issues due to global process corners (TT, SS, FF, SF, FS).
PVT Statistical Prox-
Corner Package imity
Applications Description and Benefit Package Pack-
age
• Simulates corners, along with any user- Models Digital Statistical Well Prox-
defined corners Required Corners Parameters imity pa-
Run Corners rameters
• Allows designers to quickly iterate to
eliminate design loss 180nm
• Identifies sources of design loss by 180nm
sweeping using corners
Sweep Design Variables 130nm
• Pinpoints specific adjustments that can
be made to fix the design 90nm
• Performs a corner sensitivity analysis to 65nm
search for sensitive devices
Find Sensitive Devices 45nm
• Finds the most important devices using a
minimum number of simulations 32nm
Variation Designer has been deployed for various flows such as Cadence® Vir- 22nm
tuoso® Analog Design Environment (ADE) with Spectre Circuit Simulator, Virtuoso Recommended Application Packages
ADE with Synopsys’ HSPICE® Circuit Simulator, and HSPICE netlist.
Statistical Package
PVT Corner Package
Proximity Package
Discover True Corners
Analyze Mismatch
Run Monte Carlo
Reduce PVT Corners Verify High-Sigma Design Solve Well Proximity
Run Corners Sweep Design Variables Find Sensitive Devices
Command Line
User Interface
Graphical
Variation Designer
SPICE
Simulators Environments
Models
Spectre TSMC Virtuoso ADE
HSPICE UMC HSPICE Netlist
...
BDA IDM
...
...
North America Sales Europe Sales
111 North Market St, Suite 300 Japan Sales Support Asia Pacific Sales
Sipeda
San Jose, CA 95113 090 3910 4163 +1 408 332 5811 x 5728
+44 (0) 1386 550101
+1 408 332 5811 japan.sales@solidodesign.com asia.sales@solidodesign.com
europe.sales@solidodesign.com
na.sales@solidodesign.com
www.solidodesign.com