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Acceleration of Analog Physical Design<br />HiPerDevGen™ - Structure Generation<br />
Factors Driving the need for Analog Acceleration<br />Shorter Product Development Times<br />1<br />Shrinking Process Geom...
Shorter Product Development Times<br />Average IC Product Development Times<br />“We need to re-assess design tools and pr...
Effects of Shrinking Geometries<br />Companies are most concerned about the challenges of higher mask costs, greater desig...
Effects of Shrinking Process Geometries<br />Technology Cost Pressures<br />As geometries shrink, mask and design costs go...
Effects of Shrinking Process Geometries<br />EDA Trends<br />Development and support of Design Kits<br />Hierarchical Veri...
Effects of Shrinking Process Geometries<br />Transistor Count v Design Cycle Time <br />Transistor Count<br />Design Time<...
Analog Design – Bottleneck<br />1<br />Full automation approach has not gained traction<br />Analog Automation has been a ...
Analog Physical Design Automation<br />What do users want?<br />Create efficient device placements from user-provided cons...
Our Approach<br />Acceleration <br />Recognition and Generation of Common Structures<br /><ul><li>Differential Pairs
Current Mirrors
Resistor Dividers</li></ul>Our Approach<br />Correct by Construction<br /><ul><li>Closely aligned to handcrafted layout
 DRC & LVS Clean</li></ul>Consistent High Quality<br /><ul><li>Guarantees design standards are the same across the whole o...
Quick & Easy Set-up<br />Manufacturing Rules<br />User friendly GUI for set-up of new technologies<br />No CAD development...
 Features of HiPerDevGen™<br />  Linear Process Gradients<br />  Mask Misalignment<br />Implant Shadowing<br />  Photolith...
 Features of HiPerDevGen™<br /> Accelerates Layout time<br />Optimized for Yield<br />Double Contacts / Vias<br />Support ...
 Features of HiPerDevGen™<br />User<br />Tuning<br />Functionally<br />Aware<br />Floorplan<br />Estimations<br />Guarante...
 Features of HiPerDevGen™<br />User<br />Tuning<br />Functionally<br />Aware<br />Floorplan <br />Estimations<br />Guarant...
 Features of HiPerDevGen™<br />Understands functional differences between structures<br />User<br />Tuning<br />Functional...
 Features of HiPerDevGen™<br />User<br />Tuning<br />Functionally<br />Aware<br />Layout <br />Optimization<br />Guarantee...
 Features of HiPerDevGen™<br />User<br />Tuning<br />Functionally<br />Aware<br />Floorplan<br />	Estimations<br />Guarant...
Current Mirror Generation<br />
Current Mirror Generation<br />
Current Mirror Generation<br />
Current Mirror Generation<br />
Current Mirror Generation<br />
Current Mirror Generation<br />
Current Mirror Generation<br />
Differential Pair Generation<br />
Differential Pair Generation<br />
Differential Pair Generation<br />
Differential Pair Generation<br />
Differential Pair Generation<br />
Differential Pair Generation<br />
Differential Pair Generation<br />
Typical Op Amp Schematic<br />
Typical SDL Flow– Op Amp<br />
HiPerDevGen: Structure Recognition<br />Recognition of Current Mirrors <br />Recognition of Differential Pairs <br />
HiPerDevGen Generation<br />Generation of Current Mirrors <br />Generation of Differential Pairs <br />
Completed Op-Amp<br />Total Layout time <br /><1 hr !!<br />
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IC Mask Design - IC Layout Acceleration Tool - DAC Conference, June 2010

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IC Mask Design - The Experts in all aspects of IC Layout.
DAC Conference, Anaheim, June 2010
IC Layout Acceleration Tool - HiPer DevGen

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IC Mask Design - IC Layout Acceleration Tool - DAC Conference, June 2010

  1. 1. Acceleration of Analog Physical Design<br />HiPerDevGen™ - Structure Generation<br />
  2. 2. Factors Driving the need for Analog Acceleration<br />Shorter Product Development Times<br />1<br />Shrinking Process Geometries<br />2<br />EDA advancement on other areas of M/S Design<br />3<br />
  3. 3. Shorter Product Development Times<br />Average IC Product Development Times<br />“We need to re-assess design tools and practices to ensure we can achieve right first time design in a reasonable timeframe, and thus reach profitability sooner.”<br />Douglas Pattullo, Director Field Technical Support, TSMC Europe <br />Early 1990’s cycle times<br />0 6 12 18 24 30<br />Today’s average cycle times<br />0 6 12 18 24 30<br />Shorter Product Development Times<br /> Faster Time to Market<br />
  4. 4. Effects of Shrinking Geometries<br />Companies are most concerned about the challenges of higher mask costs, greater design complexity, IP costs and availability, and inadequate EDA tools. <br />Source: Kalypso Semiconductor Analysis 2009. <br />
  5. 5. Effects of Shrinking Process Geometries<br />Technology Cost Pressures<br />As geometries shrink, mask and design costs go up<br />TSMC’s wafer forecast shows a 40% CAGR (4x in 5 years) due to new designs in 90nm, 65nm and smaller<br />Mask Costs ($M) <br />Design Costs ($k)<br />First pass silicon is an essential target for all semiconductor companies regardless of geometry<br /> 350nm 90nm 22nm<br />Source: EETimes<br />
  6. 6. Effects of Shrinking Process Geometries<br />EDA Trends<br />Development and support of Design Kits<br />Hierarchical Verification<br />Successful deployment of P&R Tools<br />Can handle multi-million gate designs<br />Use of greater processing power<br />
  7. 7. Effects of Shrinking Process Geometries<br />Transistor Count v Design Cycle Time <br />Transistor Count<br />Design Time<br />90nm<br />250nm<br />45nm<br />Design cycle times at 90nm are increasing!! <br />Why??<br />Analog Layout Design IS now a bottleneck!!<br />Acceleration of this process is key<br />
  8. 8. Analog Design – Bottleneck<br />1<br />Full automation approach has not gained traction<br />Analog Automation has been a disappointment<br /> Difficult to set up<br /> Schematics need to be generated in defined formats<br /> Complicated to Constrain<br />Analog designers like to retain control<br />2<br />Very difficult to automate analog layout due to the ‘artistic’ nature of the process<br />3<br />
  9. 9. Analog Physical Design Automation<br />What do users want?<br />Create efficient device placements from user-provided constraints<br />Do this in a matter of minutes<br />Easy to set-up and use <br />Compliments existing user environments<br />Closely resemble handcrafted layout<br />Allow designers to apply constraints to groups of devices<br />Source: Jim Solomon, Founder Cadence<br />
  10. 10. Our Approach<br />Acceleration <br />Recognition and Generation of Common Structures<br /><ul><li>Differential Pairs
  11. 11. Current Mirrors
  12. 12. Resistor Dividers</li></ul>Our Approach<br />Correct by Construction<br /><ul><li>Closely aligned to handcrafted layout
  13. 13. DRC & LVS Clean</li></ul>Consistent High Quality<br /><ul><li>Guarantees design standards are the same across the whole organisation</li></ul>Is “Silicon Aware”<br /><ul><li>Understands functionality & process artefacts</li></ul>Analog Designers can easily tune the design<br /><ul><li>Rapid generation and simulation loop for optimal solution</li></li></ul><li>Our Solution<br />HiPerDevGen™<br />Automatic generation of design primitives<br />Using only set of DRC rules as base input <br />Reduces manual tasks and accelerates full custom layout<br />No change in design flow methodology <br />Understands design and process requirements associated with each structure<br />Matching, Parasitics<br />Technology node aware<br />Devices and structures scale with design rules<br />WPE, STI/LOD effects on nanometer technologies<br />
  14. 14. Quick & Easy Set-up<br />Manufacturing Rules<br />User friendly GUI for set-up of new technologies<br />No CAD development required<br />Instant generation of parameterized devices and structures<br />20 minutes for any new process<br />Note: Tanner will provide technology set-ups free of charge<br />
  15. 15. Features of HiPerDevGen™<br /> Linear Process Gradients<br /> Mask Misalignment<br />Implant Shadowing<br /> Photolithographic Invariance<br /> Current Flow Direction<br /> Antenna / VT Shift<br /> WPE<br />User<br />Tuning<br />Functionally<br />Aware<br />Floorplan<br />Estimations<br />Guarantees <br />Matching<br />Layout <br />Optimization<br />Parasitic <br />Aware<br />HiPerDevGen™<br />
  16. 16. Features of HiPerDevGen™<br /> Accelerates Layout time<br />Optimized for Yield<br />Double Contacts / Vias<br />Support for DFM<br />User<br />Tuning<br />Functionally<br />Aware<br />Guarantees <br />Matching<br />Floorplan<br />Estimations<br />Parasitic <br />Aware<br />Layout <br />Optimization<br />HiPerDevGen™<br />
  17. 17. Features of HiPerDevGen™<br />User<br />Tuning<br />Functionally<br />Aware<br />Floorplan<br />Estimations<br />Guarantees <br />Matching<br />Parasitic <br />Aware<br />HiPerDevGen™<br />Considers device and interconnect parasitics<br />Optimal solution based on user specific parasitic requirements<br />Layout <br />Optimization<br />
  18. 18. Features of HiPerDevGen™<br />User<br />Tuning<br />Functionally<br />Aware<br />Floorplan <br />Estimations<br />Guarantees <br />Matching<br />Layout <br />Optimization<br />Parasitic <br />Aware<br />HiPerDevGen™<br /> Ensures user defined matching, parasitic and performance requirements<br /> Reduced Simulation Cycle<br />
  19. 19. Features of HiPerDevGen™<br />Understands functional differences between structures<br />User<br />Tuning<br />Functionally<br />Aware<br />Floorplan<br />Estimations<br />Guarantees <br />Matching<br />Layout <br />Optimizatons<br />Parasitic <br />Aware<br />HiPerDevGen™<br />
  20. 20. Features of HiPerDevGen™<br />User<br />Tuning<br />Functionally<br />Aware<br />Layout <br />Optimization<br />Guarantees <br />Matching<br />Floorplan<br />Estimations<br />Parasitic <br />Aware<br />HiPerDevGen™<br />Prompt Floorplan Estimation<br />
  21. 21. Features of HiPerDevGen™<br />User<br />Tuning<br />Functionally<br />Aware<br />Floorplan<br /> Estimations<br />Guarantees <br />Matching<br />Layout<br />Optimization<br />Parasitic <br />Aware<br />HiPerDevGen™<br />
  22. 22. Current Mirror Generation<br />
  23. 23. Current Mirror Generation<br />
  24. 24. Current Mirror Generation<br />
  25. 25. Current Mirror Generation<br />
  26. 26. Current Mirror Generation<br />
  27. 27. Current Mirror Generation<br />
  28. 28. Current Mirror Generation<br />
  29. 29. Differential Pair Generation<br />
  30. 30. Differential Pair Generation<br />
  31. 31. Differential Pair Generation<br />
  32. 32. Differential Pair Generation<br />
  33. 33. Differential Pair Generation<br />
  34. 34. Differential Pair Generation<br />
  35. 35. Differential Pair Generation<br />
  36. 36. Typical Op Amp Schematic<br />
  37. 37. Typical SDL Flow– Op Amp<br />
  38. 38. HiPerDevGen: Structure Recognition<br />Recognition of Current Mirrors <br />Recognition of Differential Pairs <br />
  39. 39. HiPerDevGen Generation<br />Generation of Current Mirrors <br />Generation of Differential Pairs <br />
  40. 40. Completed Op-Amp<br />Total Layout time <br /><1 hr !!<br />
  41. 41. Summary<br />Problem<br />Analog Layout is now a bottleneck<br /> Automation attempts have not gained traction<br />Solution<br />HiPerDevGen adopts an acceleration approach<br /> Generates high quality “first time right” layout<br /> Is “Silicon Aware” and understands process artefacts<br /> Gives the user complete control over the design<br /> Simple to set-up and use<br /> No change in design flow methodology<br />
  42. 42. Come See for Yourself!<br />View a HiPerDevGen™Demo<br />Tanner – Booth #1342<br />Tanner EDA User Event <br />Thursday 17th June 2010<br />For more information visit www.tannnereda.com<br />

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