Celestial ss

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Celestial ss

  1. 1. SUCCESS STORY Cad E nC E a n d CEl E S T Ia l SEm I C O n dU C T O R Cadence Encounter Platform Helps Celestial develop High-Speed multimedia IC Based on 0.13µm Process “We adopted the Cadence Encounter digital IC design platform for this project. The Cadence Services team gave us key advice on 0.13µm technologies. By learning about and using Cadence technologies, we avoided costly re-spins and shortened the project schedule. We expect to have further collaboration with Cadence in the future.” John A.Thodiyil, Technical Director, Celestial Semiconductor Inc. (Beijing) CoRpoRaTe pRoFile Challenges in CPU, and a narrow time-to-market window, 0.13µm design the Celestial team simply could not afford • Celestial semiconductor develops a long learning curve or multiple iterations. integrated circuits for decoding Celestial Semiconductor Inc. (Beijing) aVs, mpeg2, h.264, and other develops integrated circuits for decoding In 0.13µm designs and below, both IR standards aVS, mPEG2, H.264, and other standards. drop and signal integrity (SI) have great In the past two years, Celestial has devel- impact on the entire design process. design Challenges Even the smallest default will cause chip oped the aVS decoding chip based on • Convert to a 0.13µm process failure. To avoid re-spins, the Celestial China standards as well as the mPEG2 while increasing the frequency decoding chip based on international engineering team needed a wire-centric to 220mhz standards, which have 5m+ gates and methodology to account for the effects of • minimize the impact of iR drop and signal integrity 160mHz in frequency. Both of these chips interconnect across the entire chip—from • Tape out the chip in a very tight have taped out. the very beginning of the design cycle— project schedule complete with power and timing analysis The mPEG2 decoding chip project in and SI prevention and fixing capabilities. CadenCe solUTion particular faced a new set of challenges, such as higher technical requirements • Cadence® encounter ® digitial and a much tighter schedule. To lower managing iR dRop iC design platform the cost, Celestial decided to convert its Cadence VoltageStorm Power analysis, CadenCe pRodUCTs 0.18µm process to a 0.13µm process, and a key technology in the Cadence and seRViCes Encounter digital IC design platform, then increased the frequency to 220mHz. • soC encounter™ RTl-to-gdsii system delivers leading-edge power and power With the Celestial back-end team’s limited • Voltagestorm® power analysis rail analysis. By adopting VoltageStorm experience in 0.13µm process design, • encounter Timing system the inherent complexity of completing a technology, Celestial designers benefited • Cadence services 220mHz design by embedded application from accurate instance-based power calculation and IR drop impact on the IC.
  2. 2. This data also played an important role in aChieVing Timingthe design of power rail routing and the ClosURe in 220mhznumber of power I/Os. VoltageStorm modetechnology helped Celestial keep the totalIR drop to less than 5%. as Celestial shifted to the 0.13µm pro- cess, it became more difficult to achieve the 220mHz design. On this front, theaddRessing si issUes Cadence SoC Encounter RTl-to-GdSIIFor 0.13µm technology, crosstalk analysis System played an important role. Byis crucial. Cadence Encounter Timing optimizing the interconnect and settingSystem offers a consistent, integrated up regions in key paths, the SoC Encounterstatic timing analysis (STa) environment system made it possible for the Celestialfor place-and-route optimization and team to achieve timing closure.signoff verification. It combines theCeltIC® nanometer delay Calculator’s “We adopted the Cadence Encounterproduction-proven SI analysis capabilities digital IC design platform for this project.with Cadence technologies for timing and The Cadence Services team gave us keypower analysis, delay calculation, advanced advice on 0.13µm technologies. By learningmodeling, and global timing debug. about and using Cadence technologies,Celestial adopted Encounter Timing we avoided costly re-spins and shortenedSystem to analyze both the impact of the project schedule,” explained Johncrosstalk on timing and of glitch on logic. a. Thodiyil, Technical director at Celestial.Using Encounter Timing System enabled “We expect to have further collaborationthe Celestial design team to avoid with Cadence in the future.”uncontrollable errors in post-routinganalysis. For more information about these and other products contact: info@cadence.com or log on to: www.cadence.com© 2007 Cadence design systems, inc. all rights reserved. Cadence, CeltiC, encounder, and Voltagestorm are registered trademarks andthe Cadence logo and soC encounter are trademarks of Cadence design systems, inc. all others are properties of their respective holders.7415 04/07 mK/Fld/Ja/pdF

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