DEV meet-up UiPath Document Understanding May 7 2024 Amsterdam
Celestial ss
1. SUCCESS STORY
Cad E nC E a n d CEl E S T Ia l
SEm I C O n dU C T O R
Cadence Encounter Platform Helps Celestial develop
High-Speed multimedia IC Based on 0.13µm Process
“We adopted the Cadence Encounter digital IC design platform
for this project. The Cadence Services team gave us key advice
on 0.13µm technologies. By learning about and using Cadence
technologies, we avoided costly re-spins and shortened the
project schedule. We expect to have further collaboration
with Cadence in the future.”
John A.Thodiyil, Technical Director, Celestial Semiconductor Inc. (Beijing)
CoRpoRaTe pRoFile
Challenges in CPU, and a narrow time-to-market window,
0.13µm design the Celestial team simply could not afford
• Celestial semiconductor develops a long learning curve or multiple iterations.
integrated circuits for decoding Celestial Semiconductor Inc. (Beijing)
aVs, mpeg2, h.264, and other develops integrated circuits for decoding In 0.13µm designs and below, both IR
standards aVS, mPEG2, H.264, and other standards. drop and signal integrity (SI) have great
In the past two years, Celestial has devel- impact on the entire design process.
design Challenges Even the smallest default will cause chip
oped the aVS decoding chip based on
• Convert to a 0.13µm process failure. To avoid re-spins, the Celestial
China standards as well as the mPEG2
while increasing the frequency
decoding chip based on international engineering team needed a wire-centric
to 220mhz
standards, which have 5m+ gates and methodology to account for the effects of
• minimize the impact of iR drop
and signal integrity 160mHz in frequency. Both of these chips interconnect across the entire chip—from
• Tape out the chip in a very tight have taped out. the very beginning of the design cycle—
project schedule complete with power and timing analysis
The mPEG2 decoding chip project in and SI prevention and fixing capabilities.
CadenCe solUTion particular faced a new set of challenges,
such as higher technical requirements
• Cadence® encounter ® digitial
and a much tighter schedule. To lower
managing iR dRop
iC design platform
the cost, Celestial decided to convert its Cadence VoltageStorm Power analysis,
CadenCe pRodUCTs 0.18µm process to a 0.13µm process, and a key technology in the Cadence
and seRViCes Encounter digital IC design platform,
then increased the frequency to 220mHz.
• soC encounter™ RTl-to-gdsii system delivers leading-edge power and power
With the Celestial back-end team’s limited
• Voltagestorm® power analysis rail analysis. By adopting VoltageStorm
experience in 0.13µm process design,
• encounter Timing system
the inherent complexity of completing a technology, Celestial designers benefited
• Cadence services
220mHz design by embedded application from accurate instance-based power
calculation and IR drop impact on the IC.