Computer Organisation Part 4


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Computer Organisation by Mukesh Upadhyay from Lachoo Memorial College Jodhpur

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Computer Organisation Part 4

  1. 1. BASIC COMPUTER ORGANISATION<br />God’s Organisation <br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  2. 2. CPU<br />TRIODE<br />I/O<br />MEMORY<br />Buses :<br />A Bus (Address Bus)<br />D Bus (Data Bus)<br />C Bus (control Bus)<br />System Buses <br />(Collection of A,B,C)<br />Note : Primary Memory directly addressable by CPU<br /> Secondary Memory not directly addressable by CPU<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  3. 3. Memory<br />RAM<br />ROM<br />IOC<br />I/P 1<br />V<br />FLAG<br />I<br />N<br />T<br />E<br />R<br />F<br />A<br />C<br />E<br />I/P 2<br />.<br />.<br />.<br />ALU<br />I/P n<br />GPR<br />ACC<br />O/P 1<br />O/P 2<br />.<br />.<br />.<br />PC<br />SP<br />O/P m<br />IR<br />I/O<br />TIMING &CONTROL<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  4. 4. Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />Bus Convention :<br />A/B Bus<br />C Bus<br />Exchange of Information : <br />Unidirectional<br />Note :<br />I / O Control : South Bridge<br />Memory Control : North Bridge<br />Note :<br />Memory which can be change itself is known as register.<br />Note :<br />Every CPU is microprocessor, But every microprocessor is not CPU<br />
  5. 5. Transformation mechanism that transforms the given input into a desired O/P is typically called a PROCESS<br />Entity that perform these task (transformation) is <br />typically called PROCESSOR<br />The method followed where processor is performing a process is <br />typically called PROCESSING<br />(Process is being processed by processor is PROCESSING)<br />Role of Flags : 2 flags are affected when we go for A – B and they are Z (Zero) and B (Borrow).<br /> Z B <br /> 0 0 A&gt;B<br /> 0 1 A&lt;B<br /> 1 0 A=B<br /> 1 1 X<br /> Z . B + Z . B = S1<br /> Z . B = S2<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  6. 6. =<br />x<br />+<br />z<br />y<br />Role of Register : Pentium processor contains only 4 register<br /> (Register is nothing but a scratch pad memory)<br /> x = y + z <br />According to programming language:<br /> MOV R0 , y<br /> MOV R1 , z<br /> ADD R0 , R1<br /> MOV x , R0<br />L Value <br />R Value <br />Translated by <br />Compiler<br />This is Parse Tree <br />Or Syntax Tree <br />Note : Accumulator is represented by ( R0 / A )<br /> ( Most General Purpose Register )<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  7. 7. Role of Special Purpose Register (SPR):<br />Program Counter / Instruction Counter<br />( It holds address of next instruction to be executed )<br />101<br />100<br />PC<br />101<br />Instruction Register<br />Next Instruction’s address is in PC now, instruction at that address is read out and put it in Instruction Register. (Click any where to move)<br />This all process is maintained by Operating System<br />Stack Pointer <br />( It can not contain address of any empty location and when it not point to any thing than it contain NULL )<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  8. 8. Role of Instruction Register (IR):<br />100<br />100<br />.<br />.<br />.<br />1. Fetching of Instruction<br />2. Decoding of Instruction <br /> ( What to do ? )<br />3. Fetching of Data ( if any )<br />4. Execution<br />5 Stores Result<br />Machine Operations<br />Machine Operation (M.O.) + (M.O.) + (M.O.) + (M.O.) + . . . = Macro Operation<br />(Micro Operation) ( 1 Instruction Execution )<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  9. 9. Instruction and Addressing Mode :<br />ADD A , B<br />Operand<br />Operation<br />Classification <br />Zero Addressing Instruction<br />One Addressing Instruction<br />Two Addressing Instruction<br />Three Addressing Instruction<br />Zero Register Processor (C.P.U)<br /> OR<br /> Stack Oriented Computer<br /> OR<br /> Zero Register Organised C.P.U<br />Not a single GPR is available not even ACC<br />Single Register Processor<br /> Only one Register ACC<br />General Register Organisation<br /> More than one register <br /> ( ACC + many other register ) <br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  10. 10. Given Equation : X = ( A * B ) + ( C * D ) <br />3 Address Instruction <br />MUL R1 , A B <br />MUL R2 , C D<br />ADD X , R1 R2<br />MUL A , B<br />MUL C , D<br />ADD A , C<br />MOV X , A<br />In this case we will loose <br />value of A and C therefore <br />not feasible<br />2 Address Instruction <br />MOV R1 , A<br />MOV R1 , B<br />MOV R2 , C<br />MOV R2 , D<br />MOV R1 , R2<br />MOV X , R1<br />1 Address Instruction <br />LOAD A ( R0 A )<br />MUL B ( R0 R0 * B )<br />STORE T1<br />LOAD C<br />MUL D<br />ADD T1<br />STORE X<br />Note : Implicit operand is ACC / A / R0<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  11. 11. 0 Address Instruction <br />PUSH A<br />PUSH D<br />D<br />C<br />A<br />A * B<br />PUSH B<br />MUL <br />B<br />C * D<br />A<br />A * B<br />MUL <br />ADD<br />A * B<br />(A*B) + (C*D)<br />PUSH C<br />STORE X<br />C<br />(A*B) + (C*D)<br />(Calculated)<br />A * B<br />X<br />(in Memory)<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  12. 12. TYPE<br />OPERATOR<br />DESTINATION / SOURCE 1<br />SOURCE 2<br />00 ADD / AND<br />01 SUB / OR<br />10 MUL / XOR<br />11 DIV / NOT<br />Instruction Construction :<br />0 ADD<br />1 SUB<br />00 R0<br />01 R1<br />10 R2<br />11 M<br /> OPERATOR DESTINATION / SOURCE 1 SOURCE 2<br />1<br />2<br />2<br />5 bits<br />000 R0 <br />001 R1<br />010 R2<br />. .<br />. .<br />. .<br />111 R7<br />0 ARITHEMATIC<br />1 LOGICAL<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  13. 13. Register<br />Operand<br />Input Output<br />Operand<br />Memory<br />Operand<br />Addressing Mode :<br />( How you are getting data )<br />Instruction<br />Operand OR Operator<br />Direct<br />Indirect<br />Immediate<br />Register-Register Indirect<br />Register-Memory Indirect<br />Memory-Memory Indirect<br />Memory-Register Indirect<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  14. 14. 1. ADD[6] Direct Pointer<br /> (The address of operand is available in instruction (ORIGINAL WORKING))<br /> At location 6 (0110) , we are having address 9 (1001) of <br /> operand (1001011101).<br />2. Add 6 Immediate<br /> (Data is part of instruction , data is not in any register or memory)<br /> Here, data is available is Instruction, 6 (0110) is itself is data<br />IADD[6] Indirect<br /> (Pointer)<br /> At location 6 (0110) , we are having address 9 (1001), of memory location which is having address of operand (1001011101).It means it is concept of pointer to pointer<br />0110<br />1001<br />1001<br />1001011101<br />0110<br />1001<br />1001<br />1100<br />1100<br />1001011101<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  15. 15. Implied Mode : <br />( operand is at CPU’s register ) <br /> CMA Compliment ACC.<br /> STC Set Carry<br />Immediate Mode : <br />( data is part of Instruction ) <br /> ADD 6 Add 6 to Accumulator<br />Register Mode : <br />( Operand is available in GPR )<br /> ADD B A  A + B<br /> ADD A , B A  A + B <br /> ADD R1 R0  R0 + R1<br />Register Indirect Mode : <br /> IADD B A  A + [M]B<br /> the content of Memory M<br /> whose address is given by register B<br /> must be Added to A<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  16. 16. Memory<br />4096 X 16<br />PC ( Program Counter )<br />1 2 3 . . . . . .16<br />MAR<br />1 2 3 . . . 12<br />1 2 3<br />1<br />I<br />OPR<br />MBR<br />1<br />1 2 3 . . . . . .16<br />E<br />AC<br />1 2 3 . . . . . .16<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  17. 17. ADIC BUS<br />CPU<br />CPU<br />VIDEO<br />BUS<br />FSB<br />DVD<br />HOST PORT<br />MAIN<br />MEMORY<br />NORTH <br />BRIDGE<br />AGP<br />PORT<br />AGP POINT<br />MONITOR<br />LOCAL VIDEO<br /> MEMORY<br />PCI SLOT<br />PCI BUS<br />IDE<br />SOUTH<br />BRIDGE<br />SCSI<br />ETHERNET<br />USB<br />I<br />R<br />C<br />HDD<br />CD<br />ROM<br />INTERRUPT<br />IO<br />APIC<br />ISA BUS<br />SUPER<br />I/O<br />ISA<br />SLOT<br />FDD<br />BIOS<br />KB<br />RPINTER<br />SOUND<br />CHIP<br />MOUSE<br />COM 1<br />COM 2<br />BUSES<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  18. 18. 1<br />I/O<br />PROCESSOR<br />MEMORY<br />CONTROL<br />2<br />O/P<br />PRIMITIVE BUS ARCHITECTURE<br />The drawback of this technique is that a double side bus is needed<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  19. 19. BACKPLANE BUS<br />PROCESSOR<br />I/O<br />I/O<br />I/O<br />MEMORY<br />SHARED BUS ARCHITECTURE<br />Different i/o has different data transmission protocol<br />and also having different speed (mismatch) for that, <br />and this is all burden taken care by one device<br />Shared Bustypically called Backplane Bus<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  20. 20. Processor Memory Bus<br />(PMB)<br />Processor<br />Memory<br />Bus<br />Adaptor<br />Bus<br />Adaptor<br />Bus<br />Adaptor<br />I/O Bus<br />I/O Bus<br />I/O Bus<br />The previously said bus system is also having disadvantage of CPU Overheads,<br />to remove this we have two type of Level Architecture :<br /> 1. 2 Leveled Architecture<br /> 2. 3 Leveled Architecture <br />2 Leveled Architecture<br />Note : Conflicts and Mismatch can be taken care by Bus Adaptor now this not burden for CPU<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  21. 21. Processor Memory Bus<br />(PMB)<br />Processor<br />Memory<br />MBA<br />BA<br />Backplane Bus<br />BA<br />3 Leveled Architecture<br />Note : PMB is not directly connected to I/O, rather connected to MBA<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  22. 22. Transfer<br />Video camera <br />To PC<br />Proprietary<br />and <br />rest all are Free<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  23. 23. SU<br />DU<br />Valid Data<br />Data<br />Strobe<br />t3<br />t4<br />t2<br />t1<br />BUS TRANSFER : <br />Strobe Method<br />Handshake Method<br />Strobe Method : (source initiated)<br />Block Diagram<br />Timing Diagram<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  24. 24. SU<br />DU<br />Valid Data<br />Data<br />Strobe<br />Strobe Method : (destination initiated)<br />Block Diagram<br />Timing Diagram<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  25. 25. SU<br />DU<br />Data Bus<br />DAV<br />DAC<br />2. Handshaking Method : ( Source Initiated )<br />Block Diagram<br />SU<br />DU<br />DAC<br />DAV <br />0<br />1<br />0<br />1<br />Data Valid<br />Data Accept<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />Click for Every Action<br />
  26. 26. Place Data on BUS<br />Enable DAV<br />Accept Data<br />Enable DAC<br />Disable DAV<br />Disable DAV<br />Timing Diagram<br />Valid Data<br />Data<br />DAV<br />DAC<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  27. 27. 2. Handshaking Method : ( Destination Initiated )<br />Block Diagram<br />SU<br />DU<br />Data Bus<br />DAV<br />RFD<br />SU<br />DU<br />DAC<br />DAV <br />0<br />0<br />1<br />1<br />Data Valid<br />Data Accept<br />Ready to Accept Data<br />Click for Every Action<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  28. 28. Ready to accept Data<br />Enable DAC<br />Place Data on BUS<br />Enable DAV<br />Accept Data from <br />Enable DAC<br />Disable DAV<br />Timing Diagram<br />Data<br />Valid Data<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  29. 29. Bus Scheduling :<br />Daisy Chaining <br />Polling<br />Independent<br />Daisy Chaining<br />Bus Control<br />Unit<br />(BCU)<br />U1<br />U2<br />Un<br />Bus Grant<br />. . .<br />Bus Request<br />Bus Busy<br />BUS<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  30. 30. Case 1: U1 is requesting for BUS<br />Note: <br />(Sequential processing)<br />Therefore Un have lowest priority and U1 have highest priority.<br />If U1 leave then only other gets the chance.<br />(as shown in diagram)<br />Case 2: U2 is requesting for BUS<br />.<br />.<br />.<br />Case 3: Un is requesting for BUS<br />U1 grab the Bus<br />Bus Control<br />Unit<br />(BCU)<br />U1<br />U2<br />Un<br />Bus Grant<br />. . .<br />Bus Request<br />Bus Busy<br />BUS<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  31. 31. Polling<br />111<br />000<br />001<br />. . .<br />U1<br />U2<br />Un<br />Bus Control<br />Unit<br />(BCU)<br />Poll count<br />BR<br />BB<br />8 devices : 3 poll count<br />16 devices : 4 poll count<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  32. 32. Independent<br />U1<br />U2<br />Un<br />Bus Control<br />Unit<br />(BCU)<br />. . .<br />Poll count<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  33. 33. START<br />A=0, QN-1=0<br />M=MULTIPLECAND<br />Q=MULTIPLIER<br />COUNT =N<br />=10<br />=01<br />Q0QN-1<br />=11<br />=00<br />A=A+M<br />A=A-M<br />Arithmetic Shift Right<br />A Q QN-1 <br />COUNT=N<br />No<br />COUNT =0<br />?<br />Yes<br />STOP<br />Booth Algorithm :<br />(Using 2’s compliment)<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  34. 34. Multiplication Algorithm :<br />(Using Signed Magnitude)<br />START<br />Bs<br />MULTIPICAND B<br />MULTIPLIER Q<br />As = Qs + Bs<br />Qs = Qs + Bs<br />A = 0 , E = 0<br />SC = n - 1<br />As<br />Qs<br />E<br />A<br />Q<br />QN<br />=1<br />QN-1=?<br />=0<br />EA=A+B<br />SHR EA Q<br />SC=SC-1<br />Not 0<br />SC=?<br />=1<br />STOP<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  35. 35. Division Algorithm :<br />Basic Steps:<br />“A trial division” is made by subtracting the y register from Accumulator after the subtraction one of the following is executed<br /> 1. if Result is – ve the divisor will not go so a ZERO is placed in rightmost bit of the B register and Accumulator is restored. The combined B register and Accumulator are shifted Left.<br /> 2. if Result of subtraction is + ve or Zero, then the trail division is succeeded. The Accumulator and B register both are shifted left and then 1 is placed in the right most bit of B. <br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />
  36. 36. CBest of Luck<br />Krishna Kumar Bohra (KKB), MCA LMCST<br /><br />