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Fully Pipelined Low-Cost and High-Quality Color
Demosaicking VLSI Design for Real-Time Video
Applications
ABSTRACT:
This paper presents a fully pipelined color demosaicking design. To improve the
quality of reconstructed images, a linear deviation compensation scheme was
created to increase the correlation between the interpolated and neighboring pixels.
Furthermore, immediately interpolated green color pixels are first to be used in
hardware-oriented color demosaicking algorithms, which efficiently promoted the
quality of the reconstructed image. A boundary detector and boundary mirror
machine were added to improve the quality of pixels located in boundaries. In
addition, a hardware sharing technique was used to reduce the hardware costs of
three interpolators. The VLSI architecture in this work contains only 4.97 K gate
counts and the core area is 60,229 um2 synthesized by using 0.18-um CMOS
process. The operating frequency of this work is 200 MHz by consuming 4.76
mW. Compared with the previous low-complexity designs, this work has the
benefits in terms of low cost, low power consumption, and high performance.
EXISTING SYSTEM:
NOWADAYS, digital cameras are widely used in many fields. The most well-
known is portable consumer electronics such as smart phone, tablet PC, digital
video, digital camera, notebook, etc. The image sensor is a very important
component in a digital camera, which can be roughly classified into charge-
coupled device (CCD) and complementary metal oxide semiconductor (CMOS). A
color filter array (CFA) technique is an efficient and compact method to obtain a
multispectral image both on CCD and CMOS image sensors. Each pixel in a CFA
image contains only one color. The most widely used format of color filter arrays
in the modern electronic products is Bayer color filter array [1] as shown in Fig. 1,
in which each pixel contains one of red, green and blue colors only. Hence, the
cost of image sensors and memory demand can be greatly reduced by the CFA
technique. However, since two-third color information is missed after using color
filter array, it is necessary to interpolate missing values backing to the CFA image
to restructure a full color image.
PROPOSED SYSTEM:
The proposed color demosaicking algorithm consists of a novel linear deviation
compensation, immediately interpolated green color information, boundary
detection, and boundary mirror models as illustrated in Fig. 2. The boundary
detector and mirror models were added to detect the boundary information and
provide mirror pixels for green and red-blue color interpolations, which can
efficiently improve the quality of interpolated pixels located in boundary. In
addition, the linear deviation compensation and immediately interpolated green
color pixels G’ are used to improve the quality of the interpolated red and blue
color pixels. The details of green and red-blue color interpolation models are
described.
SOFTWARE IMPLEMENTATION:
 Modelsim 6.0
 Xilinx 14.2
HARDWARE IMPLEMENTATION:
 SPARTAN-III, SPARTAN-VI

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Fully pipelined low cost and high-quality color demosaicking vlsi design for real-time video applications

  • 1. Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications ABSTRACT: This paper presents a fully pipelined color demosaicking design. To improve the quality of reconstructed images, a linear deviation compensation scheme was created to increase the correlation between the interpolated and neighboring pixels. Furthermore, immediately interpolated green color pixels are first to be used in hardware-oriented color demosaicking algorithms, which efficiently promoted the quality of the reconstructed image. A boundary detector and boundary mirror machine were added to improve the quality of pixels located in boundaries. In addition, a hardware sharing technique was used to reduce the hardware costs of three interpolators. The VLSI architecture in this work contains only 4.97 K gate counts and the core area is 60,229 um2 synthesized by using 0.18-um CMOS process. The operating frequency of this work is 200 MHz by consuming 4.76 mW. Compared with the previous low-complexity designs, this work has the benefits in terms of low cost, low power consumption, and high performance.
  • 2. EXISTING SYSTEM: NOWADAYS, digital cameras are widely used in many fields. The most well- known is portable consumer electronics such as smart phone, tablet PC, digital video, digital camera, notebook, etc. The image sensor is a very important component in a digital camera, which can be roughly classified into charge- coupled device (CCD) and complementary metal oxide semiconductor (CMOS). A color filter array (CFA) technique is an efficient and compact method to obtain a multispectral image both on CCD and CMOS image sensors. Each pixel in a CFA image contains only one color. The most widely used format of color filter arrays in the modern electronic products is Bayer color filter array [1] as shown in Fig. 1, in which each pixel contains one of red, green and blue colors only. Hence, the cost of image sensors and memory demand can be greatly reduced by the CFA technique. However, since two-third color information is missed after using color filter array, it is necessary to interpolate missing values backing to the CFA image to restructure a full color image.
  • 3. PROPOSED SYSTEM: The proposed color demosaicking algorithm consists of a novel linear deviation compensation, immediately interpolated green color information, boundary detection, and boundary mirror models as illustrated in Fig. 2. The boundary detector and mirror models were added to detect the boundary information and provide mirror pixels for green and red-blue color interpolations, which can efficiently improve the quality of interpolated pixels located in boundary. In addition, the linear deviation compensation and immediately interpolated green color pixels G’ are used to improve the quality of the interpolated red and blue color pixels. The details of green and red-blue color interpolation models are described.
  • 4. SOFTWARE IMPLEMENTATION:  Modelsim 6.0  Xilinx 14.2 HARDWARE IMPLEMENTATION:  SPARTAN-III, SPARTAN-VI