FSE_RTSimex

Logical Time @ work: the project Julien DeAntoni, Frédéric Mallet I3S/UNS/INRIA Frédéric Thomas, Gonzague Reydet Obeo Jean-Philippe Babau UBO and more... FSE 2010 1

Logical Time...• focuses on causal relations between events• Is independent of the abstraction level• Is multi-clock (polychronous)• Provides a partial order between events After 23 starts of the computer, a disk check is done The computation duration is 156 processor ticks 3

Logical Time...• focuses on causal relations between events• Is independent of the abstraction level• Is multi-clock (polychronous)• Provides a partial order between events After 23 starts of the computer, a disk check is done The computation duration is 156 processor ticks In modern laptop, tick is logical since the processor speed depend on the battery level 4

Logical Time...• focuses on causal relations between events• Is independent of the abstraction level• Is multi-clock (polychronous)• Provides a partial order between events LOGICAL TIME Friedemann Mattern Darmstadt University of Technology 5

Physical Time...• Can be seen as a special case of logical time After 5 secondes, it stops... ≅ After 5 events of the “second” clock, it stops 6

Logical Time @ work: the project Julien DeAntoni, Frédéric Mallet I3S/UNS/INRIA Frédéric Thomas, Étienne Juliot Obeo Jean-Philippe Babau UBO and more... FSE 2010 7

Retro-ingénierie de Traces danalyse de SIMulationet dEXécution de systèmes temps-réel 8

Context : help the designer Designer Code Real time Multi-task execution Analysis of the execution 9 9

Context: execution traces Designer Code Real time Multi-task executionJumpShot , Vampir,Linux Tool Eclipse Project Exection analysis Temporal execution traces and reports OTF, VCD 10 10

observationsDesigner Model Code Real time Multi-task execution SDL, AADL ... Execution Temporal execution analysis and traces report 11 11

RT-Simex objectivesDesigner Models Code Real time Multi-task executionUML MARTE Eclipse Execution analysis Temporal execution and report AT THE traces MODEL LEVEL 12 12

Processus RT-Simex 13 13

MARTE TIME MODEL• SubProfile of the MARTE UML profile standardized by the OMG (Object Management Group) – Reviewed and accepted by the community – Implemented in Papyrus, magic draw, etc – Under Implementation in other UML tools• A Domain Model integrated with eclipse and usable with Domain Specific Language 15 15

MARTE TIME MODEL• The main concept is the Clock. – It is a way to specify a, possibly infinite, ordered set of instants – It can be logical or chronometric, discrete or dense – Its type is a ClockType itsResolution = 1 = TAI = discrete tick 16 16

MARTE TIME MODEL 1..* itsResolution = 1 = TAI Simplified view of the MARTE Time meta-Model 17 17

MARTE TIME MODEL • Sketchy example of its use Producer Consumer c1User model 18 18

MARTE TIME MODEL • Sketchy example of its use Producer Consumer c1User model sendEvent receiveEvent 19 19

MARTE TIME MODEL • Sketchy example of its use Producer Consumer c1User model sendEvent receiveEvent on on c1.sendEvent: LogicalClock c1.receiveEvent: LogicalClockMARTE model LogicalClock : ClockType IsLogical : True Nature : discrete The ordered set of sendEvent is bijective with the ordered set of instants of c1.sendEvent 20 20

CCSL• Clock Constraint Specification Language – Firstly introduced in the MARTE TIME profile – Declarative model-based language integrated with Eclipse – Formal semantics (both denotational and operational) – Tooled (TimeSquare)→ Explicitly represents / specifies relations between clocks 21 21

CCSL (Clock Constraint Specification Language) – Relations: dependencies between clocks • Coincidence → = • Exclusion → # • Precedence → < • Alternance → ~ – Expressions: a mean to create new clocks from others • Delay → delayedFor X on aClock • Filtering → aClock filteredBy aBinaryWord • Union → aClock union anotherClock • Intersection → aClock inter anotherClock • Periodicity → periodicOn aClock period X offset Y • … 22 22

CCSL (Clock Constraint Specification Language) – Relations: dependencies between clocks • Coincidence → = • Exclusion → # • Precedence → < • Alternance → ~ – Expressions: a mean to create new clocks from others • Delay → delayedFor X on aClock • Filtering → aClock filteredBy aBinaryWord • Union → aClock union anotherClock • Intersection → aClock inter anotherClock • Periodicity → periodicOn aClock period X offset Y – Libraries: user-defined relations and expressions • … 23 23

CCSL • Sketchy example of its use Producer Consumer c1User model sendEvent receiveEvent on on c1.sendEvent: LogicalClock c1.receiveEvent: LogicalClockMARTE model LogicalClock : ClockType IsLogical : True Nature : discrete The ordered set of sendEvent is bijective with the ordered set of instants of c1.sendEvent 24 24

CCSL • Sketchy example of its use Producer Consumer c1User model sendEvent receiveEvent on on c1.sendEvent: LogicalClock c1.receiveEvent: LogicalClockMARTE model LogicalClock : ClockType IsLogical : True left Nature : discrete right R1 : Precedes 25 25

Graphical formal annotation over a UML modelfor RT-Simex... 26 26

Simulate and animate the UML/MARTE model in TimeSquare(http://www-sop.inria.fr/aoste/dev/time_square/) 27 27

Processus RT-Simex 28 28

Processus RT-Simex CCSL specification 29 29

Processus RT-Simex CCSL specificationFor a specific platform, this is a total order... 30 30

Processus RT-Simex CCSL specificationFor a specific platform, this is a total order... For two communicating platforms, the traces are multi-clocks... 31 31

Processus RT-Simex CCSL specificationIf simulated it replays the execution... CCSL specification 32 32

Processus RT-Simex CCSL specification If simulated it replays the execution...So you can have a timing diagram, animate the model and so on... CCSL specification 33 33

A specification and the actual execution 34 34

Processus RT-Simex CCSL specification CCSL specification 35 35

Processus RT-Simex CCSL assertions CCSL specification 36 36

Processus RT-Simex CCSL assertions You can simulation both together to CCSL see if a violation occurs specification 37 37

Processus RT-Simex You can simulation both together to see if a violation occurs CCSL Violation of “Clk3b isSubClockOf clk3” assertions CCSLspecification 38 38

Conclusion 39 39

FSE_RTSimex

by fthomasfr on Dec 14, 2010

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FSE_RTSimex — Presentation Transcript