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RECONFIGURABLE CORDIC-BASED LOW-POWER DCT ARCHITECTURE BASED
ON DATA PRIORITY
ABSTRACT:
This paper presents a low-power coordinate rotation digital computer (CORDIC)-based
reconfigurable discrete cosine transform (DCT) architecture. The main idea of this paper is based
on the interesting fact that all the computations in DCT are not equally important in generating
the frequency domain outputs. Considering the importance difference in the DCT coefficients,
the number of CORDIC iterations can be dynamically changed to efficiently tradeoff image
quality for power consumption. Thus, the computational energy can be significantly reduced
without seriously compromising the image quality. The proposed CORDIC-based 2-D DCT
architecture is implemented using 0.13 μm CMOS process, and the experimental results show
that our reconfigurable DCT achieves power savings ranging from 22.9% to 52.2% over the
CORDIC-based Loeffler DCT at the cost of minor image quality degradations.