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Registers
- 2. Registers I0 • Group of D Flip-Flops • Synchronized (Single Clock) I1 • Store Data Q A0 Q A1 Q A2 Q D A3 R D R I2 D R I3 CLK Reset D R 2 / 28
- 3. Registers I0 CLK Q A0 Q A1 Q A2 Q D A3 R I3 I2 I1 D I1 R I0 I2 A3 D A2 R A1 I3 A0 Note: New data has to go in with every clock CLK Reset D R 3 / 28
- 4. Registers with Parallel Load • Control Loading the Register with New Data D7 D6 D5 D4 D3 D2 D1 D0 R E G I S T E R Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 LD 0 1 Q(t+1) Q(t) D LD 4 / 28
- 5. Registers with Parallel Load • Should we block the “Clock” to keep the “Data”? D7 D6 D5 D4 D3 D2 D1 D0 R E G I S T E R LD Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 I0 D Q A0 I1 D Q A1 I2 D Q A2 I3 D Q A3 Delays the Clock Load CLK 5 / 28
- 6. Registers with Parallel Load • Circulate the “old data” I0 I0 MUX I1 S Y D Q A0 I1 I0 MUX I1 S Y D Q A1 I2 I0 MUX I1 S Y D Q A2 I3 I0 MUX I1 S Y D Q A3 Load CLK 6 / 28
- 7. Shift Registers • 4-Bit Shift Register Serial Input SI D Q D Q D Q D Q SO Serial Output CLK 7 / 28
- 9. Serial Transfer SI Clock Shift Control Shift Register A CLK SO SI Shift Register B CLK Clock Shift Control CLK 9 / 28
- 10. Serial Addition Shift Control CLK SI Shift Register A x FA y z Shift Register B Q S C D CLR Clear 10 / 28
- 11. • • • • Universal Shift Register Parallel-in Parallel-out Serial-in Serial-out Serial-in Parallel-out Parallel-in Serial-out D Q D Q D Q D Q 11 / 28
- 12. Universal Shift Register Q3 Q2 Q1 Q0 Q SI for SR Q Q D CLR CLK S1 S0 Q D D D Y S1 S0 MUX I3 I2 I1 I0 D3 D2 D1 D0 SI for SL 12 / 28
- 13. Universal Shift Register S1 USR S0 SRin Q3 Q2 Q1 Q0 CLR D3 D2 D1 D0 SLin Mode Control S1 S0 0 0 0 1 1 0 1 1 Register Operation No change Shift right Shift left Parallel load 13 / 28