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- 1. Design of Adder and Multiplier using Quantum dot cellular automata based on Nanotechnology P. RADHIKA NEELABH TIWARI YOGITA PANTAsst. Prof., ECE Dept. M.Tech (VLSI-DESIGN), ECE Dept. Department of PhysicsSRM UNIVERSITY SRM UNIVERSITY UNIVERSITY OF LUCKNOW CHENNAI, INDIA CHENNAI, INDIA LUCKNOW, INDIAgpradhika82@gmail.com neelabh1988@gmail.com yogita.idol@gmail.comAbstract- Adders and multipliers are the basic building scaling down of CMOS devices. Quantum-dotblocks of digital systems. Initially transistors are used to cellular automata is an emerging paradigm whichimplement the circuit of adders and multipliers. Due tothe decreasing supply voltage, the power consumption allows operating frequencies in range of THz andfrom leakage current is a big challenge for transistor device integration densities about 900 times morecircuits. Nanotechnology is the better alternative to than the current end of CMOS scaling limits, whichthese problems. So in this project we will take help from is not possible in current CMOS technologies.nanotechnology to improve the design of adder andmultipliers. For doing this we use quantum dot Adders are fundamental circuits for mostautomata which is an emerging nanotechnology. With digital systems. Better adder performance depends onthe potential for faster speed smaller size and lower minimizing the carry prorogation delay..power consumption. Several adder and multiplierdesigns in QCA have been proposed. Conventional Conventional adder circuits frequently require manyadder circuit requires many wires which are relatively wires which are relatively difficult to realize in QCAdifficult to realize in QCA technology. . That work technology. Due to these wire delays, most previousdemonstrated that the design trade-offs are very adder designs are limited in speed.different in QCA. This paper utilizes the unique QCAcharacteristics to design a carry flow adder that is fast Multiplier design has not been widelyand efficient. Simulations indicate very attractive considered by QCA designers. There is QCAperformance (i.e., complexity, area, and delay). multiplier design simplicity. Complex designs generally incur long delays in QCA, so a simpleKeywords- Quantum-dot cellular automata, carry flowadder, carry delay multiplier, 1-bit full adder. structure is a good choice for the starting point. QCA designer is the product of an ongoing I. Introduction effort to create a rapid and accurate simulation and Quantum-dot cellular automata are an layout tool for quantum-dot cellular automata. QCAemerging technology that offers a revolutionary designer is capable of simulating complex QCAapproach to computing at Nano-level. This circuits on most standard platforms.technology has extra low power, high speed, andextremely dense circuit. After decades of watching II. Quantum cellular automatathe Moore‟s law hold and enjoying the steady A. Cellular automata-increase in transistor densities, the predominantly A cellular automaton is an abstract systemCMOS based Integrated Circuit industry now faces consisting uniform grid of cells. Each one of thesethe prospect of transistor sizes hitting the physical cells can only be in one of a finite number of states atlimit. As sizes go well below the micro-scale, a discrete time. The state of each cell in this grid isundesirable effects like high power dissipation and determined by the state of its adjacent cells, alsoquantum-mechanical side-effects discourage further called the cell‟s neighborhood. 1
- 2. B. Quantum cellular automata- within the cell. During the hold phase, the barriers are Any device designed to represent data and kept high, which keeps the electrons highly localizedperform computation, regardless of the physics on two dots and giving the cell a set polarization.principles it exploits and materials used to build it, This provides a driver cell for a neighbor. In themust have two fundamental properties: distinguish release phase, the barriers are slowly reduced, whichability and conditional change of state, the latter delocalizes the electrons, and the cell loses a distinctimplying the former. This means that such a device polarization value. The barriers in the relax phase aremust have barriers that make it possible to distinguish minimized, giving full freedom to the electrons andbetween states, and that it must have the ability to preventing these cells from influencing neighbors.control these barriers to perform conditional change During the switch phase, the barriers are slowlyof state. For example, in a digital electronic system, raised while the cells are driven by neighbors in thetransistor plays the role of such controllable energy hold phase. By the end of this phase, the cells arebarriers, making it extremely practical to perform distinctly polarized.computing with them. The below fig1 (d) shows about the four different clock zones available for the C. Design of QCA cell- implementation of the logic circuits. In quantum dot cellular automata, fourquantum dots occupy the corners of a square of thecell with potential barriers between pair of dots.Within this cell, two extra electrons are available, andby raising and lowering the potential barriers with theclock, an electron can localize on a dot. Due tocolumbic interaction, these electrons will tend to Fig1 (d) QCA clock zonesoccupy antipodal sites in the square cell. For anisolated cell, there are two energetically equivalent Each of the clock signals is shifted in phasearrangements of the extra electrons that are denoted by 90 degrees. This allows information to be pumpedas state polarization P. The cell polarization is used to through the circuit as a result of the successiveencode binary information. The basic building block latching and unlatching in cells attached to differentof QCA devices is the QCA cell shown in Figure clock cycles. These four clocking zones are1(a). A polarization of P=+1 (Binary 0) results if cells implemented in QCA designer and each cell can be1 and 3 occupied as in figure 1(b), while electrons on independently attached to anyone of the four clockingsites 2 and 4 results in P=-1 (Binary 1) as shown in zones.Figure 1(c). One of the main differences between circuit design in QCA and circuit design using conventional CMOS technologies and devices is that the circuit has no control over the clocks. This means that Fig1 (a) Basic QCA cell information is transmitted through each cell and not retained. III. QCA cell design A. Signal flow and control-Fig1 (b) Polarization= +1 Fig1 (c) Polarization= -1 A series of QCA cell acts like a wire. During each clock cycle, half of the wire is active for signal D. QCA clocking- propagations, while the other half is stable. During The clock used in QCA consists of four the next clock cycle, half of the previous active zonephases: hold, release, relax, and switch. Theses is deactivated and the remaining active zone cellsphases correlate to action of the potential barriers 2
- 3. trigger the newly activated cells to be polarized. Thus D. Design rules-signal propagates from one clock zone to the next. A nominal cell size of 20nm by 20nm is assumed. The cell has a width and height of 18nm and 5nm diameter quantum dots. The cells are placed on a grid with a cell center to center distance of Fig2 (a) QCA wire 20nm. For circuit layout and functionality B. QCA majority gate- checking, a simulation tool for QCA circuits, QCA The majority gate implements logic function Designer is used. This tool allows users to do aAB+BC+AC. The output cell assumes the custom layout and then verify QCA circuitpolarization of majority of three input cells. By functionality by simulations.setting one of the majority gate inputs to logic „0‟ or„1‟, the gate reduces to an AND or OR gate, IV. Adder designrespectively. A. Carry flow adder- A 1. Basic design- For fast calculation to reduce the carry propagation delay. We add additional logic elements. In Carry flow adder the path from carry-in to carry- B M= (AB+BC+AC) out only uses one majority gate. The majority gate always adds one more clock zone. Thus each bit in the words to be added requires at least one clock zone which sets the minimum delay. C Sum = abcᵢ+abcᵢ bcᵢ bcᵢ Fig2 (b) QCA majority gate M c , M a, b, cᵢ), cᵢ) Computation in a QCA majority gate is C = ab+bcᵢ+cᵢaperformed by driving the device cell to its lowest =M (a, b, cᵢ)energy state. This is achieved when the device cell This is the equations for a full adder realizedassumes the polarization of the majority of the three with majority gates and inverters.input cells. 2. Carry flow adder design- C. QCA inverter- The schematic and layout are optimized to The most common inverter design is shown minimize the delay and area. The carry propagationin fig2 (c). This fork inverter has two legs of the delay for 1-bit is a quarter clocks and the delay frominput QCA wire which interact at 45° angle with the data inputs to the sum output is three quarter clocks.first cell of the output wire. At this angle, the The wiring channels for the input/outputcoupling between cells is negative and can be synchronization should be minimized since wireexploited to realize the compliment function. channels add significantly to the circuit area. A B Fig3 (a) Layout of 1-bit full adder Fig2 (c) QCA inverter 3
- 4. V. Multiplier design A. FIR filter- To consider the multiplication of two numbers, start with a FIR filter. The FIR filter is defined by equation. Fig3 (b) Schematic of 1-bit full adder Using the one cycle delay operator, Zˉ¹, the Fig3 (a) and fig3 (b) show the layout and equation can be restated asschematic diagram of 1-bit full adder. Fig3 (c) showsthe layout diagram of 4-bit carry flow adder. Above equation can be implemented by the network shown in fig4 (a). Fig3 (c) Layout of 4-bit carry flow adder B. Carry look ahead adder- 1. Basic design- Fig4 (a) FIR filter network It is a type of adder used in digital logic. Acarry look ahead adder improves speed by reducing To use a pipeline design, both upper andthe amount of time required to determine carry bits. lower signal lines include the same additional delayThe carry look ahead adder calculates one or more units. Assume that Zˉ¼ is possible and apply the Zˉ½carry bits before the sum, which reduces the wait delay element to each section with upper and lowertime to calculate the result of the larger value bits. lines. Below equation shows that fig4 (b) gives the C M a, b, cᵢ) correct filter output result with N/2 cycle delay. Sum= M (M , b, cᵢ), M a, b, cᵢ), M a, b, cᵢ)) Pipelined FIR filter output 2. Carry look ahead design- The layout of carry look ahead adder isshown in fig3 (d). Fig3 (d) Layout of carry look ahead adder Fig4 (b) Pipelined FIR filter 4
- 5. B. Multiplication network- Let (aᵢ, bᵢ) be the multiplicand and multiplierpair and pᵢ be the product bit for position i. Bits aᵢ andpᵢ correspond to words xᵢ and yᵢ of the filter. Theposition i is the input at time i. Assume that the sumgeneration takes at least Zˉ½ and the carry generation Fig4 (g) CDM network for QCAtakes at least Zˉ¼. Even though fig4 c) and fig4 d)ignored the zeroth full adder, the derivation includesthat adder. The implementation can be done as Fig4 (h) Multiplier block diagram for CDM Fig4 (c) Redirected FIR filter network Fig4 (g) is used for QCA circuit implementation since it minimizes the latency from the first input to the first output. Fig4 (h) shows the block diagram of the optimized design for QCA layout. C. QCA implementation- Fig4 (d) Pipelined redirected FIR filter network Bit-serial adders are used to realize the carry delay multiplier. The bit- serial adder is modified from the full adder so that carry-in and carry-out are connected internally with a one clock delay. Fig4 (i) and fig4 (j) shows the schematic and layout diagram of 1-bit serial adder. This is denoted as a carry delay multiplier(CDM). It is optimized to minimize the latency of theoutput. The carry delay multiplier minimizes thelatency to the output. Fig4 (i) Schematic diagram of 1-bit serial adder Fig4 (k) and fig4 (l) shows the layout and simulation of carry delay multiplier. Fig4 (e) Carry delay multiplication Fig4 (j) Layout of 1-bit serial adder Fig4 (f) Redirected FIR filter network for QCA 5
- 6. Automata”, IEEE Trans. On Computers, vol. 58, no. 6, June 2009. 2. H. Cho and E.E. Swartzlander, Jr., “Serial Parallel Multiplier Design in Quantum-Dot Cellular Automata,” Proc. 18th IEEE Symp. Computer Arithmetic, pp. 7-15, 2007. 3. K. Walus, T. Dysart, G. Jullien, and R. Budiman, “QCA Designer: A Rapid Design and Simulation Tool for Quantum-Dot Cellular Automata,” IEEE Trans. Nanotechnology, vol. 3, no. 1, pp. 26-29, Mar. 2004. Fig4 (k) Layout of carry delay multiplier 4. H. Cho and E.E. Swartzlander, Jr., “Adder Designs and Analyses for Quantum-Dot Cellular Automata,” IEEE Trans. Nanotechnology, vol. 6, no. 3, pp. 374-383, May 2007. 5. R. Zhang, K. Walus, W. Wang, and G.A. Jullien, “Performance Comparison of Quantum-Dot Cellular Automata Adders,” Proc. IEEE Int‟l Symp. Circuits and Systems, vol. 3, pp. 2522-2526, 2005. 6. W. Wang, K. Walus, and G.A. Jullien, “Quantum-Dot Cellular Automata Adders,” Proc. Third IEEE Conf. Nanotechnology, pp. 461-464, 2003. 7. A. Vetteth et al., “Quantum-Dot Cellular Automata Carry-Look-Ahead Adder and Barrel Shifter,” Proc. Fig4 (l) Simulation result of carry delay multiplier IEEE Emerging Telecomm. Technologies Conf., Sept. 2002. 8. C.S. Lent, P.D. Tougaw, W. Porod, and G.H. Bernstein, VI. Conclusion “Quantum Cellular Automata,” Nanotechnology, vol. 4, QCA circuits have generally wires delay. no. 1 pp. 49-57, Jan. 1993.For a fast design it minimizes the complexity. In this 9. A.Orlovetal. “Experimental Demonstration of a Binarypaper by using QCA we are designing a carry flow Wire for Quantum Dot Cellular Automata” Appliedadder and carry look ahead adder which is faster and Physics Letters, vol.74, no.19, pp.2875-2877, May1999.efficient than the conventional adders. From this 10. R.K.Kummamuruetal., “Operation of a Quantum Dotproject we can conclude that simulation of carry flow Cellular Automata (QCA) Shift Register and Analysisadder and carry look ahead adder indicates very of Errors,” IEEE Trans. Electron Devices, vol.50, no.9,attractive performances i.e. less complexity, less area pp.1906-1913, Sept.2003.and less delay. By taking the help of nanotechnology 11. C.S.Lent, M.Liu, and Y.Lu, “Bennett Clocking of Quantum Dot Cellular Automata and the Limits toin the design of an adder we can reduce the size of Binary Logic Scaling,” Nanotechnology, vol.17, no.16,the adder circuit and thus can reduce its power pp.4240-4251, Aug.2006.consumption. By the given logical interpretation of 12. R.P.CowburnandM.E.Welland,“RoomTemperatureMagthe adder circuit we can say that speed of the adder is neticQuantumCellularAutomata,”Science,vol.287,no.54increased in this adder and its area is also reduced. 57,pp.14661468,Feb.2000.The CFA adders require less than one-fifth of the 13. L. Bonci, M. Macucci, “ Numerical investigation of energy dissipation in Quantum Cellular Automatonarea of the CLA and have about half of the delay of circuits,” in the Proceedings of the Europeanthe CLA. Conference on Circuit Theory and Design (Cork, There is a lot of work that is to be done in Ireland), vol.II, p. 239.this field. In the future we can try to increase the 14. I.Amlani,A.O.Orlov,G.Toth,G.H.Bernstein,C.S.Lent,an dG.L.Snider,“DigitalLogicGateUsingQuantumDotCelluspeed of the adder and multiplier circuit. We can larAutomata,”Science,vol.284,no.5412,pp.289–modify the carry flow adder by reducing its delay 291,1999.time and size. We can try to reduce the number of 15. M.Lieberman,S.Chellamma,B.Varughese,Y.L.Wang,C. S.Lent,G.H.Bernstein,G.Snider,andF.C.Peiris,“Quantuwire channels and thus reduce the size of this adder. m dot cellular automata at a molecular scale,” inBy reducing its size or area we can reduce power Molecular ElectronicsII of the New York Academy of Sciences, 2002, vol.960, pp.225–239.consumption of the adder and multiplier. VII. References 1. Heumpil Cho, and Earl E. Swartzlander, Jr., “Adder and Multiplier Design in Quantum-Dot Cellular 6

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