The document describes a standard cell library design project completed by three students - Vignesh Ganesan, Jayashree Jayabalan, and Franson Joshua J - for a VLSI design course at the University of Texas at Dallas. The standard cell library contains the schematics, layouts, and waveforms for 10 basic logic gates - inverter, NAND2, NOR2, XOR2, MUX2:1, OAI211, OAI21, AOI22, and D-Flip Flop. The document also includes a layout of all the cells together.

1. The University of Texas at Dallas
EECT 6325-VLSI DESIGN
Fall 2018
Vignesh Ganesan – VXG170004
Jayashree Jayabalan – JXJ180012
Franson Joshua J – FXJ180000
STANDARD CELL LIBRARY
DESIGN

2. CELLS :
1. INVERTER:
Schematics:

3. Layout:

4. Waveform:
2. NAND2
Schematics

5. Waveform:
Layout:

6. 3. NOR2
Schematics
Waveform:

7. Layout:

8. 4. XOR2
Schematics
Waveform:

9. Layout:

10. 5. MUX2:1
Schematics
Waveform:

11. Layout:

12. 6. OAI211
Schematics
Waveform:

13. Layout:

14. 7. OAI21
Schematics:
Waveform:

15. Layout:

16. 8. AOI22
Schematics:
Waveform:

17. Layout:

18. 9. D-Flip Flop
Schematics:

19. Waveform:

20. Layout:

21. 10. Layout of all the cells: