This document provides an overview of system on chip (SoC) interconnect architectures and standard bus protocols. It discusses key considerations for choosing an interconnect architecture such as bandwidth, latency, and clock domains. Common SoC bus standards including AMBA, CoreConnect, and Wishbone are described along with their bus architectures and components. The document also provides details on specific buses within standards, such as AMBA's AHB, ASB, and APB buses and CoreConnect's PLB, OPB, and DCR buses.

1. SOC Interconnects
SOC Bus Architectures
Mr. A. B. Shinde
Assistant Professor,
Electronics Engineering,
PVPIT, Budhgaon.
shindesir.pvp@gmail.com
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2. Unit-IV: Contents
 Introduction,
 Overview: Interconnect Architectures,
 Bus: Basic Architecture,
 SOC Standard Buses:
 AMBA,
 Core Connect,
 Bus Interface Units:
 Bus Sockets
 Bus Wrappers
 Analytic Bus Models.
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3. SoC Buses Overview
 AMBA bus
 ASB (Advanced System Bus)
 AHB (Advanced High-
performance Bus)
 APB (Advanced Peripheral Bus)
 Avalon
 CoreConnect
 PLB (Processor Local Bus)
 OPB (On-chip Peripheral Bus)
 ST Bus
 Type I (Peripheral protocol)
 Type II (Basic Protocol)
 Type III (Advanced protocol)
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 Wishbone
 CoreFrame
 Marble
 PI bus
 OCP
 VCI (Virtual Component Interface)
 SiliconBackplane Network

4. SoC Buses Overview
 AMBA bus
 ASB (Advanced System Bus)
 AHB (Advanced High-
performance Bus)
 APB (Advanced Peripheral Bus)
 Avalon
 CoreConnect
 PLB (Processor Local Bus)
 OPB (On-chip Peripheral Bus)
 ST Bus
 Type I (Peripheral protocol)
 Type II (Basic Protocol)
 Type III (Advanced protocol)
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 Wishbone
 CoreFrame
 Marble
 PI bus
 OCP
 VCI (Virtual Component Interface)
 SiliconBackplane Network

5. Introduction
 SOC designs involves the integration of intellectual property (IP)
cores, each separately designed and verified.
 Most important issue is the method by which the IP cores are
connected together.
 SOC interconnect architectures:
 Network - on - chip (NOC).
 Bus architectures
 Switch - based interconnects used in SOC are referred to as NOC.
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6. Overview: Interconnect Architectures
6
A simplified block diagram of an SOC module in a system context.

7. Overview: Interconnect Architectures
 The SOC module typically contains a number of IP blocks
(processors).
 In addition, there are various types of on - chip memory like cache,
data, or instruction storage.
 Other IP blocks serving application - specific functions, such as
graphics processors, video codecs and network control units are
integrated in the SOC.
 All above SOC modules need to communicate with each other for
the proper operation of system. Interconnects are used to do the
communication between them.
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8. Overview: Interconnect Architectures
 System level issues and specifications while Choosing a suitable
interconnect architecture:
1. Communication Bandwidth:
2. Communication Latency:
3. Master and Slave:
4. Concurrency Requirement:
5. Packet or Bus Transaction:
6. ICU: An interconnect interface Unit:
7. Multiple Clock Domains:
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9. Overview: Interconnect Architectures
 System level issues and specifications while Choosing a suitable
interconnect architecture:
1. Communication Bandwidth:
 It is the rate of information transfer between a module and the
surrounding environment in which it operates.
 Usually measured in bytes per second,
 The bandwidth requirement of a module describes the type of
interconnection required to achieve the overall system throughput as
per specifications.
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10. Overview: Interconnect Architectures
 System level issues and specifications while Choosing a suitable
interconnect architecture:
2. Communication Latency:
 It is the time delay between a module requesting data and receiving
a response to the request.
 For example:
 Watching a movie that is a couple of seconds later than when it is
actually broadcast is of no consequence.
 In contrast, even small, unanticipated latencies in a two - way mobile
communication protocol can make it almost impossible to carry out a
conversation.
 Hence, Latency may or may not be important in terms of overall system
performance. 10

11. Overview: Interconnect Architectures
 System level issues and specifications while Choosing a suitable
interconnect architecture:
3. Master and Slave.
 These terms concern whether a unit can initiate or react to
communication requests.
 A master, such as a processor, controls transactions between itself
and other modules.
 A slave, such as memory, responds to requests from the master.
 An SOC design typically has several masters and numerous slaves.
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12. Overview: Interconnect Architectures
 System level issues and specifications while Choosing a suitable
interconnect architecture:
4. Concurrency Requirement:
 The number of independent simultaneous communication
channels operating in parallel.
 Usually, additional channels improve system bandwidth.
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13. Overview: Interconnect Architectures
 System level issues and specifications while Choosing a suitable
interconnect architecture:
5. Packet or Bus Transaction:
 The size and definition of the information transmitted in a single
transaction.
 For a bus, this consists of an address with control bits (read/write, etc.)
and data.
 For a NOC it is referred as a packet. The packet consists of a header
(address and control) and data.
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14. Overview: Interconnect Architectures
 System level issues and specifications while Choosing a suitable
interconnect architecture:
6. ICU: An interconnect interface Unit.
 This unit manages the interconnect protocol and the physical
transaction.
 If the IP core requires a protocol translation to access the bus, the
unit is called a bus wrapper.
 In an NOC, this unit manages the protocol for transport of a packet
from the IP core to the switching network.
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15. Overview: Interconnect Architectures
 System level issues and specifications while Choosing a suitable
interconnect architecture:
7. Multiple Clock Domains:
 Different IP modules may operate at different clock and data rates.
 For example:
A video camera captures pixel data at a rate governed by the video
standard used,
while a processor’s clock rate is usually determined by the
technology and architectural design.
As a result, IP blocks inside an SOC often need to operate at
different clock frequencies, creating separate timing regions known
as clock domains.
 Crossing between clock domains can cause deadlock and
synchronization problems. 15

16. Bus: Basic Architecture
 The Computer Systems heavily dependent on the characteristics of
its interconnect architecture.
 A poorly designed system bus can throttle:
 Transfer of instructions and data between memory and
processor or
 between peripheral devices and memory.
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17. Bus: Basic Architecture
 The speed at which the bus can operate is often limited by:
 The high capacitive load on each bus signal,
 The resistance of the contacts on the connector, and
 The electromagnetic noise produced by such fast–switching
signals.
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18. Bus: Basic Architecture
 Arbitration and Protocols:
 Bus is just wire shared by multiple units.
 Some logic must be present to use the bus; otherwise, two units
may send signals at the same time, causing conflicts.
 In an SOC, a bus master is a component within the chip, such as a
processor.
 Other units connected to bus, such as I/O devices and memory
components, are the “slaves”.
 The bus master controls the bus paths using specific slave
addresses and control signals.
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19. Bus: Basic Architecture
 Arbitration and Protocols:
 Arbitration determines ownership (to whom access should be given).
 There is a centralized arbitration unit with an input from each
requesting unit. The arbitration unit then grants bus ownership to
one requesting unit, as determined by the bus protocol.
 The protocol determines the following:
 The type and order of data being sent;
 How the sending device indicates that it has finished sending the
information;
 The data compression method used, if any;
 How the receiving device acknowledges successful reception of
the information; and
 How arbitration is performed to resolve contention on the bus
and in what priority, and the type of error checking to be used. 19

20. Bus: Basic Architecture
 Bus Bridge:
 A bus bridge is a module that connects together two buses, which
are not necessarily of the same type.
 A typical bridge can serve three functions:
1. If the two buses use different protocols, a bus bridge provides the
necessary format and standard conversion.
2. A bridge is inserted between two buses to segment them and keep
traffic contained within the segments. This improves concurrency:
both buses can operate at the same time.
3. A bridge often contains memory buffers and the associated control
circuits.
When a master on one bus initiates a data transfer to a slave module
on another bus through the bridge, the data is temporarily stored in
the buffer, allowing the master to proceed to the next transaction
before the data are actually written to the slave.
A bus bridge can significantly improve system performance. 20

21. Bus: Basic Architecture
 Bus Varieties:
 Buses may be unified or split (address and data).
 In the unified bus the address is initially transmitted followed by one
or more data cycles;
 The split bus has separate buses for each of these functions.
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22. AMBA bus
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23. AMBA bus
 AMBA is Advanced Microcontroller Bus Architecture
 The AMBA protocol is an open standard, on-chip bus specification.
 Originally developed in 1995, the AMBA Specification has been refined
and extended with additional protocol support to provide the
capabilities required for SoC design.
 The AMBA protocol enhances a reusable design methodology.
 IP re-use is essential in reducing SoC development costs and
timescales and AMBA provides the interface standard that enables IP
re-use meeting the essential requirements
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24. AMBA bus
 Nowadays, AMBA is one of the leading on-chip busing system used
in high performance SoC design.
 AMBA is hierarchically organized into two bus segments, system-
bus and peripheral-bus, connected via bridge.
 Standard bus protocols for connecting on-chip components generalized
for different SoC structures are independent of the processor type and
are defined by AMBA specifications.
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25. AMBA bus
25
AMBA based system architecture

26. AMBA bus
 The three distinct buses specified within the AMBA bus are:
 ASB: Advanced System Bus
 ASB - First generation of AMBA system bus used for simple cost-
effective designs.
 ASB supports:
 burst transfer,
 pipelined transfer operation and
 multiple bus masters.
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27. AMBA bus
 The three distinct buses specified within the AMBA bus are:
 AHB: Advanced High-performance Bus
 AHB - later generation of AMBA bus is intended for high
performance high-clock synthesizable designs.
 It provides high-bandwidth communication channel and high
performance peripherals/hardware accelerators (ASICs MPEG, color
LCD, etc), on-chip SRAM, on-chip external memory interface and
APB bridge.
 AHB supports a multiple bus masters operation, peripheral and a
burst transfer, split transactions, wide data bus configurations.
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28. AMBA bus
 The three distinct buses specified within the AMBA bus are:
 APB: Advanced Peripheral Bus
 APB - is used to connect general purpose low speed low-power
peripheral devices.
 The bridge is peripheral bus master, while all buses devices (Timer,
UART, PIA, etc) are slaves.
 APB is static bus that provides a simple addressing with latched
addresses and control signals for easy interfacing.
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29. AMBA AHB
 AMBA AHB implements the features required for high-performance,
high clock frequency systems including:
 Burst transfers
 Split transactions
 Single-cycle bus master handover
 Single-clock edge operation
 Non-tristate implementation
 Wider data bus configurations (64/128 bits).
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30. AMBA AHB
 A typical AMBA AHB system design contains the following components:
 AHB master
A bus master is able to initiate read and write operations by
providing an address and control information. Only one bus master is
allowed to actively use the bus at any one time.
 AHB slave
A bus slave responds to a read or write operation within a
given address space range. The bus slave signals back to the active
master the success, failure or waiting of the data transfer.
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31. AMBA AHB
 A typical AMBA AHB system design contains the following components:
 AHB arbiter
The bus arbiter ensures that only one bus master at a time is
allowed to initiate data transfers.
 AHB decoder
The AHB decoder is used to decode the address of each
transfer and provide a select signal for the slave that is involved in
the transfer.
A single centralized decoder is required in all AHB implementations.
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32. AMBA AHB
AMBA AHB Master Interface
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33. AMBA AHB
AMBA AHB bus slave interface
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34. AMBA APB Bridge Interface
 The APB bridge is the only bus master on the AMBA APB.
 The APB bridge is also a slave on the higher-level system bus.
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35. AMBA APB Bridge
 The bridge converts system bus transfers into APB transfers and
performs the following functions:
 Latches the address and holds it valid throughout the transfer.
 Decodes the address and generates a peripheral select, PSELx.
Only one select signal can be active during a transfer.
 Drives the data onto the APB for a write transfer.
 Drives the APB data onto the system bus for a read transfer.
 Generates a timing strobe, PENABLE, for the transfer.
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36. AMBA APB
Bridge
 The AHB to APB bridge is an AHB slave, providing an interface
between the high speed AHB and the low-power APB.
 Read and write transfers on the AHB are converted into equivalent
transfers on the APB. As the APB is not pipelined, wait states are
added during transfers to and from the APB.
36
Block diagram
of bridge module

37. IBM’s CoreConnect Bus
37

38. CoreConnect Bus
38
CoreConnect bus based system

39. CoreConnect Bus
 CoreConnect is an IBM-developed on-chip bus.
 By reusing processor, subsystem and peripheral cores, supplied
from different sources, enables their integration into a single VLSI
design.
 It is comprised of three buses (PLB, OPB & DCR) that provide an
efficient interconnection of cores, library macros, and custom logic
within a SoC
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40. CoreConnect Bus
 PLB Bus : Processor Local Bus
 It is synchronous, multi master, central arbitrated bus that allows
achieving high-performance on-chip communication.
 Separate address and data buses support concurrent read and
write transfers.
 PLB macro is used to interconnect various master and slave
macros.
 PLB slaves are attached to PLB through shared, but decoupled,
address, read data, and write data buses.
 Up to 16 masters can be supported by the arbitration unit, while there
are no restrictions on the number of slave devices.
40

41. CoreConnect
Bus
 Figure illustrates the connection of multiple masters and slaves
through the PLB macro. Each PLB master is attached to the PLB macro
via separate address, read data and write data buses.
 PLB slaves are attached to the PLB macro via shared, but decoupled,
address, read data and write data buses along with transfer control and
status signals for each data bus.
 The PLB architecture supports up to 16 master devices and any
number of slave devices. 41
Example of PLB
Interconnection

42. CoreConnect Bus
 OPB Bus: On-chip Peripheral Bus
 It is optimized to connect lower speed, low throughput peripherals,
such as serial and parallel port, UART, etc.
 Crucial features of OPB are:
 Fully synchronous operation,
 Dynamic bus sizing,
 Separate address and data buses,
 Multiple OPB bus masters,
 Single cycle transfer of data between bus masters,
 Single cycle transfer of data between OPB bus master and OPB
slaves, etc.
 Instead of tristate drivers OPB uses distributed multiplexer.
42

43. CoreConnect Bus
 OPB Bridge:
 PLB masters gain access to the peripherals on the OPB bus through
the OPB bridge.
 The OPB bridge acts as a slave device on the PLB and a master on
the OPB.
 It supports word (32-bit), half-word (16-bit) and byte read and write
transfers on the 32-bit OPB data bus.
 The OPB bridge performs dynamic bus sizing, allowing devices with
different data widths to efficiently communicate.
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44. CoreConnect Bus
 DCR Bus: Device Control Register Bus
 It is a single master bus mainly used as an alternative relatively low
speed datapath to the system for:
(a) passing status and setting configuration information into the
individual device-control-registers between the Processor Core and
others SoC constituents (Auxiliary Processors, On-Chip Memory,
System Cores, Peripheral Cores, etc.); and
(b) design for testability purposes.
 DCR is synchronous bus based on a ring topology implemented as
distributed multiplexer across the chip.
 It consists of a 10-bit address bus and a 32-bit data bus.
44

45. IBM CoreConnect Vs ARM AMBA Architectures
45

46. Bus Sockets and Bus Wrappers
 Using a standard SOC bus for the integration of different reusable IP
blocks has one major drawback.
 Standard buses specify protocols over wired connections
 An IP block that complies with one bus standard cannot be reused
with another block using a different bus standard.
 An approach to overcome this is to employ a hardware “socket”, i.e.
bus wrapper is used.
 Core-to-Core communication is handled by the interface wrapper.
46

47. Bus Sockets and Bus Wrappers
 OCP - Open Core Protocol.
 The OCP defines a point - to – point interface between two
communicating entities such as two IP cores using a core - centric
protocol.
 A system consisting of three IP core modules using the OCP and bus
wrappers is shown in Figure.
 One module is a system initiator, one is a system target, and another is
both initiator and target.
47

48. Analytic Bus Models
 Contention and Shared Bus:
 Contention occurs wherever two or more units request a shared
resource that cannot supply both at the same time.
 When contention occurs, either (1) it delays its request and is idle until
the resource is available or (2) it queues its request in a buffer and
proceeds until the resource is available.
 As contention and queues develop at the “bottleneck” in the
system, the most limiting resource is the source of the contention,
and other parts of the system simply act as delay elements.
 Buses often have no buffering (queues), and access delays cause
immediate system slowdown.
 The analysis on the effects of bus congestion depends on the
access type and buffering.
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49. Analytic Bus Models
 Contention and Shared Bus:
 Generally there are two types of access patterns:
1. Requests without Immediate Resubmissions:
Once a request is denied, processing continues despite the delay in
the resubmission of the request.
2. Requests Are Immediately Resubmitted:
A program cannot proceed after a denied request. It is immediately
resubmitted.
The processor is idle until the request is honored and serviced.
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50. Thank You…
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This presentation is published only for Educational Purpose