Sangbin Jeon has studied electrical engineering at Korea University and Seoul National University. He is currently pursuing a Master's degree in electrical engineering at Seoul National University, with a GPA of 4.06/4.30. His research has focused on semiconductor device fabrication and analysis of leakage currents in transistors. He has worked on projects for Samsung involving DRAM and logic devices. Jeon has published several journal papers and presented at multiple conferences on topics related to MOSFETs, FinFETs, and random telegraph noise. He is skilled in TCAD simulation, nanofabrication techniques, and semiconductor characterization equipment.

1. Resume
Sangbin Jeon
Department of Electrical Engineering, Seoul National University, Seoul, Republic of Korea
E-mail : savijeon@gmail.com Mobile : +82-10-8378-6006
Education
Korea University, Seoul, Republic of Korea
B.S. in School of Electrical Engineering, Mar. 2008 – Feb. 2014 (including 2 years of Korean
military service)
Coursework includes : Device Physics, Biology, Device fabrication, Electrical circuit, Signal
and system
GPA 3.78 /4.50 (Overall) 3.83/4.50 (Major)
Seoul National University, Seoul, Republic of Korea
M.S in School of Electrical Engineering, Mar. 2014 – Feb. 2016 (Expected)
Coursework includes : Bioelectronics, Semiconductor Device, Bioelectrical and Computer
Engineering, Nanoelectronic device
GPA: 4.06/4.30 (Overall) 4.06/4.30 (Major)
Thesis : Analysis of leakage current according to the impact of bulk traps in strained n-
FinFETs
Research Experience
Nanotronics Laboratory, Korea University
Undergraduate Research Participation Program, Sep. 2014 – Dec. 2014
- Fabrication of Silicon Nano wire FET using transferring
Device Research Laboratory, Seoul National University
Master Student, Mar. 2014 – Feb. 2016 (Expected)

2. - Cooperate with Samsung Cooperation (DRAM project)
GIDL current at bulk MOSFET, Parasitic capacitance at bulk MOSFET, Random Telegraph
Noise of MOSFET
- Cooperate with Samsung Cooperation (Logic device project)
GIDL current at FinFET, Hot carrier injection at FinFET
Beelee Chua’s lab, Korea University
Researcher, Jan. 2016 –
- Medical devices, Insulin pumps, Sensors.
Teaching Experience
Device Research Laboratory, Seoul National University
- Teaching Assistant for “Topics in Semiconductor Device”, Spring 2015
- Teaching Assistant for “Advanced Semiconductor Device-next generation semiconductor
device”, Fall 2015
Skills
Computer : TCAD simulation , MATLAB, C++
Nanofabrication : Photolithography, Molecular Beam Epitaxy, PVD
Research Equipment : Cascade Probe station , HP Semiconductor Parameter Analyzer
(4156B), Low Noise Current Preamplifier(SR570), Dynamic Signal Analyzer (35670A),
B1500A
Volunteer Activity
Cambodia Volunteer camp, Feb 06 2010 ~ Feb 28 2010
Korean, Korean culture guide, Jul 08 2010 ~ Sep 15 2010

3. Scholarships & Awards
Korea University
- Honors Scholarship, Fall 2008 - Honors Scholarship, Spring 2009
- Honors Scholarship, Spring 2010
- Academic Excellent Award, Fall 2013
Seoul National University
- Brain Korea 21 plus, Fall 2014 - Brain Korea 21 plus, Fall 2015
- Merit Based Scholarship, Fall 2014
- Lecture and Research Scholarship, Spring 2015
IEEE Daejon Section
- Best paper award, Dec 2014
Publication
Journal Papers
Sung-Won Yoo, Joonha Shin, Youngsoo Seo, Hyunsuk Kim, Sangbin Jeon, Hyunsoo Kim,
and Hyungcheol Shin, “Characterizing traps causing random telegraph noise during trap-
assisted tunneling gate-induced drain leakage”, Solid-State Electronics - vol. 109, July,
2015. [SCI]
Joonha Shin, Sangbin Jeon, Hyun Suk Kim, and Sung-Won Yoo, “Analysis on the variable
junction leakage in MOS transistors due to interaction between two traps”, Japanese Journal
of applied physics - vol. 54, no. 3, Mar. 2015.[SCI]
Youngsoo Seo, Sung-Won Yoo, Joonha Shin, Hyunsoo Kim, Hyunsuk Kim, Sangbin Jeon
and Hyungcheol Shin, “Extraction of distance between interface trap and oxide trap from
random telegraph noise in gate-induced drain leakage”, Journal of Nanoscience and
Nanotechnology (Accepted, under publication), [SCI]
Sangbin Jeon, Sung-Won Yoo, Youngsoo Seo, and Hyungcheol Shin, “Extraction of Gate
Induced Drain Leakage(GIDL) at room temperature using extrapolation at bulk MOSFET”,
Japanese Journal of applied physics (Submitted), [SCI]
Conference papers

4. Sangbin Jeon, Sung-Won Yoo, Hyoungwoo Ko, Kyul Ko, and Hyungcheol Shin, "A method
for extracting parasitic capacitance at planar MOSFET", IEIE Fall Conference, Wonju, Korea,
Nov 2015
Sangbin Jeon, Sungwon Yoo, Hyunseul Lee, Youngsoo Seo, Hyoungwoo Ko, Kyul Ko,
Hyunok Jeon and Hyungcheol Shin, “New method for extracting Gate Induced Drain
Leakage (GIDL) at planar MOSFET”, IEIE Summer Conference, Jeju, Korea, Jun 2015
Sangbin Jeon, Hyunsuk Kim, Dokyun Son and Hyungcheol Shin, “Analysis of Strained
Bandgap Narrowing Effect on Gate-Induced Drain Leakage(GIDL) in 7nm node
FinFET”,The institute of Electronics and Information Engineers Symposium, Daejeon, Korea,
Dec 2014
Other 10 presentations in conference meeting