Yiqin Wang
*811 Camino Pescadero Room 1124 *Goleta, CA 93117 *Cell Phone: (805) 886-4683
*E-mail: yiqin@umail.ucsb.edu
OBJECTIVE
A summer internship in electrical engineering research requiring lab experience,
quantitative skills, and familiarity with designs.
SUMMARY OF QUALIFICATIONS
 Three years of project work on circuit analysis, circuit testing and logic
fabrication
 Developed skills including: measurement, coding control circuits, designing and
problem-solving
 Software competencies: Arduino, Matlab, C++ programming, Microsoft Office
 Fluent communication in English and Chinese, conversational Japanese
EDUCATION
B.S., Electical Engineering. University of California, Santa Barbara, expected June 2017
Junior Thesis: Nanotechnology, Signal Design and Communication
GPA: 3.29
Relevant Course work:
 Circuit design and testing
 Signal processing and designs
 Logic designs
 Semiconductor
 Communication design
 Programming
SPECIAL SKILLS
Leadership and participation in laboratory
 Assisted colleagues in designing, implementing and presenting projects in labs.
 Co-organized and –facilitated teaching assistant in debugging and testing circuits.
 Contributed to solving problems with others and sharing ideas
Advanced design abilities and attention to detail skills
 Used Arduino to model particular circuits and monitor the signal
 Checked the project constantly and tried to fully understand and fix the problems
on my own at first time
 Presented various solutions for signal problem and compared each other to
determine the best answers
Illustrated presentations skills and communication skills
 Performed fluent speeches about science research in front of crowd
 Consulted questions about projects and researches with direct contact with
professors
Organized assembling abilities
 Built most circuit projects in laboratory by hands and tools such as oscilloscope,
power supply and function generator
 Packaged different electrical elements together precisely and swiftly
 Redesigned the blueprint when mistakes occur

resume Yiqin Wang

  • 1.
    Yiqin Wang *811 CaminoPescadero Room 1124 *Goleta, CA 93117 *Cell Phone: (805) 886-4683 *E-mail: yiqin@umail.ucsb.edu OBJECTIVE A summer internship in electrical engineering research requiring lab experience, quantitative skills, and familiarity with designs. SUMMARY OF QUALIFICATIONS  Three years of project work on circuit analysis, circuit testing and logic fabrication  Developed skills including: measurement, coding control circuits, designing and problem-solving  Software competencies: Arduino, Matlab, C++ programming, Microsoft Office  Fluent communication in English and Chinese, conversational Japanese EDUCATION B.S., Electical Engineering. University of California, Santa Barbara, expected June 2017 Junior Thesis: Nanotechnology, Signal Design and Communication GPA: 3.29 Relevant Course work:  Circuit design and testing  Signal processing and designs  Logic designs  Semiconductor  Communication design  Programming SPECIAL SKILLS Leadership and participation in laboratory  Assisted colleagues in designing, implementing and presenting projects in labs.  Co-organized and –facilitated teaching assistant in debugging and testing circuits.  Contributed to solving problems with others and sharing ideas Advanced design abilities and attention to detail skills  Used Arduino to model particular circuits and monitor the signal  Checked the project constantly and tried to fully understand and fix the problems on my own at first time  Presented various solutions for signal problem and compared each other to determine the best answers Illustrated presentations skills and communication skills  Performed fluent speeches about science research in front of crowd  Consulted questions about projects and researches with direct contact with professors Organized assembling abilities  Built most circuit projects in laboratory by hands and tools such as oscilloscope, power supply and function generator  Packaged different electrical elements together precisely and swiftly  Redesigned the blueprint when mistakes occur