This document is a curriculum vitae for Neetesh Bhardwaj, an embedded systems and VLSI design engineer. It summarizes his professional qualifications including a Master of Technology degree in VLSI design and embedded systems. It also lists his educational background and projects including designing an SRAM circuit using FinFET technology and developing automatic light and visitor detection systems.

1. OBJECTIVE
PROFESSIONAL QUALIFICATION
EDUCATIONAL QUALIFICATION
CURRICULUM VITAE
Sanjay Colony S.A.F. Road
Morena (M.P.) Pin : 476001
Mob: +91-7795613687, +91-9425738418
NEETESH BHARDWAJ E-mail:-- bhardwajneetesh18@gmail.com
(VLSI Design and Embedded Engineer) bhardwajneeraj287@gmail.com
To excel in the cutthroat competitive environment using my talent and acquired and also to
work in professional managed companies where creativity and hard work are rewarded and
preferred.
 Master of Technology in stream with VLSI Design and Embedded System from RGPV,
Bhopal and research project is finished in ABV-IIITM, Gwalior, M.P.
 B.E. IN ELECTRONICS & COMMUNICATION ENGG. From RGPV BHOPAL (M.P.) in 2010
with 70 % (1st
division).
 10th
passed from M.P. Board, Bhopal (M.P.) in 2002 with 79 %
 10+2 passed from M.P. Board, Bhopal (M.P.) in 2005 with 70 %
 M.Tech running in VLSI DESIGN & EMBEDDED SYSTEM from Atal Bihari Vajpayi-
Indian Institute of Information technology and mgmt. (ABV-IITM), Gwalior, M.P.
 Programming Language: C-programming Certified by E-biz Technocrat pvt.lmt.
 Seminar Delivered:-- Seminar based on Networking & GPRS/GSM.
 Professional Knowledge:-
I have knowledge about Electronic Design Automation (EDA) and IC-CAD tools. I have
worked on numerous EDA tools such as, Tanner EDA package, Synopsys EDA Package,
Cadence EDA Package, Silvaco EDA package and Mentor Graphics EDA Package. I

2. have also worked on Xilinx ISE Design suit and Synopsys VCS package for Verilog-HDL
programming.
 Projects:--
1. I have worked on M.Tech research title “Highly Noise Immune Power Gated FinFET
Based SRAM Design”, which is based on static memory circuit in FinFET based
technology with EDA tool Silvaco Gateway, Tanner S-edit and Synopsys HSPICE.
2. Major project on Automatic room light controller & visitor person detector at the
basis of IR device. It is basically a infrared energy sensors which absorb the infrared
energy and in this in-built 555 timer and counter circuit detected the persons whose
are go through. The counter is up and down manner that means entering the room
the counter work as a up and vice versa.
3. Minor project on clapping switching system. It is a microphone sound based circuit
which detected clapping sound in microphone and circuit is connected to battery
and will flow there.
 Research Publication:--
1. Neetesh Bhardwaj, Vikas Mahor, Manisha Pattaniak,“Robust FinFET Based Highly
Noise ImmunePower Gated SRAM Circuit Design”, ICCN-2015,ID:139
2. Neetesh Bhardwaj, Dharmendra Kushwah,“A Novel Stack Based Power Gated
FinFET SRAMDesign”, IJAIR,ISSN:2278-7844.
 Training :--
1. Two months practical training with full time Professional Certificate Programmer In
Software Programming & IT Applications Development under the Project
“Advance Training For Professionals” in A.V.B. IIITM COLLEGE OF GWALIOR . During
in this period , we trained in C, C++, J2SE, J2EE, C#&ASP.NET, ANDROID SYSTEM,
CLOUD COMPUTING, ORACLE & SOFT SKILLS.
2. Four weeks practical training in BSNL MORENA. During in this training period , we
work on frequency banding which telephone signals are worked and modems with
interfaces, transmitting lines etc.
Additional Information / Achievements:---
 Secured 5TH
Position in G.K. in College Competition.
 I am awarded by ShriRam Talent Search-2005 STS CERTIFICATE Program organized
by SHRIRAM GROUP OF COLLEGES, BANMORE.
 Hold 1st
position for throughout 5 years in school examinations (8th
to 12th
) & also

3. topper in B.E.
Key Skills:---
Father’s name : Mr. Krishna Kant Bhardwaj
Date of birth : 18.07.1988
Marital status : Single
Language known : English, Hindi
Permanent address : Sanjay Colony
S.A.F. Road Morena, [M.P.]
Pin-476001
Salary expected : Negotiable
DECLARATION
I solemnly declare that the above statements made by me are true to the best of my
knowledge and belief.
Date: ..................... (Neetesh Bhardwaj)
Place: .. MORENA.. Signature
HOBBY & INTRESTS:---
 Travelling on historical places.
 Studying our subject related information.
 Reading books of subjective.
 Playing & Showing CRICKET MATCH’S.
 Internet surfing & Growing knowledge.
 Manufacturing & Designing of IC’S & Printed circuit boards.
 Knowledge of communication transmission & channels with various equipment’s.
 Basic knowledge of Mobile, Satellite & Microwave communication with the
Application of TV & Radar system.
 Knowledge of Software Programming & IT Applications Development.
PERSONAL PROFILE: