Rajendaran Rathinasabapathy is a PCB design engineer with over 9 years of experience designing PCBs for various industries including telecom, aerospace, medical, and automotive. He has extensive experience using ECAD tools like Mentor Graphics, Cadence, and PADS to design boards with up to 36 layers. He is certified as an Advanced Certified Interconnect Designer by IPC and has demonstrated strong work ethic, professionalism, and commitment to customer satisfaction throughout his career. Currently based in Bengaluru, India, he is looking for new opportunities in PCB design.

1. RAJENDARAN.R Mobile No: +91 9739447611
Email: rajendaran.r@gmail.com Optional No: +91 9894326367
CAREER SUMMARY
Around 9 years of strong PCB design experience in all kinds of PCB’s using various
ECAD tools for various products like Telecom, Aerospace, medical, Automotive domains.
Demonstrated a strong work ethic, professionalism, team player and drive for quality and strong
commitment towards customer delight on day to day activity. Certified from IPC, an “Advanced
Certified Interconnect designer (CID+) and strive forward for a world class PCB Designer.
CORE SKILLS:
 Designed PCBs for various domains like telecom, aerospace, medical & automotive.
 Designed PCBs from 1 to 36 layers in various product lines.
 Designed for high speed board designs with high speed PCB design rules, minimize cross
talk, techniques to overcome EMI/EMC issues and SI
 Knowledge on PCB & PCBA level failures and preventive design techniques.
 Exposure to IPC standards for PCB library creation and layout design
 Best practices for DFx (DFM, DFA & DFT) in layout.
 PCB panel design for best manufacturing benefit
 Knowledge on placement for RF, high speed, DDR2, DDR3, interfaces like Ethernet,
SATA, PCI, PCI-E, memory sections, AC-DC, DC-DC converters, Audio-video sections.
 Good knowledge on stack up development for impedance, EMIEMC, switch noise etc
 Smart placement and routing techniques like copy circuit and use of optimum tool
options to minimise layout duration and maximise accuracy.
 Exposure to ROHs compliance
 Schematic design support and resolving packaging/net-listing issues.
 Exposure on thermal management.
 Knowledge of conformal coatings and its rules in assembly
 Knowledge on GCD-DMS for database management for components.
 Technical support and interaction with fab and assembly vendors
 Team player & work with contract resources to extract quality output from them.
 Accountability for Quality, delivery, schedule and cost.

2. TOOLS KNOWN:
 Mentor Graphics: DxDesigner – Expedtion PCB flow
 Design Capture – Expedition PCB flow
 Design Entry – PADS Layout flow
 PADS Logic – PADS Layout flow
 Cadence: Design Entry – Allegro flow
 Concept HDL – Allegro flow
 DFx: Valor NPI
 CAM: CAM350, GC-Prevue.
PROFESSIONAL EXPERIENCE:
4. Staff Engineer – Broadcom Limited, Bangalore, India (21st
Dec, 2015 to 31st
May, 2016)
 Tools: Design Entry – Allegro flow
 Responsible for effort estimation, schedule, layout design
 Interaction with cross functional team for layout design.
 Requirement analysis for deriving electrical and DFx constraints.
 Follow Broadcom layout standards
 Participating in review meetings.
 Agile for design release
3. Senior Engineer – UTC Aerospace systems, Bangalore, India (30th
Jan, 2012 to 18th
Dec,
2015)
 Tools: DxDesigner – Expedition PCB & Concept HDL – Allegro, Design Entry –Allegro
 Attending the project kick off meeting to understand the scope of work.
 Analyse the inputs for responsible for effort estimation, schedule and resource allocation.
 Interaction with cross functional teams for inputs
 Resolving the packaging issues in the schematic tool for forward integration.
 Optimum placement and routing techniques to complete the design activity within the
schedule
 Follow respective SBU standards and checklist
 Support library activity – Symbol, cell creation and review
 Use of IPC calculators for electrical constraints.
 Use of LP wizard for Land pattern creation
 Attending artefact review meeting with all cross functional team members for sign-off.
 Attending telecon’s with global team members for design related queries/issues.

3.  Ability to work with contract resources to extract quality output within the schedule time.
 Involved in continuous improvement training related to PCB design process.
 Implement IPC standards.
 Better understanding of datasheets for LP creation, layout specific guidelines etc
 Tracking of day to day quality issues and review periodically to reduce the quality issues.
 Accountable to Quality, schedule, delivery and sign-off
 Knowledge on GCD-DMS for library support.
 Interaction with manufacturing vendors for technical queries.
 Valor NPI for DFM
 Work along with multiple designers using Team pcb for quick turn layout designs.
 ECAD-MCAD handoffs for mechanical review.
 Output generation and documentation based on SBU standards.
 Team center for documentation and release.
 Work effectively and participate in regular interaction with global team and understand
better understanding and quality.
 Tag team with global designers for quick turn layout.
2. Senior Designer – PWB Design, Sienna ECAD Technologies, Bangalore, India (10th
Aug,
2009 to 21st
July, 2011)
 Tools: DxDesigner – Expedition, Design Capture – Expedition, PADS Logic – PADS
Layout, Design Entry – Allegro
 Travel directly to the client location and work with them.
 Interact with cross functional team to understand the requirements.
 Follow the client’s specific standards and implement their layout guidelines.
 Implement best placement and routing techniques in layout to reduce time
 Setting up physical and spacing constraints as per the requirement.
 Output generation as per the client’s preferred standards and format
 Work with CAM engineering for DFM check
1. PCB Design Engineer – Nimbeon Intertechnologies, Coimbatore, India (03rd
Aug 2006
to 07th
Aug, 2009)
 Tools: Design Entry – PADS Layout, Design Entry – Allegro, Design Capture -
Expedition
 Worked on land pattern creation and BOM review.
 Work with senior designers and support layout activity.
 Share the layout activity with peers for quick turn layout activity

4.  Interact with cross functional team for requirements, queries and issues.
 Work with quality team for design review and DFM report.
 Worked on optimum placement, constraint setup and routing.
 Interact with global team for inputs and regular process
EDUCATION:
 MBA in International Business from ICFAI University (Distance education),
 B.E. in Electronics and communication engineering from Sapthagiri college of
Engineering, Anna University in 2006 with 72 %
 Higher secondary from Government Higher Secondary School, State board in 2002
with 89 %
 SSLC from Government Higher Secondary School, State board in 2000 with 80 %
TRAINING AND CERTIFICATION:
 Advanced certified interconnect designer CID+, IPC council
 Valor NPI class room training
 Attended various interpersonal skills – Business communication, Cross cultural training,
Conflict management, Negotiation skills, Ethics and compliance
AWARDS:
 CI Event of the Quarter, team member – UTC Aerospace systems
 Project of the Quarter, team member – UTC Aerospace systems
 Partnership award – BASICS – UTC Aerospace systems
PERSONAL DETAILS:
 DOB 27th
June, 1985
 Marital status Married
 Passport Available
 Visa B1 multiple entry visa for USA valid up to 2023
 Languages English, Tamil, Kannada
 Address Flat No A-202, BM Silver woods, 27th
Main Extn, HSR Layout
Sector 2, Somasundarapalaya, Behind Power house, Bangalore – 560102

5. DECLARATION:
I here with declare that all the details given above are true to the best of knowledge.
Date :
Place: Bengaluru Rajendaran
Rathinasabapathy

6. DECLARATION:
I here with declare that all the details given above are true to the best of knowledge.
Date :
Place: Bengaluru Rajendaran
Rathinasabapathy