Radiation exposure can negatively impact CMOS circuits in several ways: 1) Threshold voltages (Vt) for NMOS and PMOS transistors increase, reducing transistor switching speeds and increasing leakage currents. 2) Carrier mobility (μ) decreases over time, slowing the rising and falling edges of signals and increasing dynamic power consumption. 3) Increased leakage currents between drain/source and between adjacent transistors can prevent proper switching and increase static power usage. 4) Timing issues may cause glitches or circuits to fail to meet timing requirements for synchronous designs. Additional design margins are recommended for space applications.

1. Radiation effects on
CMOS
By Francesco Poderico
www.neutronix.co.uk

2. TID effects on digital CMOS circuits
As we are talking on digital circuits we are interested to understand how the
speed (max. frequency) is effected and how the input and output threshold
are effected as well.
• Ron = 1/[μ Cox(W/L) (Vgs-Vt)] (as with theTID μ decrease, Vt increase =>
Ron increase)
• Gm = μ Cox(W/L) (Vgs-Vt) ( therefore Gm decrease)
• Vt increase (in module)
• Leakage current between drain and source increase
• Leakage current between adjacent MOS increase

3. TID effects on digital CMOS circuits
• Vtn on N-MOS and P-MOS, (note thatVtno decrease first and then
increase)

4. TID effects on digital CMOS circuits
• A reduction ofVt on N-MOS may prevent MOS to switch off
• Even the Id/Vgs is reduced prevent N-MOS to switch off as well

5. TID effects on digital CMOS circuits
• Vtn increase may prevent N-MOS from switch ON

6. TID effects on digital CMOS circuits
• The leakage current between D and S may prevent NMOS to switch OFF!
• The leakage current between MOS ,may prevent the circuits to work
correctly
• Increase of static power

7. TID effects on digital CMOS circuits
• An increase (abs) ofVtp can prevent PMOS to switch ON

8. Question
• On a LEO application do you prefer to use an NAND gate or an NOR gate ?

9. Solution : NAND gate

10. Timing issues
• μ decrease => the rising and falling edge slows down.This may cause
unwanted glitches for
• not synchronous designs, and not meeting the timing for synchronous
designs.
• Solution => use only synchronous design if possible, add an high margin
(e.g. 50%) for micro-space solutions!

11. Dynamic Power
• As consequences of slower rising and falling edge, the dynamic power will
increase!
• Solution on micro-space product add a further margin of 20% on the power
budget!