This document describes a VHDL code for a simple finite state machine with 3 states (a, b, c) that is triggered by a clock signal and reset. The state transitions depend on the current state and the value of an input signal w. An output signal z is assigned the value 1 when the state is c, and 0 for all other states.

4. Ejemplo:
1 library ieee;
2 use ieee.std_logic_1164 .all;
3
4 entity ejmss is
5 port( w : in std_logic;
6 clk, rstn : in std_logic;
7 z : out std_logic);
8 end ejmss;
9
10 architecture behaviour of ejmss is
11 type estado is (a,b,c);
12 signal y: estado;
13 begin
14 process(clk,rstn)
15 begin
16 if rstn = '0' then y <= a;
17 elsif (clk = '1' and clk'event) then
18 case y is
19 when a =>
20 if w = '0' then y <= a;
21 else y <= b; end if;
22 when b =>
23 if w = '0' then y <= a;
24 else y <= c; end if;
25 when c =>
26 if w = '1' then y <= c;
27 else y <= a; end if;
28 end case;
29 end if;
30 end process;
31 process(y,w)
32 begin
33 z <= '0';
34 case y is
35 when c => z <= '1';
36 when others => z <= '0';
37 end case;
38 end process;
39 end behaviour;