This document provides a schematic diagram of an electronic circuit board. It shows various electronic components connected by lines, including capacitors, resistors, transistors, and ports. Labels indicate power sources like VBAT and ground connections. Pins and ports are numbered and labeled for components like the display interface and audio connections.

1. F1 CR1 D1 VBAT
J14 SMD200F-2 SMCJ5.0A S3A
1
2
VBAT VBAT
121
122
123
124
1
TP2 22-05-7025 + C43 R46
330uF_10V 330R
1 2
2
3 4
3 HFLP SYSCLK2 4
5 6
DMIC34CLK 3
A
3 HFLN 7 8
4,5 RESETn DMIC12CLK 3
HSR 9 10 VDMIC_1V8_VAMIC2
HSL 11 12
DMIC34DAT_MIC2N 3 HSMG-C190
TP1
PONKEY2 13 14
DMIC12DAT_MIC2P 3 LD1
15 16 DSI0_0
3 HFRN 17 18 DSI0_1
K
3 HFRP EARN 19 20 DSI0_2
EARP 21 22 DSI0_3
MICBIAS.GND 23 24 DSI0_5
25 26 DSI0_4
3 LINLP
27 28 SM_ADQ0 DSI0_[5..0] 4
3 LINRP
VAMIC1 29 30 SM_ADQ1
31 32 SM_ADQ2
3 MIC1AP
33 34 SM_ADQ3
3 MIC1AN MICBIAS.GND 35 36 SM_ADQ4 L8
SM_FBCLK 37 38 SM_ADQ5 VBAT LQH3NPN2R2NM0
SM_CKO 39 40 SM_ADQ6
5 SM_ADVn 41 42 SM_ADQ7
4
2
5 SM_WEn 43 44 SM_ADQ15 R52 VBAT U14 +3.3V
45 46 SM_ADQ14 Not populated 100K R45
L1
L2
5 SM_OEn
R1 0R SM_WAIT1n 47 48 SM_ADQ13 5 1
SM_CS1n 49 50 SM_ADQ12 VIN VOUT
5 CSn
R2 0R SM_CS0n 51 52 SM_ADQ11 8 10 R55 0R
53 54 SM_ADQ10 PM_GPIO4 R53 0R 6 VINA FB 1M2 C55
5 PM_GPIO40 EN
Not populated 55 56 SM_ADQ9 7 10uF
3 PM_GPIO41 PS_SYNC
EPAD
57 58 SM_ADQ8 C54 C57
4 PM_GPIO42 MICBIAS.GND 59 60 PM_GPIO4 SM_ADQ[15..0] 5 10uF 100nF 9 3
GND PGND
4 LCD_D[15..0] PM_GPIO1 61 62 TPS63030DSKT
11
LCD_D0 63 64 I2C3_SCL 3,4 R54
I2C3_SDA 3,4
LCD_D1 65 66 220K
PWMOUT1 4
LCD_D2 67 68
PWMOUT2 4
LCD_D3 69 70 VIDEOCTRL
LCD_D4 71 72
LCD_D5 73 74 I2C_IP_SCL 4
I2C_IP_SDA 4
LCD_D6 75 76
INT_ISP1763A 5
LCD_D7 77 78
LCD_D8 79 80 CLKOUT1 4
I2C1_SDA 4
LCD_D9 81 82
LCD_D10 83 84 I2C1_SCL 4
AV8100_CVBS
LCD_D11 85 86
AP_GPIO68 4
LCD_D12 87 88 AP_GPIO151 L7
LCD_D13 89 90 AP_GPIO152 VBAT LQH3NPN2R2NM0
LCD_D14 91 92
IP_GPIO1 4 AP_GPIO[152..151] 4
4 LCD_D[31..24] LCD_D15 93 94 IP_GPIO0
PENIRQn 3
4
2
LCD_D24 95 96 Not populated R31 VBAT U11 +1.8V
AP_GPIO162 5
LCD_D25 97 98 100K
L1
L2
LCD_D26 99 100 GSM_TX_PWR_LEVEL 5 1 R30 0R
LCD_D27 101 102 VIN VOUT
CSI0_[7..0] 4
LCD_D28 103 104 CSI0_1 8 10 R34
LCD_D29 105 106 CSI0_0 PM_GPIO1 R32 0R 6 VINA FB 560K C39
LCD_D30 107 108 CSI0_6 7 EN 10uF
PS_SYNC
EPAD
LCD_D31 109 110 CSI0_7 C38 C46
111 112 CSI0_4 10uF 100nF 9 3
4 LCDB_DE GND PGND
113 114 CSI0_5
4 LCDB_VSO
115 116 CSI0_2 TPS63030DSKT
4 LCDB_HSO
11
117 118 CSI0_3 R33
4 LCDB_CLK
119 120 220K
125
126
127
128
J2
QTH-060-02-L-D-A
A01 12-05-2011 - Initial version GH
Rev Date Revision History: Drawn Approved
Scale : Product : MOB-SKY-S9500-AVI
Sheet Size : A3 Document Number : SCH-00110-A01
2
Folio :
5 Title : CONNECTORS www.calao-systems.com
This drawing may not be reproduced without CALAO Systems prior written consent

2. Not populated for 24bits LCD Display
RN2 0R
1 8
2 7
3 6
4 5
RN3 0R
1 8
2 7
LVDS WIRING: The majority of 24bits display panels
3 6 require the 2 MSB of each color to be transferred over
4 5
the 4th serial data output Y3.
RN6 0R
1 8
2 7
3 6
4 5
RN8 0R
1 8
2 7
3 6
4 5
RN11
0R
1 8
2 7
3 6
4 5
RN13
0R
1 8
2 7 +1.8V +3.3V +3.3V
3 6
4 5
26
44
34
1
9
U2
RN1 0R
IOVCC
IOVCC
VCC
LVDSVCC
PLLVCC
1 8 50 49
CSI0_[7..0] 2
2 LCD_D[15..0] 2 7 48 47 CSI0_1
2,5 RESETn
LCD_D0 R0 3 6 51 48 46 45 CSI0_0
LCD_D1 R1 4 5 52 D0 Y0M 47 44 43 CSI0_6
LCD_D2 R2 54 D1 Y0P 42 41 CSI0_7
LCD_D3 R3 RN4 0R 55 D2 40 39 CSI0_4
LCD_D4 R4 1 8 56 D3 46 38 37 CSI0_5
ERF8-025-01-L-D-RA-L-TR
LCD_D5 R5 2 7 3 D4 Y1M 45 36 35 CSI0_2
LCD_D6 R6 3 6 50 D6 Y1P 34 33 CSI0_3
D27 AP_GPIO[152..151] 2
LCD_D7 R7 4 5 2 32 31 AP_GPIO152
RN5 0R D5 42 30 29 AP_GPIO151
LCD_D8 G0 1 8 4 Y2M 41 28 27
D7 Y2P I2C1_SCL 2
LCD_D9 G1 2 7 6 26 25
D8 I2C1_SDA 2
LCD_D10 G2 3 6 7 24 23
D9 3 YN CLKOUT1 2
LCD_D11 G6 4 5 11 38 22 21 I2C_IP_SDA 2
D12 Y3M 3 XN
LCD_D12 G7 RN7 0R 12 37 20 19
D13 Y3P 3 YP I2C_IP_SCL 2
LCD_D13 G3 1 8 14 18 17
D14 3 XP I2C3_SCL 2,3
LCD_D14 G4 2 7 8 16 15
D10 I2C3_SDA 2,3
LCD_D15 G5 3 6 10 40 DSI0_4 14 13
D11 CLKOUTM PM_GPIO42 2
2 LCD_D[31..24] 4 5 39 DSI0_5 12 11
CLKOUTP SYSCLK2 2
LCD_D24 B0 15 DSI0_3 10 9 R9 0R
D15 PWMOUT1 2
LCD_D25 B1 RN10 0R 19 DSI0_2 8 7 R8 0R
D18 PWMOUT2 2
LCD_D26 B2 1 8 20 DSI0_1 6 5
LCD_D27 B3 2 7 22 D19 DSI0_0 4 3 Not populated
D20 VLED
LCD_D28 B4 3 6 23 2 1
D21 2 DSI0_[5..0]
LCD_D29 B5 4 5 24
LCD_D30 B6 16 D22 J5 R11 0R
D16 +1.8V
LCD_D31 B7 RN12 0R 18 VBAT VBAT
1 8 D17 R10 0R +3.3V
2 7
3 6 27
4 5 28 D24
30 D25
25 D26
D23
31
CLKIN
17
CLKSEL
2 LCDB_HSO
2 LCDB_VSO
+1.8V R7 4K7 32
2 LCDB_DE SHDN
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2 IP_GPIO1
2 LCDB_CLK
2 AP_GPIO68
SN75LVDS83BDGG
5
13
21
29
33
35
36
43
49
53
+1.8V R5 100K
Not populated
R6
100K
A01 12-05-2011 - Initial version GH
Rev Date Revision History: Drawn Approved
+1.8V +1.8V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V
Scale : Product : MOB-SKY-S9500-AVI
C4 C20 C6 C5 C13 C14 C8 C9
Sheet Size : A3 Document Number : SCH-00110-A01
10nF 100nF 10nF 100nF 10nF 100nF 10nF 100nF
4
Folio :
5 Title : LVDS INTERFACE www.calao-systems.com
This drawing may not be reproduced without CALAO Systems prior written consent