Flip-flop working on computers

1. SC Latch Timing Diagram
S C Q
Truth Table
S Q
Latch
C
1
0
1
0
1
0
Input S
Input C
Output Q

2. JK Flipflop Operation
J
CLK
K
S Q
C
Vcc
Vcc
Q
PRE CLR J K CLK Q
0 0 X X X ?
0 1 X X X 1
1 0 X X X 0
1 1 X X — Q
1 1 X X  Q
1 1 0 0  Q
1 1 0 1  0
1 1 1 0  1
1 1 1 1  Q

3. JK Flipflop Timing Diagram
J
CLK
K
S Q
C
Vcc
Vcc
Q
1
0
1
0
1
0
Time
Input J
Input K
Output Q
1
0
Input CLK

4. Transparent D-Latch Timing

5. Transparent D-Latch

6. D Flip Flop

7. Latch & Flip Flop Summary
Latches Flip-Flops
Asynchronous inputs are level sensitive
(active-high or active-low)
Synchronous Control inputs and an
edge-triggering CLK (rising or falling
edge triggered)
SC Latch (AKA RS Latch):
SET and CLEAR inputs. Could think of
those as direct and inverting inputs.
Has an unstable input combination.
SC Flip-Flop:
SET and CLEAR queries at CLK edge.
Has an unstable input combination.
Rare.
(No corresponding latch.
Can’t toggle without a CLK.)
JK Flip-Flop:
Like SC-FF, but unstable input replaced
by toggle mode.
D Latch:
Make D-FF level sensitive. This has
“transparent” and “hold” modes.
D Flip-Flop:
Remove toggle and “inverting” inputs
of JK-FF. Output copies input at CLK
trigger.

8. Clock Signal Details
tw
T 1 sec
↳ f = 3 Hz

9. Making an Edge ‘Detector’
CLK
CLK*
CLK CLK*
CLK
CLK

10. Building a SC Flip Flop
Edge
Detector
S
CLK
C
SET
CLEAR
Q
Q
CLK*

11. Building a JK Flip Flop
J
CLK CLK*
K
Edge
Detector
SET
CLEAR
Q
Q

12. Adding Preset & Clear
J
CLK
CLK*
K
Edge
Detector
Set
Q
Q
Clear
PRESET
CLEAR