Ethernet sniffer projectEthernet sniffer project
Project definition
• Network Ethernet sniffer based on FPGA
board Nexys 4.
• The device has the ability to monitor the
network, to gain information about the
network and the devices by dynamically
changing the Mac address. The project is
implemented HW VHDL language without
software.
Basic configurations and PR
• The UE should be able to monitor own sub
network.
• Once reception Ethernet broadcast message
from another device, UE should recognize
start of frame and notifies the user by output
message.
• Output message should consist of destination
and source MAC, length of message and data.
HLAHLA
PHY
adapter AXI_Ethernet Transaction
control
4 data bus
Axi
interface
Dual Port Ram UART control UART state machine
FT2232
PHY
IP MII to RMII v2.0
The core accept the 16 signal MII interface and provides a six or seven signal
interface to a RMII compliant PHY. Additionally, a fixed 50 MHz reference clock
synchronizes the MII to RMII core with both interfaces.
Protocol Description
Signal from PHY to RMII
Signal from RMII to MII
AXI Ethernet Lite MAC v3.0
Parameterized AXI4 slave interface based on the AXI4 or AXI4-Lite specification
for transmit and receive data dual port memory access. Include independent
internal 2KByte TX and RX dual port memory for holding data for one packet.
Advanced Extensible Interface 4 Lite
(AXI4-Lite)
Read procedure
The most widespread AMBA interface. Connectivity up to 100's of Masters and
Slaves in complex SoC's
AXI Lite protocol
Write procedure
Controller state machine

Ethernet sniffer project

  • 1.
  • 2.
    Project definition • NetworkEthernet sniffer based on FPGA board Nexys 4. • The device has the ability to monitor the network, to gain information about the network and the devices by dynamically changing the Mac address. The project is implemented HW VHDL language without software.
  • 3.
    Basic configurations andPR • The UE should be able to monitor own sub network. • Once reception Ethernet broadcast message from another device, UE should recognize start of frame and notifies the user by output message. • Output message should consist of destination and source MAC, length of message and data.
  • 4.
    HLAHLA PHY adapter AXI_Ethernet Transaction control 4data bus Axi interface Dual Port Ram UART control UART state machine FT2232
  • 5.
  • 6.
    IP MII toRMII v2.0 The core accept the 16 signal MII interface and provides a six or seven signal interface to a RMII compliant PHY. Additionally, a fixed 50 MHz reference clock synchronizes the MII to RMII core with both interfaces.
  • 7.
    Protocol Description Signal fromPHY to RMII Signal from RMII to MII
  • 8.
    AXI Ethernet LiteMAC v3.0 Parameterized AXI4 slave interface based on the AXI4 or AXI4-Lite specification for transmit and receive data dual port memory access. Include independent internal 2KByte TX and RX dual port memory for holding data for one packet.
  • 9.
    Advanced Extensible Interface4 Lite (AXI4-Lite) Read procedure The most widespread AMBA interface. Connectivity up to 100's of Masters and Slaves in complex SoC's
  • 10.
  • 11.