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Aspire 4551 g

This document is a schematics document for a Compal Electronics laptop motherboard. It contains confidential and proprietary information about the board's design. The document provides schematics for the board's various components and subsystems, including the Intel processor, memory interfaces, graphics interfaces, SATA and USB interfaces, and power delivery circuitry. Identification numbers and component models are included.

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A B C D E 1 1 Compal Confidential 2 2 PEW71/91/51 M/B Schematics Document Intel Arrandale Processor with DDRIII + Ibex Peak-M NV N11P-GV2H and N11P-GE 2010-06-07 3 3 REV:1.0 4 4 2009/08/01 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: A B C D Sheet Wednesday, June 30, 2010 E 1 of 56
A B C D E Clock Generator Compal Confidential IDT: 9LVS3199AKLFT Realtek: RTM890N-631-VB-GRT Model Name : NEW71/91 File Name : LA5893P 133/120/100/96/14.318MHZ to PCH Fan Control page 41 page 12 1 1 PEG(DIS) 100MHz PCI-E 2.0x16 5GT/s PER LANE page 4,5,6,7,8,9 CRT(DIS) FDI x8 (UMA) CRT Conn. page 30 2 LVDS Conn. page 29 DMI x4 100MHz 1GB/s x4 MINI Card x2 WLAN, WWAN USB port 12,13 page 34 port 1 page 38 DC/DC Interface CKT. page 42 4 Power Circuit DC/DC page 43~53 3.3V 24MHz ALC272X SPI page 39 port 0 SATA HDD Conn. page 31 TI TPS6017 40 page page 13 SATA CDROM Conn. page 31 LPC BUS 3 33MHz Int. Speaker ENE KB926 Phone Jack x 2 page 40 page 40 page 36 USB/B 2 Ports USB Port 0,2 page 35 Card Reader USB Port9 RTS5160 Audio AMP port 1 Touch Pad Int.KBD page 37 page 37 CPU XDP page 35 page 5 EC ROM LS-5893P page 37 LS-5894P Power/B PCH XDP LID_SW/B 4 page 38 page 21 LS-5895P 3G USB Port10,13 2009/08/01 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification page 35 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A page 35 2 SPI ROM x1 page 32 LS-5896P Power On/Off CKT. USB port 9 page 28 3.3V 48MHz BCM57780 Sub-board LS-5891P page 15 USB port 8 page 35 HDA Codec page 13,14,15,16 17,18,19,20,21 100MHz page 33 RTC CKT. USB port 11 LAN(GbE) RJ45 3 Card Reader RTS5160 PCH 100MHz SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) CMOS Camera HD Audio Intel Ibex Peak-M page 30 PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) Bluetooth Conn USB port 1 USBx14 LVDS(UMA) CRT(UMA) TMDS(UMA) HDMI Level Shift USB conn x3 USB port 0, 2 on USB/B page 35 100MHz 2.7GT/s page 28 HDMI(UMA) port 2 page 10,11 1.5V DDRIII 800/1066 Processor rPGA988A LVDS(DIS) HDMI Conn. BANK 0, 1, 2, 3 Arrandale (UMA/DIS) page 22,23,24,25,26,27 HDMI(DIS) Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2 Dual Channel Intel 133MHz NV N11P-GV2H NV N11P-GE B C D SCHEMATICS,MB A5893 Document Number Rev C 401869 Sheet Wednesday, June 30, 2010 E 2 of 56
A B C D Voltage Rails Power Plane S1 Description S3 VIN N/A N/A N/A Battery power supply (12.6V) N/A N/A N/A B+ AC or battery power rail for power circuit. N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF +VGA_CORE Core voltage for GPU ON OFF OFF +VGFX_CORE Core voltage for Arrandale GPU (only for arrandaleCPU) ON OFF OFF +0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF +1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF +1.05VS_VTTP to +1.05VS_VTT switched power rail for ARD CPU ON OFF +1.05VS_VTT to +1.05VS_PCH power for PCH ON OFF OFF +1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF +1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Vcc Ra/Rc/Re +1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF Board ID +1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF +3VALW +3VALW always on power rail ON ON ON* +3VALW_EC +3VALW always to KBC ON ON ON* +3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* +3V +3VALW to +3V power rail for PCH (Short Jumper) ON ON ON* +3VS +3VALW to +3VS power rail ON OFF OFF +5VALW +5VALWP to +5VALW power rail ON ON ON* +5V +5VALW to +5V switched power rail for PCH (Short resister) ON ON ON* 0 1 2 3 4 5 6 7 +5VS +5VALW to +5VS switched power rail ON OFF +VSBP to +VSB always on power rail for sequence control ON ON ON* +RTCVCC RTC power ON ON ON +V +VS Clock OFF +VSB +VALW OFF +1.05VS_PCH SLP_S1# SLP_S3# SLP_S4# SLP_S5# OFF +1.05VS_VTT 2 Adapter power supply (19V) BATT+ 1 SIGNAL STATE S5 E HIGH HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Full ON Board ID / SKU ID Table for AD channel Device Device Board ID 0 1 2 3 4 5 6 7 0001 011X b Address PCH SM Bus address Device Address Clock Generator (9LVS3199AKLFT, RTM890N-631-VB-GRT) 1001 000Xb DDR DIMM2 1001 010Xb V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V BTO Item UMA ONLY Discrete Discrete Only VRAM Switchable UMA ONLY & OPTIMUS 3G Blue Tooth OPTIMUS NonSG SKU NEW71 NEW91 N11P-GV2H N11P-GE1 N11P-GV2H-A2 N11P-GV2H-A3 Non OPT SKU SG or OPT USB Port Table USB 2.0 USB 1.1 Port 3 UHCI0 BOM Config move to page 56 UHCI1 EHCI1 UHCI2 VRAM BOM Config X7621@: X76198BOL21 ALT. GROUP PARTS 1G SAM UHCI3 X7622@ UHCI4 X76198BOL22 V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BTO Option Table PCB Revision 0.1 0.2 0.3 1.0 1101 0010b DDR DIMM0 V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V BOARD ID Table EC SM Bus2 address Address Smart Battery 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC 2 Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. EC SM Bus1 address 1 ALT. GROUP PARTS 1G HYN EHCI2 UHCI5 UHCI6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 3 External USB Port USB/B (Right Side) USB Port (Left Side) USB/B (Right Side) Camera Card Reader SIM Card Blue Tooth Mini Card(WLAN) Mini Card(GPS) BOM Structure UMA ONLY@ DIS@ DIS ONLY@ X76@ SG@ UMOP@ 3G@ BT@ OPT@ NonSG@ 71@ 91@ GV2H@ GE1@ GV2HA2@ GV2HA3@ NonOPT@ SGOPT@ 3 VRAM P/N : Samsung : SA000035720 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA ABO!) Hynix : SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA ABO! ) 4 4 2009/08/01 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D SCHEMATICS,MB A5893 Document Number Rev C 401869 Sheet Wednesday, June 30, 2010 E 3 of 56
5 4 3 2 1 JCPU1E PEG_IRCOMP R485 1 2 49.9_0402_1% EXP_RBIAS R493 1 2 750_0402_1% RSVD32 RSVD33 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] B24 D23 B23 A22 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_HTX_PRX_N0 DMI_HTX_PRX_N1 DMI_HTX_PRX_N2 DMI_HTX_PRX_N3 D24 G24 F23 H23 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3 D25 F24 E23 G23 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7 D22 C21 D20 C18 G22 E20 F20 G19 FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] 15 H_FDI_FSYNC0 15 H_FDI_FSYNC1 F17 E17 FDI_FSYNC[0] FDI_FSYNC[1] 15 H_FDI_INT C17 FDI_INT 15 H_FDI_LSYNC0 15 H_FDI_LSYNC1 F18 D17 FDI_LSYNC[0] FDI_LSYNC[1] C PCI EXPRESS -- GRAPHICS E22 D21 D19 D18 G21 E19 F21 G18 Intel(R) FDI H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7 15mil DMI DMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2 DMI_PTX_HRX_P3 D A24 C23 B22 A21 B PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS B26 A26 B27 A25 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 PEG_GTX_C_HRX_N15 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N0 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P0 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 PEG_HTX_GRX_N15 PEG_HTX_GRX_N14 PEG_HTX_GRX_N13 PEG_HTX_GRX_N12 PEG_HTX_GRX_N11 PEG_HTX_GRX_N10 PEG_HTX_GRX_N9 PEG_HTX_GRX_N8 PEG_HTX_GRX_N7 PEG_HTX_GRX_N6 PEG_HTX_GRX_N5 PEG_HTX_GRX_N4 PEG_HTX_GRX_N3 PEG_HTX_GRX_N2 PEG_HTX_GRX_N1 PEG_HTX_GRX_N0 C586 C561 C584 C559 C582 C557 C580 C555 C578 C553 C576 C551 C574 C549 C572 C547 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_N0 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] 10mil L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 PEG_HTX_GRX_P15 PEG_HTX_GRX_P14 PEG_HTX_GRX_P13 PEG_HTX_GRX_P12 PEG_HTX_GRX_P11 PEG_HTX_GRX_P10 PEG_HTX_GRX_P9 PEG_HTX_GRX_P8 PEG_HTX_GRX_P7 PEG_HTX_GRX_P6 PEG_HTX_GRX_P5 PEG_HTX_GRX_P4 PEG_HTX_GRX_P3 PEG_HTX_GRX_P2 PEG_HTX_GRX_P1 PEG_HTX_GRX_P0 C585 C560 C583 C558 C581 C556 C579 C554 C577 C552 C575 C550 C573 C548 C571 C546 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_P0 AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30 AJ13 AJ12 RSVD34 RSVD35 AH25 AK26 RSVD36 RSVD_NCTF_37 AL26 AR2 RSVD38 RSVD39 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 SA_DIMM_VREF (CFD Only) SB_DIMM_VREF (CFD Only) RSVD11 RSVD12 RSVD13 RSVD14 AJ26 AJ27 1 @ R61 3.01K_0402_1% R60 3.01K_0402_1% 1 DIS@ @ 1 R59 3.01K_0402_1% 1 @ 2 CFG0 2 2 CFG3 CFG4 2 CFG7 WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1 AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86 B19 A19 R501 0_0402_5% DMI_PTX_HRX_N[0..3] 15 DMI_PTX_HRX_P[0..3] 15 H_FDI_TXN[0..7] H_FDI_TXP[0..7] 15 15 RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75 AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 RSVD21 RSVD22 RSVD_NCTF_23 RSVD_NCTF_24 RSVD26 RSVD27 A34 A33 RSVD_NCTF_28 RSVD_NCTF_29 C35 B35 PEG_HTX_C_GRX_N[0..15] 22 PEG_HTX_C_GRX_P[0..15] 22 E15 F15 A2 D15 C15 AJ15 AH15 RSVD19 RSVD20 J29 J28 PEG_GTX_C_HRX_N[0..15] 22 PEG_GTX_C_HRX_P[0..15] 22 RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65 RSVD17 RSVD18 C1 A3 DMI_HTX_PRX_N[0..3] 15 DMI_HTX_PRX_P[0..3] 15 AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32 RSVD15 RSVD16 AC9 AB9 H_RSVD17_R H_RSVD18_R A20 B20 U9 T9 R497 0_0402_5% @ 1 2 @ 1 2 AT3 AR1 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58 D AP1 AT2 RSVD_NCTF_42 RSVD_NCTF_43 R58 3.01K_0402_1% RSVD_NCTF_40 RSVD_NCTF_41 RESERVED JCPU1A DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3 RSVD_NCTF_30 RSVD_NCTF_31 IC,AUB_CFD_rPGA,R1P0 CONN@ VSS C R146 0_0402_5% RSVD64_R 2 @ @ RSVD65_R 2 R147 0_0402_5% 1 1 B AP34 IC,AUB_CFD_rPGA,R1P0 CONN@ A eDP Signals Mapping eDP Singal PEG Singals PEG_HTX_C_GRX_P15 eDP_TX0 eDP_TX#0 PEG_HTX_C_GRX_N15 eDP_TX1 PEG_HTX_C_GRX_P14 eDP_TX#1 PEG_HTX_C_GRX_N14 eDP_TX2 PEG_HTX_C_GRX_P13 eDP_TX#2 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_P12 eDP_TX3 eDP_TX#3 PEG_HTX_C_GRX_N12 eDP_AUX PEG_GTX_C_HRX_P13 eDP_AUX# PEG_GTX_C_HRX_N13 eDP_HPD# PEG_GTX_C_HRX_P12 H_FDI_FSYNC0 H_FDI_FSYNC1 R519 1 DIS ONLY@ 2 R517 1 DIS ONLY@ 2 1K_0402_5% 1K_0402_5% H_FDI_INT R513 1 DIS ONLY@ 2 1K_0402_5% H_FDI_LSYNC0 H_FDI_LSYNC1 Lane Reversal PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_P3 R520 1 DIS ONLY@ 2 R515 1 DIS ONLY@ 2 CFG0 - PCI-Express Configuration Select CFG4 - Display Port Presence *1:Single PEG 0:Bifurcation enabled *1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port 1K_0402_5% 1K_0402_5% CheckList0.8 1.22 Auburndale Graphics Disable CFG3 - PCI-Express Static Lane Reversal *:Default *1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ... A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 SCHEMATICS,MB A5893 Document Number Rev C 401869 Wednesday, June 30, 2010 Sheet 1 4 of 56
5 4 3 2 1 JCPU1B AT23 COMP3 R507 2 1 20_0402_1% H_COMP2 AT24 COMP2 R521 2 1 49.9_0402_1% H_COMP1 G16 COMP1 R503 2 1 49.9_0402_1% H_COMP0 AT26 COMP0 SKTOCC#_R AH24 SKTOCC# T7 @ PAD D H_CATERR# H_PECI_R 2 AT15 CATERR# THERMAL THERMAL R547 1 0_0402_5% 18 H_PECI AK14 PECI BCLK BCLK# A16 B16 BCLK_ITP BCLK_ITP# E16 D16 DPLL_REF_SSCLK DPLL_REF_SSCLK# A18 A17 CLK_CPU_XDP CLK_CPU_XDP# AR30 AT30 PEG_CLK PEG_CLK# CLK_CPU_BCLK 18 CLK_CPU_BCLK# 18 SM_DRAMRST# CLK_CPU_DMI 14 CLK_CPU_DMI# 14 THERMTRIP# AP26 RESET_OBS# R123 1 0_0402_5% C 2 H_PM_SYNC_R AL15 PM_SYNC R122 1 0_0402_5% 15 H_PM_SYNC 2 H_CPUPWRGD_1 AN14 VCCPWRGOOD_1 R121 1 0_0402_5% 18 H_CPUPWRGD R150 1 0_0402_5% 15 PM_DRAM_PWRGD 2 R489 1 0_0402_5% VCCPWRGOOD_0 AK13 2 H_VTTPWRGD_R 0_0402_5% SM_DRAMPWROK VTTPWRGOOD AM26 TAPPWRGOOD PLT_RST#_R 2 AM15 H_PWRGD_XDP_R AL14 +1.05VS_VTT 2009/08/14 #425302 CP_S3PowerReduction WhitePaper_Rev1.0 SM_DRAMRST# 10 PM_EXT_TS#[0] PM_EXT_TS#[1] AN15 AP15 PM_EXTTS#0 PM_EXTTS#1_R AT28 AP27 XDP_PRDY# XDP_PREQ# TCK TMS TRST# AN28 AP28 AT27 XDP_TCLK XDP_TMS XDP_TRST# TDI TDO TDI_M TDO_M AT29 AR27 AR29 AP29 XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M DBR# AN25 XDP_DBR#_R BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23 RSTIN# 1 R567 2 100K_0402_5% R539 1 R538 1 R548 1 +1.05VS_VTT 2 10K_0402_5% 2 10K_0402_5% 2 0_0402_5% SM_RCOMP_0 R578 1 SM_RCOMP_1 R576 1 SM_RCOMP_2 R573 1 R89 R496 R495 R90 R62 R499 1 XDP_TDI_R XDP_TDO_M SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 XDP_PRDY# XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TCLK XDP_TRST# AL1 AM1 AN1 @ @ @ @ @ R488 1 R475 1 1 1 1 1 1 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 2 2 2 2 2 PM_EXTTS#0_1 10,11 2 51_0402_5% 2 100_0402_1% 2 24.9_0402_1% 2 130_0402_1% 2 0_0402_5% 2 0_0402_5% @ XDP_TDI XDP_TDO R87 1 R480 0_0402_5% 2 0_0402_5% XDP_DBRESET# XDP_DBRESET# 15,21 XDP_TDI_M XDP_TDO_R XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7 C @ 1 R481 1 R476 2 2 0_0402_5% 0_0402_5% JTAG MAPPING 2009/09/16 update 2009/2/4 #414044 DG Update Rev1.11 R125 750_0402_1% STUFF -> R488 ,R475 NO STUFF -> R480 , R481 , R476 STUFF -> R481,R476 NO STUFF -> R488, R475 , R480 2 IC,AUB_CFD_rPGA,R1P0 CONN@ STUFF -> R488 , R480 , R476 NO STUFF -> R475 , R481 CPU Only 2009/2/4 Delete dampling resistor for power noise and Layout space issue 1 2 Scan Chain (Default) GMCH Only R126 1 1.5K_0402_1% 17,21,32,36 PLT_RST# AN27 PM_DRAM_PWRGD_R H_VTTPWRGD 1 @ R540 H_PWRGD_XDP H_CPUPWRGD_0 2 PWR MANAGEMENT PWR MANAGEMENT H_CPURST# 2 0_0402_5% 2 0_0402_5% 1 AK15 DDR3 MISC H_THERMTRIP#_R 2 PROCHOT# R504 1 R510 1 D F6 SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] JTAG & BPM R124 1 0_0402_5% 18 H_THERMTRIP# AN26 CLK_CPU_DP_R CLK_CPU_DP#_R CLK_CPU_DP_R CLK_CPU_DP#_R PRDY# PREQ# H_PROCHOT# 53 H_PROCHOT# 2009/08/14 remove DP REF SSCLK 2 H_COMP3 CLOCKS 1 20_0402_1% MISC MISC R512 2 +1.05VS_VTT R127 R88 R91 2 2 2 @ 1 49.9_0402_1% 1 68_0402_5% 1 68_0402_5% H_CATERR# H_PROCHOT# H_CPURST# JP2 B 2009/8/14 change back to 2K B 1 A P U38 H_VTTPWRGD 2 5 +3VALW MC74VHC1G08DFT2G_SC70-5 4 H_VTTPWRGD_R XDP_OBS2 XDP_OBS3 1 G Y XDP_OBS0 XDP_OBS1 R550 2K_0402_1% 1 2 R542 3 51 H_VTTPWRGD XDP_PREQ# XDP_PRDY# 1K_0402_1% 2 XDP_OBS4 XDP_OBS5 #425302 CP_S3PowerReduction WhitePaper_Rev0.7 XDP_OBS6 XDP_OBS7 +3VALW P G 5 Need to check Voltage Level +1.5V_1 3 R152 @ 1.1K_0402_1% R151 H_VTTPWRGD 1 MC74VHC1G08DFT2G_SC70-5 R197 1K_0402_5% H_CPUPWRGD 1 2 H_PWRGOOD_R R84 1 2 PBTN_OUT#_XDP 15,21,36 PBTN_OUT# 0_0402_5% +1.05VS_VTT H_PWRGD_XDP 1 C211 @ 21 SMB_DATA_S3 0.1U_0402_16V4Z 21 SMB_CLK_S3 2 1.5K_0402_1% XDP_TCLK 2 2 A A Y 1 1 4 U11 B 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 XDP Connector GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 CONN@ B H_RESET#_R R83 1K_0402_5% 1 2 @ 1 2 H_CPURST# PLT_RST# R85 0_0402_5% CLK_CPU_XDP CLK_CPU_XDP# H_RESET#_R XDP_DBRESET# XDP_TDO XDP_TRST# XDP_TDI XDP_TMS +1.05VS_VTT 2 R81 1K_0402_5% 2 R79 51_0402_5% 1 1 +3VS +1.05VS_VTT A SAMTE_BSH-030-01-L-D-A 1 1 PM_DRAM_PWRGD_R 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 2 R149 2009/04/23 Intel CRB 1.55 Update Change R68 to 1.1K_1%, R71 to 3.01K_1% Compal Electronics, Inc. Compal Secret Data Security Classification 750_0402_1% 2 R148 @ 3.01K_0402_1% 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 SCHEMATICS,MB A5893 Document Number Rev C 401869 Wednesday, June 30, 2010 Sheet 1 5 of 56
4 C B 10 DDR_A_BS0 10 DDR_A_BS1 10 DDR_A_BS2 10 DDR_A_CAS# 10 DDR_A_RAS# 10 DDR_A_WE# A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AC3 AB2 U7 DDR_A_CAS# DDR_A_RAS# DDR_A_WE# AE1 AB3 AE9 SA_CK[0] SA_CK#[0] SA_CKE[0] SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_RAS# SA_WE# AA6 AA7 P7 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDR_A_CLK0 10 DDR_A_CLK0# 10 DDR_A_CKE0 10 SA_CK[1] SA_CK#[1] SA_CKE[1] Y6 Y5 P6 DDR_A_CLK1 10 DDR_A_CLK1# 10 DDR_A_CKE1 10 SA_CS#[0] SA_CS#[1] AE2 AE8 DDR_A_CS0# 10 DDR_A_CS1# 10 SA_ODT[0] SA_ODT[1] AD8 AF9 DDR_A_ODT0 10 DDR_A_ODT1 10 SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] DDR SYSTEM MEMORY A DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 2 B9 D7 H7 M7 AG6 AM7 AN10 AN13 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] C9 F8 J9 N9 AH7 AK9 AP11 AT13 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] C8 F9 H9 M9 AH8 AK10 AN11 AR13 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 11 DDR_B_CAS# 11 DDR_B_RAS# 11 DDR_B_WE# B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 SB_CK[0] SB_CK#[0] SB_CKE[0] DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AB1 W5 R7 AC5 Y7 AC6 V7 V6 M2 DDR_B_CLK1 11 DDR_B_CLK1# 11 DDR_B_CKE1 11 AB8 AD6 DDR_B_CS0# 11 DDR_B_CS1# 11 SB_ODT[0] SB_ODT[1] AC7 AD1 DDR_B_ODT0 11 DDR_B_ODT1 11 SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] D4 E1 H3 K1 AH1 AL2 AR4 AT8 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D5 F4 J4 L4 AH2 AL4 AR5 AR8 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C5 E3 H4 M5 AG2 AL5 AP5 AR7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] SB_CAS# SB_RAS# SB_WE# DDR_B_CLK0 11 DDR_B_CLK0# 11 DDR_B_CKE0 11 SB_CS#[0] SB_CS#[1] SB_BS[0] SB_BS[1] SB_BS[2] W8 W9 M3 SB_CK[1] SB_CK#[1] SB_CKE[1] SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] DDR_B_CAS# DDR_B_RAS# DDR_B_WE# 11 DDR_B_BS0 11 DDR_B_BS1 11 DDR_B_BS2 1 JCPU1D 11 DDR_B_D[0..63] 11 DDR_B_DM[0..7] 11 DDR_B_DQS#[0..7] 11 DDR_B_DQS[0..7] 11 DDR_B_MA[0..15] JCPU1C 10 DDR_A_D[0..63] 10 DDR_A_DM[0..7] 10 DDR_A_DQS#[0..7] 10 DDR_A_DQS[0..7] 10 DDR_A_MA[0..15] D 3 DDR SYSTEM MEMORY - B 5 U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 D C B IC,AUB_CFD_rPGA,R1P0 CONN@ IC,AUB_CFD_rPGA,R1P0 CONN@ A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 SCHEMATICS,MB A5893 Document Number Rev C 401869 Wednesday, June 30, 2010 Sheet 1 6 of 56
5 4 3 2 1 JCPU1F WW15 MOW +CPU_CORE Peak 21A 48A A 1.1V RAIL POWER VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15 10U_0805_6.3V6M +CPU_CORE 1 1 C258 2 1 C274 2 1 C286 2 C282 2 10U_0805_6.3V6M 1 C288 2 1 C284 2 10U_0805_6.3V6M 1 C281 10U_0805_6.3V6M 1 2 10U_0805_6.3V6M 10U_0805_6.3V6M 1 C676 2 10U_0805_6.3V6M C677 2 1 10U_0805_6.3V6M 1 C669 2 1 C674 2 10U_0805_6.3V6M 10U_0805_6.3V6M 1 C657 2 1 C652 2 10U_0805_6.3V6M 10U_0805_6.3V6M 1 C679 2 1 C262 2 10U_0805_6.3V6M C232 2 10U_0805_6.3V6M (Place these capacitors between inductor and socket on Bottom) +CPU_CORE 1 + 10U_0805_6.3V6M 1 C268 2 + C667 1 1 C242 10U_0805_6.3V6M 1 C223 1 C257 10U_0805_6.3V6M 1 C261 1 C269 1 C275 C155 2 2 330U_X_2VM_R6M 2 2 2 2 2 2 330U_X_2VM_R6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors under CPU socket, top layer) CSC (Current Sense Configuration) 8/25 +1.05VS_VTT R436 1 R451 1 @ 2 1K_0402_1% 2 1K_0402_1% CPU_VID1 R437 1 R452 1 @ 2 1K_0402_1% 2 1K_0402_1% CPU_VID2 R438 1 R453 1 @ CPU_VID3 R439 1 R454 1 @ 2 1K_0402_1% 2 1K_0402_1% CPU_VID4 R440 1 R455 1 @ 2 1K_0402_1% 2 1K_0402_1% 22U_0805_6.3V6M C278 1 C277 1 2 2 22U_0805_6.3V6M CPU_VID5 CPU_VID6 R441 1 R456 1 R442 1 R457 1 @ @ H_DPRSLPVR R443 1 R458 1 PSI# AN33 AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 @ R444 1 R459 1 22U_0805_6.3V6M 2 1K_0402_1% 2 1K_0402_1% C157 @ G15 H_VTTVID1 C276 2 1 22U_0805_6.3V6M C270 2 1 C256 2 1 22U_0805_6.3V6M C241 2 1 C231 2 22U_0805_6.3V6M 1 2 22U_0805_6.3V6M (Place these capacitors on CPU cavity, Bottom Layer) 2 1K_0402_1% 2 1K_0402_1% 2 1K_0402_1% 2 1K_0402_1% +CPU_CORE 2 1K_0402_1% 2 1K_0402_1% 22U_0805_6.3V6M 2 1K_0402_1% 2 1K_0402_1% C222 CPU_VID0 53 CPU_VID1 53 CPU_VID2 53 CPU_VID3 53 CPU_VID4 53 CPU_VID5 53 CPU_VID6 53 H_DPRSLPVR 53 VTT_SELECT 1 22U_0805_6.3V6M H_PSI# 53 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] PROC_DPRSLPVR @ H_PSI# C +CPU_CORE 1 C651 2 1 22U_0805_6.3V6M C658 2 1 C666 2 22U_0805_6.3V6M 1 22U_0805_6.3V6M C665 2 1 C668 2 22U_0805_6.3V6M 1 2 22U_0805_6.3V6M (Place these capacitors on CPU cavity, Bottom Layer) B T8 PAD VTT Rail H_VTTVID1 = low, 1.1V H_VTTVID1 = high, 1.05V Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V +CPU_CORE ISENSE VCC_SENSE VSS_SENSE VTT_SENSE VSS_SENSE_VTT AN35 AJ34 AJ35 B15 A15 4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF) IMVP_IMON 53 VCCSENSE_R R450 1 VSSSENSE_R R449 1 1 R435 VCCSENSE VSSSENSE 2 0_0402_5% 2 0_0402_5% VTT_SENSE 51 VSS_SENSE_VTT R523 1 2 100_0402_1% 1 R448 2 100_0402_1% +CPU_CORE VCCSENSE 53 VSSSENSE 53 1 + 1 + C541 2 330U_X_2VM_R6M 2 0_0402_5% 2 1 @ 330U_X_2VM_R6M + C136 2 1 + C251 2 330U_X_2VM_R6M 330U_X_2VM_R6M C134 2 330U_X_2VM_R6M TOP side (under inductor) +CPU-CORE Decoupling SPCAP,Polymer 2009/08/01 Issued Date C,uF ESR, mohm 4X470uF 3m ohm/12 16X10uF Stuffing Option 4m ohm/4 16X22uF 3m ohm/16 2X470uF A Compal Electronics, Inc. Compal Secret Data Security Classification IC,AUB_CFD_rPGA,R1P0 CONN@ 1 + C97 MLCC 0805 X5R 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 D +1.05VS_VTT CPU_VID0 POWER B +1.05VS_VTT 10U_0805_6.3V6M 10U_0805_6.3V6M AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 +1.05VS_VTT CPU VIDS C VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 SENSE LINES D CPU CORE SUPPLY AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 Continuous 18A 4 3 2 Sheet Wednesday, June 30, 2010 1 7 of 56
5 4 3 2 1 +VGFX_CORE JCPU1G 10U_0805_6.3V6M C802 0.1U_0402_16V4Z UMOP@ 2 1 UMOP@ 1 UMOP@ UMOP@ 2 2 C673 1 C672 1 UMOP@ UMOP@ 2 2 2 330U_X_2VM_R6M 22U_0805_6.3V6M 10U_0805_6.3V6M C J24 J23 H25 VTT1_45 VTT1_46 VTT1_47 15A GRAPHICS GRAPHICS 091211 EMI ADD 0.1U VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 3A 1 2 2 C260 FDI 22U_0805_6.3V6M 1 AR22 AT22 GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] AM22 AP22 AN22 AP23 AM23 AP24 AN24 GFX_VR_EN GFX_DPRSLPVR GFX_IMON AR25 AT25 AM24 VCC_AXG_SENSE 52 VSS_AXG_SENSE 52 D GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6 GFXVR_EN GFXVR_DPRSLPVR_R R92 R99 52 52 52 52 52 52 52 UMOP@ 2 330_0402_5% 1 R98 Reserved for +1.5V to +1.5V_1 1 2 DIS ONLY@ +1.5V_1 GFXVR_EN 52 GFXVR_DPRSLPVR 52 GFXVR_IMON 52 2 0_0402_5% 1 22U_0805_6.3V6M VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 1U_0402_6.3V4Z 2 1K_0402_5% 1U_0402_6.3V4Z 22U_0805_6.3V6M 2 C307 1 C308 2 1 C309 2 1 C306 2 1 C310 2 1 C303 2 1 2 C315 1 2 22U_0805_6.3V6M 1.1V 2 VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58 1 1 J2 2 2 2 1 1 1U_0402_6.3V4Z 1U_0402_6.3V4Z +1.5VS 1U_0402_6.3V4Z C 22U_0805_6.3V6M Short for +1.5VS to +1.5V_1 11/03 add four 0.1u 0402 Intel suggest for S3 reduse +1.5V_1 +1.5V 1 1 1 VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68 J22 J20 J18 H21 H20 H19 VCCPLL1 VCCPLL2 VCCPLL3 L26 L27 M26 1 2 0.1U_0402_16V4Z 1 C267 0.1U_0402_16V4Z C798 2 C799 2 0.1U_0402_16V4Z 1 P10 N10 L10 K10 C797 2 C800 2 0.1U_0402_16V4Z 10U_0805_6.3V6M C283 22U_0805_6.3V6M B +1.8VS 0.6A 1.8V 2 K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25 2 +1.05VS_VTT VTT0_59 VTT0_60 VTT0_61 VTT0_62 PEG & DMI 22U_0805_6.3V6M B C285 1 @ JUMP_43X118 2 1 1 @ JUMP_43X118 + C326 330U_D2_2V_Y +1.05VS_VTT 1 2 @ JUMP_43X118 1 +1.05VS_VTT C287 +1.5V J4 J3 +1.05VS_VTT C253 VAXG_SENSE VSSAXG_SENSE - 1.5V RAILS R514 0_0402_5% DIS ONLY@ C272 DDR3 D + 1 SENSE LINES 1 2 C250 GRAPHICS VIDs C675 1 AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16 POWER 22U_0805_6.3V6M 2.2U_0603_6.3V4Z +1.8VS_VCCSFR C230 1U_0402_6.3V4Z IC,AUB_CFD_rPGA,R1P0 CONN@ 1 2 1 2 C224 1 2 1U_0402_6.3V4Z C235 1 R97 0_0805_5% 1 2 40mil C234 2 1 C233 2 22U_0805_6.3V6M 4.7U_0805_10V4Z A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 8 of 56
5 4 3 2 D C B VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 JCPU1I VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30 K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9 IC,AUB_CFD_rPGA,R1P0 CONN@ VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 D C VSS NCTF JCPU1H AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35 1 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 AT35 AT1 AR34 B34 B2 B1 A35 H_NCTF1 H_NCTF2 @ @ PAD T14 PAD T19 H_NCTF6 H_NCTF7 @ @ PAD T18 PAD T15 B IC,AUB_CFD_rPGA,R1P0 CONN@ A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 9 of 56
5 4 3 2 1 +1.5V DIMMA VREFDQ M1 Circuit JDIMM1 6 DDR_A_DQS#[0..7] +DIMM_VREFDQA +1.5V 6 DDR_A_D[0..63] 1 6 DDR_A_DM[0..7] +DIMM_VREFDQA R222 1 1 DDR_A_D0 DDR_A_D1 C402 DDR_A_DM0 0.1U_0402_16V4Z 6 DDR_A_MA[0..15] 20mil 2 C401 6 DDR_A_DQS[0..7] 1K_0402_1% 2 2 2.2U_0603_6.3V4Z DDR_A_D2 DDR_A_D3 1 DDR_A_D8 DDR_A_D9 R227 D DDR_A_DQS#1 DDR_A_DQS1 2 1K_0402_1% DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DIMMA & DIMMB VREFCA circuit +1.5V 1 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 +DIMM_VREFCA R203 DDR_A_DM3 1K_0402_1% +1.5V R201 R254 0_0402_5% 1 @ 2 1K_0402_1% DDR_A_CKE0 2 6 DDR_A_CKE0 D S DIMM_DRAMRST# 1 Q17 BSS138LT1G_SOT23-3 3 5 SM_DRAMRST# G G C 2 18 RST_GATE DIMM_DRAMRST# 11 DDR_A_BS2 6 DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 C422 RST_GATE 1 DDR_A_MA8 DDR_A_MA5 2 DDR_A_MA3 DDR_A_MA1 0.047U_0402_16V7K DDR_A_CLK0 DDR_A_CLK0# 6 DDR_A_CLK0 6 DDR_A_CLK0# DDR_A_MA10 DDR_A_BS0 6 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# 6 DDR_A_WE# 6 DDR_A_CAS# DDR_A_MA13 DDR_A_CS1# 6 DDR_A_CS1# DDR_A_D32 DDR_A_D33 Layout Note: Place near JDIMM1 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 Layout Note: Place these 4 Caps near Command and Control signals of DIMMA DDR_A_D40 DDR_A_D41 B +1.5V DDR_A_DM5 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_A_D42 DDR_A_D43 1 10U_0805_6.3V6M C355 2 1 C356 2 10U_0805_6.3V6M 1 C405 2 1 C404 2 10U_0805_6.3V6M 1 C406 2 10U_0805_6.3V6M 1 1 2 2 C362 0.1U_0402_16V4Z 1 2 C363 1 C399 2 1 C400 2 C354 1 2 + C425 330U_2.5V_M_R15 @ DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 0.1U_0402_16V4Z DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59 Layout Note: Place near JDIMM1.203 & JDIMM1.204 R218 1 2 10K_0402_5% 1U_0402_6.3V4Z 1 2 C403 2.2U_0603_6.3V4Z 1U_0402_6.3V4Z 1 2 C398 1 +3VS +0.75VS 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDR_A_D4 DDR_A_D5 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 D DDR_A_DM1 DIMM_DRAMRST# DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 R274 2 1K_0402_1% DDR_A_D26 DDR_A_D27 1 #425302 CP_S3PowerReduction WhitePaper_Rev1.0 1 2 20mil +1.5V R217 0.1U_0402_16V4Z 10K_0402_5% 205 G2 G1 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_A_CKE1 206 DDR_A_CKE1 6 DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 C DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_CLK1 DDR_A_CLK1# DDR_A_CLK1 6 DDR_A_CLK1# 6 DDR_A_BS1 DDR_A_RAS# DDR_A_BS1 6 DDR_A_RAS# 6 DDR_A_CS0# DDR_A_ODT0 DDR_A_CS0# 6 DDR_A_ODT0 6 DDR_A_ODT1 +DIMM_VREFCA DDR_A_ODT1 6 20mil DDR_VREF_CA_DIMMA R202 1 2 0_0402_5% DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 C358 2.2U_0603_6.3V4Z DDR_A_D44 DDR_A_D45 1 1 2 2 C361 0.1U_0402_16V4Z B DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK PM_EXTTS#0_1 5,11 D_CK_SDATA 11,12 D_CK_SCLK 11,12 +0.75VS FOX_AS0A626-U8RN-7F A 2 A CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 1 C391 2 1 C388 2 1 C397 2 1 C396 1 2 2 DDR3 SO-DIMM A H=8mm C394 10U_0805_6.3V6M 2009/08/01 Issued Date 1U_0402_6.3V4Z Compal Electronics, Inc. Compal Secret Data Security Classification 1U_0402_6.3V4Z 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Sheet Wednesday, June 30, 2010 1 10 of 56
5 4 3 2 1 +1.5V +1.5V JDIMM2 2008/9/8 #400755 Calpella Clarksfield DDR3 SO-DIMM VREFDQ Platform Design Guide Change Details 6 DDR_B_DQS#[0..7] 6 DDR_B_D[0..63] 6 DDR_B_DM[0..7] 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 C433 2.2U_0603_6.3V4Z 6 DDR_B_DQS[0..7] 1 C431 2 DDR_B_D0 DDR_B_D1 1 DDR_B_DM0 2 DDR_B_D2 DDR_B_D3 6 DDR_B_MA[0..15] 0.1U_0402_16V4Z DDR_B_D8 DDR_B_D9 D DDR_B_DQS#1 DDR_B_DQS1 DIMMB VREFDQ M1 Circuit DDR_B_D10 DDR_B_D11 +1.5V 1 DDR_B_D16 DDR_B_D17 +DIMM_VREFDQB R282 DDR_B_DQS#2 DDR_B_DQS2 1K_0402_1% DDR_B_D18 DDR_B_D19 1 2 20mil DDR_B_D24 DDR_B_D25 R281 1K_0402_1% 2 DDR_B_DM3 DDR_B_D26 DDR_B_D27 DDR_B_CKE0 6 DDR_B_CKE0 DDR_B_BS2 6 DDR_B_BS2 C DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 DDR_B_CLK0 DDR_B_CLK0# 6 DDR_B_CLK0 6 DDR_B_CLK0# DDR_B_MA10 DDR_B_BS0 6 DDR_B_BS0 DDR_B_WE# DDR_B_CAS# 6 DDR_B_WE# 6 DDR_B_CAS# Layout Note: Place near JDIMM2 DDR_B_MA13 DDR_B_CS1# 6 DDR_B_CS1# Layout Note: Place these 4 Caps near Command and Control signals of DIMMB DDR_B_D32 DDR_B_D33 +1.5V 10U_0805_6.3V6M 0.1U_0402_16V4Z DDR_B_DQS#4 DDR_B_DQS4 0.1U_0402_16V4Z DDR_B_D34 DDR_B_D35 1 10U_0805_6.3V6M C436 10U_0805_6.3V6M 2 2 1 C420 2 1 C418 2 1 C416 2 1 C429 2 1 2 C430 1 C417 2 1 C419 2 1 2 + C395 330U_2.5V_M_R15 DDR_B_D40 DDR_B_D41 2 C437 1 C435 B 1 DDR_B_DM5 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z DDR_B_D42 DDR_B_D43 0.1U_0402_16V4Z DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 Layout Note: Place near JDIMM2.203 & JDIMM2.204 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 +0.75VS DDR_B_DM7 1U_0402_6.3V4Z DDR_B_D58 DDR_B_D59 C413 1 2 1U_0402_6.3V4Z C412 1 C427 2 1 2 C426 1 1 C411 R279 1 +3VS 2 2 10U_0805_6.3V6M R278 C432 1 1 1 C428 A 2.2U_0603_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 2 0.1U_0402_16V4Z 2 10K_0402_5% 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 G1 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 G2 DDR_B_D4 DDR_B_D5 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D6 DDR_B_D7 DDR_B_D12 DDR_B_D13 D DDR_B_DM1 DIMM_DRAMRST# 2009/08/01 DIMM_DRAMRST# 10 DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21 DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 DDR_B_CKE1 206 DDR_B_CKE1 6 DDR_B_MA15 DDR_B_MA14 C DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_CLK1 DDR_B_CLK1# DDR_B_BS1 DDR_B_RAS# DDR_B_CS0# DDR_B_ODT0 DDR_B_ODT1 20mil DDR_B_CLK1 6 DDR_B_CLK1# 6 DDR_B_BS1 6 DDR_B_RAS# 6 DDR_B_CS0# 6 DDR_B_ODT0 6 DDR_B_ODT1 6 DDR_VREF_CA_DIMMB R270 1 +DIMM_VREFCA 2 0_0402_5% DDR_B_D36 DDR_B_D37 DDR_B_DM4 DDR_B_D38 DDR_B_D39 C414 2.2U_0603_6.3V4Z DDR_B_D44 DDR_B_D45 1 1 2 2 C415 0.1U_0402_16V4Z B DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK PM_EXTTS#0_1 5,10 D_CK_SDATA 10,12 D_CK_SCLK 10,12 +0.75VS A DDR3 SO-DIMM B H=4mm FOX_AS0A626-U4RN-7F CONN@ Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 2 10K_0402_5% VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 205 +DIMM_VREFDQB 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Sheet Wednesday, June 30, 2010 1 11 of 56
A B C D E F G H SM010014520 3000ma 220ohm@100mhz DCR 0.04 +1.05VS_VTT 1 +CLK_3VS SM010014520 3000ma 220ohm@100mhz DCR 0.04 +CLK_1.05VS 40mil 40mil 0.1U_0402_16V4Z L76 2 1 FBMA-L11-201209-221LMA30T_0805 1 1 1 1 C774 C757 C770 C782 10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 L69 2 1 FBMA-L11-201209-221LMA30T_0805 +3VS 1 C737 1 1 2 C740 10U_0805_10V4Z 2 2 10U_0805_10V4Z 1 2 1 40mil 0.1U_0402_16V4Z C768 C781 10U_0805_10V4Z C741 2 L75 2 1 FBMA-L11-201209-221LMA30T_0805 +1.5VS 1 0.1U_0402_16V4Z L74 2 1 FBMA-L11-201209-221LMA30T_0805 +CLK_1.5VS @ SM010014520 3000ma 220ohm@100mhz DCR 0.04 C750 10U_0805_10V4Z 1 1 2 2 C742 1 1 C771 2 2 C769 0.1U_0402_16V4Z 0.1U_0402_16V4Z +CLK_3VS 2 2 +CLK_3VS Clock Generator +CLK_1.5VS U47 14 CLK_BUF_DREF_96M 14 CLK_BUF_DREF_96M# 22 27M_CLK 22 27M_SSC 14 CLK_BUF_PCIE_SATA 14 CLK_BUF_PCIE_SATA# 14 CLK_BUF_CPU_DMI 14 CLK_BUF_CPU_DMI# CLK_BUF_DREF_96M CLK_BUF_DREF_96M# R717 0_0402_5% @ 1 2 1 2 R716 0_0402_5% @ 27M_CLK_R 27M_SSC_R CLK_BUF_PCIE_SATA CLK_BUF_PCIE_SATA# CLK_BUF_CPU_DMI CLK_BUF_CPU_DMI# +CLK_1.05VS H_STP_CPU# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 SCL SDA REF_0/CPU_SEL VDD_REF XTAL_IN XTAL_OUT VSS_REF CKPWRGD/PD# 32 31 30 29 28 27 26 25 VDD_CPU CPU_0 CPU_0# VSS_CPU CPU_1 CPU_1# VDD_CPU_IO VDD_SRC VDD_USB_48 VSS_48M DOT_96 DOT_96# VDD_27 27MHZ 27MHZ_SS USB_48 24 23 22 21 20 19 18 17 VSS_27M SATA SATA# VSS_SRC SRC_1 SRC_1# VDD_SRC_IO CPU_STOP# D_CK_SCLK D_CK_SDATA REF_0/CPU_SEL R682 1 D_CK_SCLK 10,11 D_CK_SDATA 10,11 CLK_BUF_ICH_14M 14 2 33_0402_5% CLK_XTAL_IN CLK_XTAL_OUT CK505_PWRGD CLK_BUF_CPU_BCLK CLK_BUF_CPU_BCLK# CLK_BUF_CPU_BCLK 14 CLK_BUF_CPU_BCLK# 14 +CLK_1.05VS +CLK_1.5VS IDT SA00003HR00 TGND SLG8SP587VTR_QFN32_5X5 IDT: 9LRS3199AKLFT, SA000030P00 3 3 SILEGO: SLG8SP587V(WF), SA00002XY10 +3VS Low Power: +3VS R678 4.7K_0402_5% 1 2 1 1 3 2 S D_CK_SCLK Y4 14.31818MHZ 20PF 7A14300003 Q45 2N7002E-T1-GE3_SOT23-3 133MHz 100MHz 14,21,34 PCH_SMBCLK CLK_XTAL_IN +3VS 1 R677 4.7K_0402_5% 1 2 D CPU_1 133MHz VGATE 15,53 2 CLK_ENABLE# 53 G Q48 2N7002E-T1-GE3_SOT23-3 C755 1 27P_0402_50V8J C762 27P_0402_50V8J 2 1 100MHz Change to 5x3.2 2009/08/01 Deciphered Date 4 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date CLK_XTAL_OUT 2 0 (Default) CPU_0 R691 0_0402_5% @ 1 2 +3VS 2 10K_0402_5% REF_0/CPU_SEL PIN 30 4 S Q46 2N7002E-T1-GE3_SOT23-3 2 G R683 1 D_CK_SDATA 3 FOR Realtek CK505_PWRGD D +3VS S 14,21,34 PCH_SMBDATA 1 D IDT Have Internal Pull-Down 1 +3VS H_STP_CPU# 1 2 10K_0402_5% 2 G R690 1 R693 10K_0402_5% Realtek: RTM890N-631-VB-GRT, SA00003HQ10 Silego Have Internal Pull-Up 3 IDT 9LVS3199AKLFT NC 2 IDT: 9LVS3199AKLFT, SA00003HR00 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: A B C D E F Wednesday, June 30, 2010 G Sheet 12 of H 56
5 4 3 2 1 +RTCBATT PCH_RTCRST# PCH_RTCX1 OSC 4 NC OSC 1 R615 2 32.768KHZ_12.5PF_Q13MC14610002 C722 2 1 D U41A 10M_0402_5% +RTCBATT_R REV1.0 FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 D33 B33 C32 A32 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 FWH4 / LFRAME# B13 D13 PCH_RTCX2 C34 LPC_FRAME# LDRQ0# LDRQ1# / GPIO23 A34 F34 SERIRQ AB9 SERIRQ SATA0RXN SATA0RXP SATA0TXN SATA0TXP AK7 AK6 AK11 AK9 SATA_DTX_C_PRX_N0 SATA_DTX_C_PRX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 SATA_DTX_C_PRX_N0 31 SATA_DTX_C_PRX_P0 31 SATA_PTX_DRX_N0 31 SATA_PTX_DRX_P0 31 SATA1RXN SATA1RXP SATA1TXN SATA1TXP AH6 AH5 AH9 AH8 SATA_DTX_C_PRX_N1 SATA_DTX_C_PRX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 SATA_DTX_C_PRX_N1 31 SATA_DTX_C_PRX_P1 31 SATA_PTX_DRX_N1 31 SATA_PTX_DRX_P1 31 SATA2RXN SATA2RXP SATA2TXN SATA2TXP AF11 AF9 AF7 AF6 SATA3RXN SATA3RXP SATA3TXN SATA3TXP AH3 AH1 AF3 AF1 SATA4RXN SATA4RXP SATA4TXN SATA4TXP AD9 AD8 AD6 AD5 SATA5RXN SATA5RXP SATA5TXN SATA5TXP AD3 AD1 AB3 AB1 RTCX1 RTCX2 18P_0402_50V8J close to RAM door modify to 330K 1 2 R675 @ 10K_0603_5% C365 1U_0603_10V6K 1 2 RTCRST# PCH_SRTCRST# +RTCVCC RC Delay 18~25mS C14 D17 SRTCRST# R213 1 2 1M_0402_5% SM_INTRUDER# A16 INTRUDER# R212 1 2 330K_0402_1% PCH_INTVRMEN A14 INTVRMEN HDA_BITCLK_PCH A30 HDA_BCLK HDA_SYNC_PCH D29 HDA_SYNC R327 1 2 33_0402_5% 2 33_0402_5% 39 PCH_SPKR (SPKR Have internal Pull-Down) 39 HDA_RST_AUDIO# 1 R328 PCH_SPKR 1 HDA_RST_PCH# 2 33_0402_5% P1 SPKR C30 HDA_RST# G30 39 HDA_SDIN0 HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 F32 HDA_SDIN3 HDA_SDOUT_PCH B29 HDA_SDO PCH_GPIO33# H32 HDA_DOCK_EN# / GPIO33 J30 HDA_DOCK_RST# / GPIO13 M3 JTAG_TCK K3 JTAG_TMS 21 PCH_JTAG_TDI K1 JTAG_TDI 21 PCH_JTAG_TDO J2 JTAG_TDO J4 TRST# HDA_SDO ,This signal has a weak internal pull-down resistor. Should not be Pull High C IHDA F30 E32 PCH_SPKR Have internal PD SERIRQ 39 HDA_SDOUT_AUDIO R324 If GPIO33 pull down, ME will not working. For factory update ME, pull down resistor pull under door. 1 2 33_0402_5% GPIO33 can not pull down (manufacturing environments) 1 PCH_GPIO33# D 2 G PCH_JTAG_TCK 21 PCH_JTAG_TCK Q39 21 PCH_JTAG_TMS S 2N7002E-T1-GE3_SOT23-3 3 1 36 ME_OVERRIDE 2 21 PCH_JTAG_RST# GPIO33 has a weak internal pull-up NOTE: Asserting the GPIO33 low on the rising edge of PWROK will also halt Intel Management Engine after chipset bringup and disable runtime Intel Management Engine features. This is a debug mode and must not be asserted after manfacturing/ debug. +1.05VS_PCH PCH_SPI_CLK_1 R665 1 2 0_0402_5% PCH_SPI_CLK PCH_SPI_CS0# 2 15_0402_5% PCH_SPI_CS0#_R AV3 2009/08/23 Debug Port DG1.7 P27.28 R662 1 T24 PAD PCH_SPI_MOSI_1 R664 1 TDO,TDI,TMS Pull Up for Production Units PCH_SPI_MISO_1 R661 1 unpop TDO,TDI,TMS resister PCH_SPI_CS1# @ BA2 1 SERIRQ 36 AY3 SATAICOMPI AF15 R205 1 PCH_SPI_MOSI AY1 SATA_COMP 2 10K_0402_5% +3VS SATALED# SPI_MOSI 2 33_0402_5% PCH_SPI_MISO AV1 @ 1 R644 1 R724 1 R722 PCH_JTAG_TDO 51_0402_5% 2 200_0402_5% 2 100_0402_5% 2 @ 1 R645 1 R728 1 R727 T3 PCH_SATALED# 37 SATA0GP / GPIO21 Y9 GPIO21 Project ID2 SPI_MISO SATA1GP / GPIO19 V1 PCH_JTAG_TDI 51_0402_5% 2 20K_0402_5% 2 10K_0402_5% 2 @ 1 R643 1 R721 1 R723 PCH_JTAG_RST# PCH_GPIO21 21 PCH_GPIO19 21 +3VS B 2 10K_0402_5% R259 NonSG@ 10K_0402_5% R268 @ 10K_0402_5% +3VS U18 +3VS R301 1 R271 1 2 3.3K_0402_5% 2 3.3K_0402_5% PCH_SPI_CS0# SPI_WP1# SPI_HOLD1# 1 3 7 4 CS# WP# HOLD# GND VCC SCLK SI SO 8 6 5 2 PCH_SPI_CLK_1 PCH_SPI_MOSI_1 PCH_SPI_MISO_1 PCH_SPI_CLK_1 @ 2 10P_0402_50V8J GPIO19 OPT PCH_JTAG_TCK 1 C729 dGPU iGPU SG GPIO37 PCH_GPIO19 MX25L3205DM2I-12G SOP 8P SA000021A00 SPI ROM Footprint 200mil R647 +3VS R267 1 R260 1 SGOPT@ 10K_0402_5% 2 TDO: Reserved on ES1 Sample Mount R724, R722 on ES2 Sample MP mount R646, R644, R645, R643 and remove others SATA for ODD 2 37.4_0402_1% PCH_SATALED# R652 1 SPI_CS1# 2 15_0402_5% SATA for HDD1 AF16 2 PCH_JTAG_TMS 51_0402_5% 2 200_0402_5% 2 100_0402_5% 2 1 20mil 0.1U_0402_16V4Z +1.05VS_PCH SATAICOMPO IBEXPEAK-M_FCBGA107 1 R646 1 R726 1 R725 2 2 +CHGRTC C724 2/10 SATA2, SATA3 not support on HM55 2008 Intel MOW36/MOW50 @ 4.7K_0402_5% VGA_PRSNT_L# 0 0 1 0 1 0 A S3 CRB 1.1 Change to 4.7K @ 1 R663 PCH_SPI_MOSI Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MOSI This signal has a weak internal pull-down resistor. This signal must be sampled low. 5 2009/08/01 Issued Date enable iTPM: SPI_MOSI High Compal Electronics, Inc. Compal Secret Data Security Classification 1K_0402_5% 2 D C SPI_CS0# +3V 51_0402_5% 2 200_0402_5% 2 100_0402_5% 2 A 20mil LPC_FRAME# 36 SPI_CLK SPI B D8 BAS40-04_SOT23-3 +RTCVCC 1 R580 100K_0402_5% JTAG 1 2 R237 10K_0402_5% 36 36 36 36 1 R330 SATA 39 HDA_BITCLK_AUDIO HDA_SYNC On Die PLL VR is supplied by 1.5V when sampled High, 1.8V when sampled Low. R650 1K_0402_5% @ 1 2 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 INTVRMEN - Integrated SUS 1.05V VRM Enable High - Enable Internal VRs HDA for AUDIO (HDA_SYNC Have internal Pull-Down) 39 HDA_SYNC_AUDIO +3VS LPC PCH_RTCRST# RTC +RTCVCC PCH_SRTCRST# 1 2 R214 20K_0402_1% 1 NC 2 1 1 3 2 1 2 R671 @ 10K_0603_5% C366 1U_0603_10V6K 1 2 R336 1K_0402_5% 20mil X2 3 close to RAM door 2 C723 18P_0402_50V8J 2 1 RC Delay 18~25mS 2 1 2 R215 20K_0402_1% +RTCVCC Rev C 401869 Date: 4 3 2 Wednesday, June 30, 2010 Sheet 1 13 of 56
4 3 REV1.0 PERN7 PERP7 PETN7 PETP7 2 0_0402_5% R266 1 PCH_GPIO73 2 0_0402_5% P9 AM43 AM45 34 CLK_PCIE_MINI1# 34 CLK_PCIE_MINI1 For Wireless LAN 34 MINI1_CLKREQ# 21 PCH_GPIO18 PCH_GPIO18 U4 AM47 AM48 PCH_GPIO20 21 PCH_GPIO20 N4 AH42 AH41 PCH_GPIO25 2009/08/25: Change back to +3V remove mini2 +3V 2009/08/25: remove mini2 clk 1 B A8 R241 MINI2_CLKREQ#_1 AM51 AM53 M9 SMBus C6 G8 D M14 PCH_GPIO74 SML1CLK / GPIO58 E10 PCH_SML1CLK SML1DATA / GPIO75 G12 PCH_SML1DAT DGPU_PWR_EN +3V 1 T13 T11 CL_RST1# T9 H1 10K_0402_5% PEG_CLKREQ#_R 1 1 AD43 AD45 CLKOUT_DMI_N CLKOUT_DMI_P CLK_CPU_DMI# 5 CLK_CPU_DMI 5 CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P CLKOUT_PCIE0N CLKOUT_PCIE0P PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P PCIECLKRQ1# / GPIO18 CLKOUT_PCIE2N CLKOUT_PCIE2P 2N7002E-T1-GE3_SOT23-3 AW24 BA24 CLKIN_BCLK_N CLKIN_BCLK_P AP3 AP1 CLK_BUF_CPU_BCLK# 12 CLK_BUF_CPU_BCLK 12 CLKIN_DOT_96N CLKIN_DOT_96P F18 E18 CLK_BUF_DREF_96M# 12 CLK_BUF_DREF_96M 12 AH13 AH12 CLK_BUF_PCIE_SATA# 12 CLK_BUF_PCIE_SATA 12 REFCLK14IN CLKIN_PCILOOPBACK J42 1 R163 XTAL25_IN XTAL25_OUT PCIECLKRQ4# / GPIO26 AF38 2 10_0402_5% 1 C319 10K_0402_5% 2 10K_0402_5% 2 H6 1 R265 MINI1_CLKREQ# PCH_GPIO20 1 R649 AK53 AK51 PCH_GPIO56 Schematic_Checklist_Rev1.6 GPIO18 GPIO25 Main (core) power well (+V3.3S) Muxed with PCIECLKRQ1#. If not used, requires 8.2-k to 10-k pull-up to +Vcc_3.3 (+V3.3S) Resume (Sus) well (+V3.3A) P13 PCIECLKRQ5# / GPIO44 CLKOUT_PEG_B_N CLKOUT_PEG_B_P PEG_B_CLKRQ# / GPIO56 XCLK_RCOMP R170 1 2 90.9_0402_1% CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 T42 CLKOUTFLEX3 / GPIO67 1 R623 1 R602 1 R626 10K_0402_5% 2 1 R208 1 R639 1 R249 PCH_SML1CLK PCH_SML1DAT 10K_0402_5% 2 1 R207 PCH_GPIO74 2.2K_0402_5% 2.2K_0402_5% 1 R624 5 PCH_GPIO25 *Discrete *Optimus 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 1 R244 1 R206 1 R257 4 PCH_GPIO44 PCH_GPIO56 PCH_GPIO73 2 C694 27P_0402_50V8J UMOP@ +3VS 0 GPIO66 ID0 0 PCH_SML1CLK 2009/08/01 6 Structure 1 NEW70 1 +3VS NEW80 1 0 NEW90 1 0 0 NEW71/91 1 1 0 Deciphered Date EC_SMB_CK2 EC_SMB_CK2 22,36 Q19A 2N7002DWH_SOT363-6 PCH_SML1DAT Pull high +3VS at KB926 side 3 4 EC_SMB_DA2 EC_SMB_DA2 22,36 Q19B 2N7002DWH_SOT363-6 NEW71/91 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 2009/08/13: Change back to +3V Change to 5x3.2 1 PCH_GPIO60 2 2 GPIO65 ID1 0 0 EC_LID_OUT# PCH_SMBCLK PCH_SMBDATA B Y2 25MHZ_20PF_7A25000012 UMOP@ 2 10K_0402_5% R144 1 2 10K_0402_5% NonOPT@ R157 1 2 10K_0402_5% @ R167 1 2 10K_0402_5% PROJECT_ID0 Project Structure GPIO21 ID2 0 10K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 10K_0402_5% 2 OPT@ +3VS R564 1M_0402_5% UMOP@ IBEXPEAK-M_FCBGA107 0 9/1: Change to +3VS R156 1 +1.05VS_PCH N50 +3V +3V Project Structure ID T45 P43 PROJECT_ID1 Muxed with PCIECLKREQ3# If not used, requires 8.2-k to 10-k pull-up to +V3.3A rail. A C693 UMOP@ 27P_0402_50V8J 1 2 XTAL25_IN XTAL25_OUT 2 PCH_GPIO44 CLKOUTFLEX0 / GPIO64 1109 RF request 5 +3VS CLKOUT_PCIE5N CLKOUT_PCIE5P R563 DIS ONLY@ 0_0402_5% 1 2 12 2 10P_0402_50V8J CLK_PCI_FB 17 AH51 AH53 XCLK_RCOMP CLKOUT_PCIE4N CLKOUT_PCIE4P 6/9 MOW23 Request add 25MHz crystal supporting Integrated Graphics CLK_BUF_ICH_14M P41 CLKOUT_PCIE3N CLKOUT_PCIE3P PCIECLKRQ3# / GPIO25 C CLK_BUF_CPU_DMI# 12 CLK_BUF_CPU_DMI 12 CLKIN_DMI_N CLKIN_DMI_P Clock Flex 2 AJ50 AJ52 PEG_CLKREQ# 22 R276 @ 2.2K_0402_5% AT1 AT3 CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P PCIECLKRQ2# / GPIO20 3 Q18 R247 DIS@ @ 2.2K_0402_5% CLK_PEG_VGA# 22 CLK_PEG_VGA 22 AN4 AN2 CLKOUT_PEG_A_N CLKOUT_PEG_A_P 10K_0402_5% MINI2_CLKREQ#_1 R275 DIS@ 10K_0402_5% R636 2 G Link Controller CL_CLK1 CL_DATA1 PEG_A_CLKRQ# / GPIO47 PERN8 PERP8 PETN8 PETP8 18,21,38,42 1 SML1ALERT# / GPIO74 1 R258 1 SML0CLK 2 32 LAN_CLKREQ# PCH_GPIO60 1 AK48 AK47 32 CLK_PCIE_LAN# 32 CLK_PCIE_LAN For PCIE LAN PCH_SMBDATA 12,21,34 J14 2 C PCH_SMBDATA SML0DATA PEG BG34 BJ34 BG36 BJ36 PCH_SMBCLK 12,21,34 C8 EC_LID_OUT# 36 2 AT34 AU34 AU36 AV36 2/10 PCIE7, PCIE8 not support on HM55 SML0ALERT# / GPIO60 PCH_SMBCLK 1 PERN6 PERP6 PETN6 PETP6 SMBDATA H14 1. Connect Directly EXPRESS CARD, MINI1, MINI2 2. Level Shift1, Pull-Up to +3VS CLOCK GEN, DIMM1, DIMM2 3. Level Shift2, Pull-Up to +3VS LAN 4. Level Shift3, Pull-Up to +3VS CPU & PCH XDP 2 PERN5 PERP5 PETN5 PETP5 2009/08/25: remove PCIE5 For Mini2 SMBCLK EC_LID_OUT# S PERN4 PERP4 PETN4 PETP4 SMBALERT# / GPIO11 B9 D PERN3 PERP3 PETN3 PETP3 D PERN1 PERP1 PETN1 PETP1 PCI-E* C332 2 C334 2 PERN2 PERP2 PETN2 PETP2 BF33 BH33 BG32 BJ32 2 2 From CLK BUFFER PCIE_DTX_C_PRX_N2 PCIE_DTX_C_PRX_P2 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 1 1 BA34 AW34 BC34 BD34 34 34 34 34 C335 C339 PCIE_DTX_C_PRX_N2 AW30 PCIE_DTX_C_PRX_P2 BA30 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BC30 0.1U_0402_16V7K PCIE_PTX_DRX_P2 BD30 BA32 BB32 BD32 BE32 For Wireless LAN PCIE_DTX_C_PRX_N1 PCIE_DTX_C_PRX_P1 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 1 1 AU30 AT30 AU32 AV32 32 32 32 32 For PCIE LAN 1 2 U41B PCIE_DTX_C_PRX_N1 PCIE_DTX_C_PRX_P1 0.1U_0402_16V7K PCIE_PTX_DRX_N1 0.1U_0402_16V7K PCIE_PTX_DRX_P1 BG30 BJ30 BF29 BH29 2 2 5 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 3 2 Wednesday, June 30, 2010 Sheet 1 14 of 56 A
5 4 3 DMI_HTX_PRX_P[0..3] 4 DMI_HTX_PRX_P[0..3] DMI_PTX_HRX_N[0..3] 4 DMI_PTX_HRX_N[0..3] DMI_PTX_HRX_P[0..3] 4 DMI_PTX_HRX_P[0..3] H_FDI_TXN[0..7] U41C H_FDI_TXP[0..7] DMI_HTX_PRX_N0 BC24 DMI_HTX_PRX_N1 BJ22 DMI_HTX_PRX_N2 AW20 DMI_HTX_PRX_N3 BJ20 DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3 BD22 BH21 BC20 BD18 DMI0TXP DMI1TXP DMI2TXP DMI3TXP @ 4 BJ12 H_FDI_LSYNC0 4 BG14 H_FDI_LSYNC1 4 DMI_IRCOMP T6 SYS_RESET# WAKE# SYS_PWROK_R 1 0_0402_5% 1 0_0402_5% M6 SYS_PWROK B17 K5 LAN_RST# A10 D9 5 PM_DRAM_PWRGD PCH_RSMRST# 36 SUS_PWR_DN_ACK H_FDI_FSYNC1 XDP_DBRESET# SYS_PWROK B BH13 C16 SUS_PWR_DN_ACK M1 PWROK MEPWROK LAN_RST# DRAMPWROK RSMRST# 36 EC_SWI# Y1 PM_CLKRUN# SUS_STAT# / GPIO61 P8 PCH_GPIO61 SUSCLK PCH_ACIN P7 4 C 32,34 PM_CLKRUN# 36 @ PAD T10 SUSCLK / GPIO62 SLP_S5# / GPIO63 E4 PM_SLP_S5# 36 SLP_S4# H7 PM_SLP_S4# 36 SLP_S3# P12 SLP_M# K8 PM_SLP_M# @ PAD T11 TP23 N2 PM_SLP_DSW# @ PAD T22 ACPRESENT / GPIO31 A6 BATLOW# / GPIO72 SUSCLK 36 PM_SLP_S3# 36 B @ 1 0_0402_5% R605 2 Q41 MMBT3906_SOT23-3 PCH_RSMRST# 1 3 EC_RSMRST# 36 E PWRBTN# PCH_PCIE_WAKE# F3 SUS_PWR_DN_ACK / GPIO30 P5 PCH_GPIO72 5,21,36 PBTN_OUT# 2 10K_0402_5% 2 D6 CH751H-40PT_SOD323-2 PCH_PCIE_WAKE# CLKRUN# / GPIO32 PBTN_OUT# 1 R240 1 J12 4 EC_SWI# F14 PMSYNCH RI# SLP_LAN# / GPIO29 BJ10 F6 H_PM_SYNC 5 2 B R620 2 R631 2 H_FDI_FSYNC0 FDI_FSYNC1 DMI_ZCOMP H_FDI_INT C BF25 BJ14 BF13 FDI_LSYNC1 BH25 DMI_COMP FDI_INT 09/09/14 WW37 PCH WAKE# PU 10K SYS_PWROK VGATE 36 EC_ACIN H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7 FDI_FSYNC0 FDI R600 49.9_0402_1% 1 2 5,21 XDP_DBRESET# +3V BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12 R604 10K_0402_5% PM_SLP_LAN# 1 R598 IBEXPEAK-M_FCBGA107 2 4.7K_0402_5% +3V D20A 2 C DMI0TXN DMI1TXN DMI2TXN DMI3TXN D H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7 FDI_LSYNC0 +1.05VS_PCH SUS_PWR_DN_ACK 2 10K_0402_5% PCH_GPIO72 2 8.2K_0402_5% EC_SWI# 2 10K_0402_5% PCH_PCIE_WAKE# 2 10K_0402_5% PM_SLP_LAN# 2 10K_0402_5% BE22 BF21 BD20 BE18 BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2 DMI_PTX_HRX_P3 +3V BD24 BG22 BA20 BG20 DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3 PM_CLKRUN# 2 8.2K_0402_5% FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 1 +3VS REV1.0 DMI0RXN DMI1RXN DMI2RXN DMI3RXN DMI 4 H_FDI_TXP[0..7] System Power Management 4 H_FDI_TXN[0..7] D 1 R648 1 R628 1 R198 1 R641 1 @ R248 1 DMI_HTX_PRX_N[0..3] 4 DMI_HTX_PRX_N[0..3] 1 R657 2 1 6 2 BAV99DW-7_SOT363 D20B 4 A Y 1 VGATE 4 3 EC_PWROK 36,38 5 VGATE 12,53 R591 2.2K_0402_5% BAV99DW-7_SOT363 MC74VHC1G08DFT2G_SC70-5 2 3 21 SYS_PWROK EC_PWROK 1 U44 2 P SYS_PWROK B G 5 +3VS A SYS_PWROK 1 R606 2 10K_0402_5% EC_PWROK 1 R632 2 10K_0402_5% LAN_RST# 1 R617 2 10K_0402_5% Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. No used Integrated LAN, connecting LAN_RST# to GND Rev C 401869 Date: 5 A 4 3 2 Wednesday, June 30, 2010 Sheet 1 15 of 56
5 4 3 2 1 U41D IGPU_BKLT_EN T48 T47 28 DPST_PWM L_BKLTCTL PCH_LCD_CLK PCH_LCD_DATA AB48 Y45 AB46 V48 SDVO_STALLN SDVO_STALLP SDVO_INTN SDVO_INTP AP39 AP41 LVD_VREF AT43 AT42 LVD_VREFH LVD_VREFL SDVO_CTRLCLK SDVO_CTRLDATA R131 1 @ 2 2.2K_0402_5% PCH_LCD_DATA 2 10K_0402_5% LCTLA_CLK R132 1 R133 1 2 10K_0402_5% 2 2.2K_0402_5% LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 PCH_TXOUT0+ PCH_TXOUT1+ PCH_TXOUT2+ BB48 BA50 AY49 AV48 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 AA52 AB53 AD53 CRT_BLUE CRT_GREEN CRT_RED PCH_CRT_CLK 2 2.2K_0402_5% BB47 BA52 AY48 AV47 LCTLB_DATA R546 1 R545 1 C 28 PCH_TXOUT0+ 28 PCH_TXOUT1+ 28 PCH_TXOUT2+ PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2- PCH_CRT_DATA R551 R552 R553 1 1 1 UMOP@ UMOP@ UMOP@ PCH_CRT_B 150_0402_1% PCH_CRT_G 150_0402_1% PCH_CRT_R 150_0402_1% 2 2 2 29 PCH_CRT_B 29 PCH_CRT_G 29 PCH_CRT_R 29 PCH_CRT_CLK 29 PCH_CRT_DATA PCH_CRT_B PCH_CRT_G PCH_CRT_R PCH_CRT_CLK PCH_CRT_DATA B ENBKL R135 1 UMOP@ 2 0_0402_5% V51 V53 1 UMA ONLY & OPTIMUS USE DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38 PCH_DPB_N0 PCH_DPB_P0 PCH_DPB_N1 PCH_DPB_P1 PCH_DPB_N2 PCH_DPB_P2 PCH_DPB_N3 PCH_DPB_P3 DDPC_CTRLCLK DDPC_CTRLDATA Y49 AB49 DDPC_AUXN DDPC_AUXP DDPC_HPD BE44 BD44 AV40 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P 2 100K_0402_5% BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36 PCH_DPB_HPD C313 C305 C320 C323 C317 C314 C327 C325 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 UMOP@ UMOP@ UMOP@ UMOP@ UMOP@ UMOP@ UMOP@ UMOP@ 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 30 PCH_TMDS_D2# 30 PCH_TMDS_D2 30 PCH_TMDS_D1# 30 PCH_TMDS_D1 30 PCH_TMDS_D0# 30 PCH_TMDS_D0 30 PCH_TMDS_CK# 30 PCH_TMDS_CK 30 HDMI D2 HDMI D1 HDMI D0 HDMI CLK C U50 U52 DDPD_AUXN DDPD_AUXP DDPD_HPD REV1.0 BC46 BD46 AT38 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36 B 1 R143 1K_0402_0.5% 2 2 R103 1 DIS ONLY@ 2 R171 1 IBEXPEAK-M_FCBGA107 R134 100K_0402_5% ENBKL DAC_IREF CRT_IRTN SDVO_SCLK 30 SDVO_SDATA 30 PCH_DPB_HPD CRT_HSYNC CRT_VSYNC CRT_IREF AD48 AB51 IGPU_BKLT_EN T51 T53 BG44 BJ44 AU38 CRT_DDC_CLK CRT_DDC_DATA Y53 Y51 29 PCH_CRT_HSYNC 29 PCH_CRT_VSYNC D DDPB_AUXN DDPB_AUXP DDPB_HPD DDPD_CTRLCLK DDPD_CTRLDATA CRT PCH_LCD_CLK LVDSA_CLK# LVDSA_CLK AY51 AT48 AU50 AT51 2 2.2K_0402_5% AV53 AV51 AY53 AT49 AU52 AT53 @ 28 PCH_TXOUT028 PCH_TXOUT128 PCH_TXOUT2- PCH_TXCLKPCH_TXCLK+ AP48 AP47 28 PCH_TXCLK28 PCH_TXCLK+ R130 1 BF45 BH45 SDVO_CTRLDATA strap Pull High at Level Shift Page LVD_IBG LVD_VBG Digital Display Interface LVDS_IBG R162 1 UMOP@ 2 0_0402_5% 11/21 intel JIM suggest Pull high at LVDS Conn BJ48 BG48 L_CTRL_CLK L_CTRL_DATA R166 1 UMOP@ 2 2.37K_0402_1% +3VS BJ46 BG46 L_DDC_CLK L_DDC_DATA LCTLA_CLK LCTLB_DATA 28 PCH_LCD_CLK 28 PCH_LCD_DATA SDVO_TVCLKINN SDVO_TVCLKINP LVDS D L_BKLTEN L_VDD_EN Y48 28 PCH_ENVDD 2/3 Change to 1K_0402_0.5% from Intel Suggestion. (EDS 1.0 is incorrect) 0_0402_5% VGA_BKL_EN DIS ONLY USE +5VS U25 22 VGA_BKL_EN IGPU_BKLT_EN A 17,28,29 DGPU_SELECT# 28 IGPU_SELECT# 2 5 1 7 1A 2A 1OE# 2OE# VCC 1B 2B GND 8 3 6 4 C472 SG@ 0.1U_0402_16V4Z 1 2 ENBKL A ENBKL 36 SN74CBTD3306CPWR_TSSOP8 SG@ Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 16 of 56
R577 R574 R572 R153 R568 R570 R565 R566 C 1 1 1 1 2 2 2 2 1 1 1 1 2 2 2 2 1 1 1 1 2 2 2 2 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 16,28,29 DGPU_SELECT# 28 DGPU_PWMSEL# PCI_GNT2# ESI Strap (Server Only) this signal should not be pulled low GNT0# GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# T12 PAD @ TP_PCI_RST# K6 PCIRST# E44 E50 SERR# PERR# A42 H44 F46 C46 IRDY# PAR DEVSEL# FRAME# PCI_PLOCK# D49 PCI_STOP# PCI_TRDY# D41 C48 STOP# TRDY# M7 R561 R142 1 1 2 22_0402_5% 2 22_0402_5% CLK_PCI_LPC_R CLK_PCI_FB_R B 1 A Y MC74VHC1G08DFT2G_SC70-5 DIS@ NV_RCOMP R660 1 @ +1.8VS NV_ALE R233 1 @ 2 1K_0402_5% If not implemented, the dual channel NAND interface signals, including NV_RCOMP, can be left as No Connect. NV_CLE R225 1 @ 2 1K_0402_5% Intel Anti-Theft Techonlogy USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 B25 USB_BIAS D25 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 N16 J16 F16 L16 E14 G16 F12 T15 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 35 35 35 35 35 35 NV_ALE USB/B (Right Side) USB Port (Left Side) NV_CLE 0 LPC 0 1 Reserved (NAND) 1 0 PCI 1 1 SPI Set to Vcc when HIGH Set to Vss when LOW Disable Intel Anti-Theft Technology：floating(internal PD) CMOS Camera (LVDS) Card Reader NV_CLE Mini Card(SIM Card) DMI termination voltage. weak internal PU, don't PD EHCI 2 Bluetooth Mini Card(WLAN) Mini Card(WWAN) B D5 1 2 R191 22.6_0402_1% USB_OC#0_R USB_OC#0_R 21 USB_OC#2_R PLTRST# N52 P53 P46 P51 P48 CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 USB_OC#0_R USB_OC#1_R USB_OC#2_R USB_OC#3_R USB_OC#4_R USB_OC#5_R USB_OC#6_R USB_OC#7_R R216 1 2 0_0402_5% R210 1 2 0_0402_5% USB_OC#2_R 21 (For USB Port0, 2) USB_OC#0 35 USB_OC#1_R 21 USB_OC#2 35 USB_OC#3_R 21 USB_OC#4_R 21 USB_OC#5_R 21 USB_OC#6_R 21 USB_OC#7_R 21 (For USB Port1) RP1 USB_OC#3_R USB_OC#5_R USB_OC#6_R USB_OC#7_R 1 2 3 4 8 7 6 5 +3V 10K_1206_8P4R_5% PCI_GNT0# R137 1 @ 2 1K_0402_5% @ 2 1K_0402_5% @ 2 1K_0402_5% USB_OC#1_R PCI_GNT1# R159 1 R601 1 2 10K_0402_5% USB_OC#4_R Have internal PU R603 1 2 10K_0402_5% Have internal PU PCI_GNT3# R558 1 A Have internal PU A16 swap overide Strap/Top-Block Swap Override jumper Compal Electronics, Inc. Compal Secret Data Security Classification Low=A16 swap override/Top-Block PCI_GNT3# Swap Override enabled High=Default * 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 * NV_ALE Enable Intel Anti-Theft Technology：8.2K PU to +3VS 2/10 USB6, USB7 not support on HM55 USB20_N8 28 USB20_P8 28 USB20_N9 35 USB20_P9 35 USB20_N10 34 USB20_P10 34 USB20_N11 35 USB20_P11 35 USB20_N12 34 USB20_P12 34 USB20_N13 34 USB20_P13 34 C DMI Termination Voltage USB/B (Right Side) EHCI 1 USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11 USB20_N12 USB20_P12 USB20_N13 USB20_P13 High=Endabled Low=Disable(floating) Boot BIOS Location 0 * PLTRST_VGA# 22 2 32.4_0402_1% OC[0..3] use for EHCI 1 OC[4..7] use for EHCI 2 PCI_GNT#1 2 R622 100K_0402_5% DIS@ IBEXPEAK-M_FCBGA107 A R619 1 DIS@ 100_0402_5% 4 Design Guide 1.5 Ver: 3.26.13 Terminating Unused Braidwood Interface Boot BIOS Strap PCI_GNT#0 D NV_ALE,NV_CLE has a weak internal pull-down NV_ALE NV_CLE H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24 PME# 2008/1/6 2009MOW01 change to 22 ohm 18,21 DGPU_HOLD_RST# USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P PLOCK# PLT_RST# U43 2 USBRBIAS PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 PCI_DEVSEL# PCI_FRAME# 36 CLK_PCI_LPC 14 CLK_PCI_FB AV11 BF5 R621 100K_0402_5% 2 +3VSDGPU USBRBIAS# B41 K53 A36 A48 PCI_IRDY# 5,21,32,36 PLT_RST# AY8 AY5 NV_WE#_CK0 NV_WE#_CK1 PCI_SERR# PCI_PERR# B NV_WR#0_RE# NV_WR#1_RE# PLT_RST_BUF# 34 1 REQ0# REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 AV7 @ 0.1U_0402_16V7K 4 2 F51 A46 B45 M53 AU2 NV_RB# Y 1 PIRQA# PIRQB# PIRQC# PIRQD# PCI_GNT0# F48 PCI_GNT1# K45 DGPU_PWMSEL# F36 PCI_GNT3# H53 PCI_GNT0#,PCI_GNT1#,PCI_GNT2#,PCI_GNT3# has a weak internal pull-up NV_RCOMP A 5 G38 H51 B37 A44 PCI_REQ0# PCI_REQ1# DGPU_SELECT# PCI_REQ3# PCI_FRAME# PCI_REQ1# PCI_PIRQH# PCI_TRDY# BD3 AY6 B 1 1 P PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_IRDY# PCI_PIRQD# DGPU_SELECT# PCI_DEVSEL# NV_ALE NV_CLE C443 2 G C/BE0# C/BE1# C/BE2# C/BE3# PCI_REQ0# PCI_PIRQB# PCI_PIRQF# PCI_REQ3# U42 PLT_RST# 3 J50 G42 H47 G34 PCI_PLOCK# PCI_PERR# PCI_PIRQE# PCI_STOP# AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6 MC74VHC1G08DFT2G_SC70-5 5 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% AV9 BG8 NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 +3VS AY9 BD1 AP15 BD8 NV_DQS0 NV_DQS1 NVRAM 2 2 2 2 PCI_PIRQA# PCI_PIRQG# PCI_PIRQC# PCI_SERR# 1 2 R556 R557 R559 R560 1 1 1 1 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 USB R554 R555 R581 R579 2 2 2 2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCI D 1 1 1 1 REV1.0 H40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H36 2 P U41E +3VS R160 R588 R585 R158 3 G 4 3 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 17 of 56
5 4 3 2 1 +3VS +3VS EC_GA20 CRT_DET 2 10K_0402_5% PCH_GPIO22 R651 1 2 10K_0402_5% PCH_GPIO39 R264 1 @ TACH3 / GPIO7 EC_SMI# F10 PCH_GPIO12 K9 T7 2 10K_0402_5% PCH_GPIO48 2 10K_0402_5% PCH_TEMP_ALERT# 17,21 DGPU_HOLD_RST# 2 10K_0402_5% VGA_PWROK R161 1 50 VGA_PWROK 0_0402_5% 2 10K_0402_5% PCH_GPIO34 2 10K_0402_5% EC_SCI# R243 1 R178 1 LAN_PHY_PWR_CTRL / GPIO12 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N AM3 CLK_CPU_BCLK# 5 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_CPU_BCLK 5 H10 GPIO24 AB12 GPIO27 PCH_GPIO28 V13 GPIO28 PCH_GPIO34 M11 STP_PCI# / GPIO34 PCH_GPIO35 V6 21 PCH_GPIO28 2 10K_0402_5% PCH_GPIO24 SCLOCK / GPIO22 PECI RCIN# BG10 T1 PROCPWRGD BD10 DIS@ R262 1 2 10K_0402_5% VGA_PRSNT_L# R659 1 2 10K_0402_5% DGPU_HOLD_RST# R154 1 @ 2 10K_0402_5% DGPU_PWROK_1 10 RST_GATE AB7 SATA2GP / GPIO36 TP1 AB13 SATA3GP / GPIO37 TP2 AW22 V3 SLOAD / GPIO38 TP3 R229 1 2 10K_0402_5% PCH_GPIO35 R263 1 @ SDATAOUT0 / GPIO39 TP4 H3 PCIECLKRQ6# / GPIO45 TP5 F1 PCIECLKRQ7# / GPIO46 TP6 AV43 SDATAOUT1 / GPIO48 TP7 AV45 SATA5GP / GPIO49 TP8 AF13 GPIO19 2 1 CRT_DET 1 High: CRT Plugged 2 G 2N7002E-T1-GE3_SOT23-3 dGPU iGPU * SG GPIO37 PCH_GPIO19 VGA_PRSNT_L# 0 0 1 0 1 0 D Q20 @ 3 29 CRT_DET# S GPIO8 This signal has a weak internal pull up can't Pull low GPIO27 On-Die PLL Voltage Regulator This signal has a weak internal pull up * H：On-Die voltage regulator enable L：On-Die PLL Voltage Regulator disable Note: the internal pull-up is disabled after RSMRST# de-asserts. The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is disabled. A F8 A4 A49 A5 A50 A52 A53 B2 B4 B52 B53 BE1 BE53 BF1 BF53 BH1 BH2 BH52 BH53 BJ1 BJ2 BJ4 BJ49 BJ5 BJ50 BJ52 BJ53 D1 D2 D53 E1 E53 TP9 C MAINPWON 44,45,47 +1.05VS_PCH R224 @ 330_0402_5% 1 2 C 2 B E VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 N18 TP11 AK41 TP13 AK42 TP14 M32 TP15 N32 TP16 M30 TP17 N30 TP18 H12 TP19 AB38 NC_3 AB42 NC_4 AB41 NC_5 B AB45 NC_2 H_THERMTRIP# AA23 NC_1 T39 INIT3_3V# REV1.0 Q14 2SC2411K_SOT23-3 @ AJ24 TP12 GPIO57 M18 TP10 R656 10K_0402_5% B AB6 PCH_TEMP_ALERT# AA4 PCH_GPIO57 +3VS +1.05VS_PCH AY46 RST_GATE H_THERMTRIP# 5 1 56_0402_5% AY45 2 10K_0402_5% PCH_GPIO27 GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable Low: VCCVRM VR Disable H_THERMTRIP# BB22 P3 PCH_GPIO48 21,36 PCH_TEMP_ALERT# 5 1 56_0402_5% 2009/08/23 Series resistor of 56±5% Pull-up of 56±5% to VTT (both these should be close to PCH) BA22 VGA_PRSNT_L# PCH_GPIO45 21 VGA_PRSNT_L# DGPU_PWR_EN VGA_PRSNT_R# 14,21,38,42 DGPU_PWR_EN PCH_GPIO28 PCH_GPIO57 PCH_GPIO45 RST_GATE 2 R221 3 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% H_CPUPWRGD THRMTRIP_PCH# SATACLKREQ# / GPIO35 RSVD 2 2 2 2 EC_KBRST# 36 BE10 THRMTRIP# H_PECI 5 EC_KBRST# 2 R220 NCTF C 1 1 1 1 EC_GA20 36 F38 PCH_GPIO39 R642 R640 R633 R630 EC_GA20 AA2 PCH_GPIO24 2 1K_0402_5% PCH_GPIO15 @ U2 DGPU_PWROK_1 Y7 10/7 Not Use PCH_GPIO15 PU 1K to +3V R242 1 A20GATE GPIO15 PCH_GPIO22 2 10K_0402_5% PCH_GPIO12 2 10K_0402_5% EC_SMI# R239 1 D GPIO8 (GPIO8 Have Internal Pull High,Should not be Pull-Low) (GPIO27 Have Internal Pull High) PCH_GPIO27 R245 1 R246 1 AF48 AF47 DGPU_HOLD_RST# 2 2009/09/07 GPIO24 pull high +3V +3V CLKOUT_PCIE7N CLKOUT_PCIE7P TACH2 / GPIO6 J32 (GPIO15 Have Internal Pull Down) PCH_GPIO15 R236 1 R658 1 R155 1 2 10K_0402_5% AH45 AH46 TACH1 / GPIO1 D37 EC_SCI# 36 EC_SMI# 2 10K_0402_5% DGPU_PWR_EN C38 DGPU_HPD_INT# 36 EC_SCI# CLKOUT_PCIE6N CLKOUT_PCIE6P BMBUSY# / GPIO0 DGPU_EDIDSEL# 30 DGPU_HPD_INT# DGPU_PWR_EN Pull Low at Page 43 Y3 CPU D 2 10K_0402_5% 1 21 CRT_DET 28 DGPU_EDIDSEL# R238 1 R654 1 EC_KBRST# R653 1 U41F 10K_0402_5% VGA_PRSNT_R# 10K_0402_5% VGA_PRSNT_L# 2 2 UMA ONLY@ MISC R655 1 R261 1 2 10K_0402_5% DGPU_EDIDSEL# 2 10K_0402_5% DGPU_HPD_INT# GPIO R582 1 R583 1 TP24 P6 2009/08/23 (Have internal PH,Do not pull down) C10 TP24_SST @ PAD T21 INIT3_3V This signal has weak internal PH, can't pull low IBEXPEAK-M_FCBGA107 A GPIO15 L：Intel ME Crypto Transport Layer Security(TLS) chiper suite with no confidentiality H：Intel ME Crypto Transport Layer Security(TLS) chiper suite with confidentiality * Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. CRB has a 1-k pull-up on this signal to +3.3VA rail. 5 Rev C 401869 Date: 4 3 2 Wednesday, June 30, 2010 Sheet 1 18 of 56
5 4 3 2 1 Need Modify 180 ohm @ 100MHz Bead +1.05VS_VTT +1.05VS_PCH +3VS Near AB24 Near AB24 Top Side Intel suggest follow CRB 8/21 All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V rails DG 1.6 (Page 329) Have Internal VRM C +1.05VS_PCH 10U_0805_10V4Z 1 C719 Near AN20 1 C321 2 Top Side 1U_0402_6.3V4Z 1 C342 2 1 C345 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 C348 2 2 1U_0402_6.3V4Z +3VS Follow Intel suggestion 8/21 Near AN35 0.1U_0402_16V4Z C329 2 1 B DG 1.6 (Page 329) T9 PAD Have Internal VRM +VCCAPLL_FDI @ +1.05VS_PCH 1 AF51 300mA VCCALVDS LVDS 42mA VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] VCCIO[50] VCCIO[51] VCCIO[52] VCCIO[53] AN30 AN31 VCCIO[54] VCCIO[55] AN35 VCC3_3[1] VCCFDIPLL AM23 VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4] AB34 VCC3_3[3] AD35 VCCIO[1] C331 Near AE50 61mA 6mA +3VS L20 UMOP@ 2 1 0.1UH_MLF1608DR10KT_10%_1608 0.1uH inductor, 200mA 1 2 R145 DIS ONLY@ 0_0402_5% +3VS 1 C Near AB34 VCCDMI[2] 2 0_0805_5% +1.05VS_PCH R192 1 2 0_0805_5% +1.8VS +VCCVRM AT24 VCCDMI[1] +1.05VS_PCH 10mil AU16 156mA CRB 0.9 is 180 ohm @ 100MHz DG0.8 is 600 ohm FB (Page 290) +1.8VS 15mil +VCCTX_LVDS C300 C316 1 UMOP@ 1 1 0.01U_0402_16V7K 22U_0805_6.3V6M C304 0.01U_0402_16V7K UMOP@ 2 2 UMOP@ 2 40mil AT16 VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9] D 2 R138 1 UMOP@ 2 0_0805_5% Near AP43 0.1U_0402_16V4Z 2 35mA 220 ohm bead,350mA 2 AB35 VCC3_3[4] VCCVRM[2] 1 2 L19 MBK1608221YZF_2P R172 0_0402_5% DIS ONLY@ AP43 AP45 AT46 AT45 3208mA 22U_0805_6.3V6M 1 C476 C291 R186 1 @ VCCVRM[1] BJ18 22U_0805_6.3V6M 1 1 C298 0.1U_0402_16V4Z 2 2 +VCCA_LVDS AH39 VCCAPLLEXP AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27 0.01U_0402_16V7K 1 C296 R136 0_0402_5% @ AH38 VSSA_LVDS VCC3_3[2] BJ24 VCCIO[24] AT22 +VCCVRM 10mil VSSA_DAC[2] HVCMOS @ +VCCAPLL_EXP AF53 59mA AK24 T20 PAD VSSA_DAC[1] +VCCADAC AE52 20mil +1.05VS_PCH 10mil AE50 VCCADAC[2] DMI Short J4 for PCH VCCCORE 2 VCCADAC[1] 69mA 2 C344 VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4]1524mA VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] 1 C718 2 AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31 AJ30 AJ31 60mA 15mil 2 1U_0402_6.3V4Z 1 CRT 10U_0805_10V4Z 1 1 NAND / SPI 1 PCI E* 2 @ JUMP_43X118 FDI 2 D POWER U41G VCC CORE J1 +VCC_DMI R204 1 2 0_0805_5% 1 C368 1U_0402_6.3V4Z 2 AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15 Near AT16 +1.8VS C372 1 B 0.1U_0402_16V4Z 2 85mA VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4] AM8 AM9 AP11 AP9 REV1.0 Near AK13 +3VS C387 IBEXPEAK-M_FCBGA107 1 0.1U_0402_16V4Z 2 Near AM8 A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 19 of 56
4 3 @ C295 C324 22U_0805_6.3V6M 1U_0402_6.3V4Z 2 2 C294 2 22U_0805_6.3V6M Near AD38 1U_0402_6.3V4Z VCCME[7] VCCME[8] V42 VCCME[9] VCCME[10] VCCME[11] Near V39 All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V rails Y42 C390 10mil 0.1U_0402_16V4Z +VCCRTCEXT 1 2 Near V9 C AU24 +VCCVRM 20mil +VCCADPLLA 20mil C330 1U_0402_6.3V4Z 2 1 2 Near AF32 C351 +PCH_VCCIO 2 0_0603_5% 2 1 C336 1U_0402_6.3V4Z 1 R139 1U_0402_6.3V4Z Near AH35 +3V 72mA VCCADPLLA[1] VCCADPLLA[2] 73mA VCCSUS3_3[30] U20 VCCSUS3_3[31] U22 2 VCCSUS3_3[32] VCC3_3[5] V16 VCC3_3[6] 1 Y16 2 C360 1 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z Near 2 AU18 AT18 A 20mil A12 VCC3_3[7] V_CPU_IO[1] V_CPU_IO[2] 2mA VCCRTC C386 1 C377 +VCC5REF Change to 1U for power sequence issue on ICH9 2 2 0.1U_0402_16V4Z Near A12 1 C692 1U_0402_6.3V4Z 2 2 Near BD51 D4 CH751H-40PT_SOD323-2 R141 100_0402_5% 1 2 2 1 2/12 Follow EDS1.11 Change to 100 ohm C +5VS C299 1U_0402_6.3V6K N36 P36 C337 U35 0.1U_0402_16V4Z 2 AD13 1 Near J38 +3VS Near AD13 AK3 AK1 10mil +VCCSATAPLL @ 2 C376 0.1U_0402_16V4Z PAD T23 DG 1.6 (Page 329) Have Internal VRM B AH22 AT20 VCCIO[10] AH19 VCCIO[11] AD20 VCCIO[12] AF22 1 VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] AD19 AF20 AF19 AH20 C371 1U_0402_6.3V4Z 2 VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] AB19 AB20 AB22 AD22 VCCME[13] VCCME[14] VCCME[15] VCCME[16] AA34 Y34 Y35 AA35 6mA VCCSUSHDA +VCCVRM +1.05VS_PCH +5VALW Near AB19 42 SBPWR_EN# PCH_VCCME13 PCH_VCCME14 PCH_VCCME15 PCH_VCCME16 R179 R164 R165 R173 1 1 1 1 2 2 2 2 L30 R176 0_0402_5% 2 @ 1 C343 @ 0.1U_0402_16V4Z +1.05VS_PCH 15mil S 2 1 Q8 R169 0_0402_5% G @ D AO3413L_SOT23-3 2 0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5% +5V +3V C357 1 A 2 1U_0402_6.3V4Z Near L30 Compal Electronics, Inc. Compal Secret Data Security Classification 0.1U_0402_16V4Z 2 @ Near K49 1 C373 1U_0402_6.3V4Z 1 +3VS VCCVRM[4] IBEXPEAK-M_FCBGA107 2 C349 1U_0402_6.3V6K 1 +RTCVCC 1 1 +5V Near F24 VCC3_3[12] > 1mA 10mil R189 2 100_0402_5% 1 M36 DCPSUS RTC 4.7U_0805_10V4Z 1 10mil VCC3_3[11] VCCSUS3_3[29] AT18 C359 +VCC5REFSUS VCC3_3[10] VCCSATAPLL[1] VCCSATAPLL[2] U19 1 +VCCADPLLB +3VS 2/12 Follow EDS1.11 Change to 100 ohm VCCIO[9] Near V15 1 +1.05VS_PCH +1.05VS_PCH Y22 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 D D5 CH751H-40PT_SOD323-2 L38 32mA DCPSST V15 C364 +3V J38 VCC3_3[9] C689 220U_B2_2.5VM_R35 1 +3VS +1.05VS_PCH K49 2 1U_0402_6.3V4Z 2 + 10mil VCC3_3[8] VCCIO[4] V12 Near P18 0.1U_0402_16V4Z V5REF 357mA R562 0_0402_5% @ L61 1 2 10UH_LB2012T100MR_20% 2 >1mA C691 @ Near U23 VCCIO[3] P18 C370 F24 VCCIO[2] Y22 0.1U_0402_16V4Z V5REF_SUS >1mA C688 220U_B2_2.5VM_R35 10uH inductor, 120mA VCC3_3[14] VCCIO[21] VCCIO[22] VCCIO[23] V12 C369 V23 1 + 0.1U_0402_16V4Z 2 Near A26 VCC3_3[13] VCCADPLLB[1] VCCADPLLB[2] AF32 +VCCSUS 1 2 C353 Near 0.1U_0402_16V4Z 10mil B VCCVRM[3] BD51 BD53 AH34 +VCCSST 1 2 C375 Near 0.1U_0402_16V4Z 10mil DCPRTC AF34 Near AH23 1 BB51 BB53 VCCME[12] AH23 AJ35 AH35 +VCCADPLLB +1.05VS_PCH V9 U23 VCCIO[56] VCCME[6] Y41 2 V39 V41 C341 2 AF42 Y39 C293 163mA VCCME[5] 0.1U_0402_16V4Z 2 1 1 1 C347 1 2 1 1 C350 Near BB51 L60 1 2 10UH_LB2012T100MR_20% 10uH inductor, 120mA 3 AF41 1 VCCSUS3_3[28] VCCME[4] 09/09/14 WW37 remove +VCCADPLLA +VCCADPLLA,+VCCADPLLB external 1U 1 VCCME[3] AF43 +3V Near V24 2 22U_0805_6.3V6M 1 VCCME[2] AD41 Follow Intel suggestion VCCME[1] AD39 Near Y20 +1.05VS_PCH C340 1U_0402_6.3V4Z 2 2 +1.05VS_PCH 1998mA AD38 0.1U_0402_16V4Z 2 V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26 +1.05VS_PCH 1 1 1 DCPSUSBYP USB 2 Near AF23 Y20 HDA C367 +PCH_VCCD6W VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27] 344mA Clock and Miscellaneous 10mil V24 V26 Y24 Y26 PCI/GPIO/LPC C352 1U_0402_6.3V4Z 2 @ DG2.0 Table162 Note2 (C295 unpop) 1 VCCLAN[2] 1 R199 0_0402_5% D VCCLAN[1] AF24 +VCCLAN VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] SATA 2 VCCACLK[2] PCI/GPIO/LPC @ 1 R187 1 0_0603_5% 15mil VCCACLK[1] AF23 +1.05VS_PCH 1 1 REV1.0 52mA AP51 AP53 DG 1.6 (Page 329) Have Internal VRM 2 POWER U41J 10mil +1.1VS_VCCACLK @ T17 PAD CPU 5 2 Wednesday, June 30, 2010 Sheet 1 20 of 56
5 4 U41I B A U41H VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366] H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14 AB16 VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] PCH XDP Port VSS[0] AA19 AA20 AA22 AM19 AA24 AA26 AA28 AA30 AA31 AA32 AB11 AB15 AB23 AB30 AB31 AB32 AB39 AB43 AB47 AB5 AB8 AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31 AD32 AD34 AU22 AD42 AD46 AD49 AD7 AE2 AE4 AF12 Y13 AH49 AU4 AF35 AP13 AN34 AF45 AF46 AF49 AF5 AF8 AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43 AH47 AH7 AJ19 AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32 AJ34 AT5 AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28 1 REV1.0 VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47 17 USB_OC#0_R R314 1 @ 2 33_0402_5% XDP_FN0 17 USB_OC#2_R R311 1 @ 2 33_0402_5% XDP_FN2 17 USB_OC#4_R R306 1 @ 2 33_0402_5% XDP_FN4 R312 R310 R309 R307 R305 R304 R300 R297 2 2 2 2 2 2 2 2 D 13 PCH_JTAG_TCK 13 PCH_JTAG_TMS 13 PCH_JTAG_TDI 13 PCH_JTAG_TDO XDP_FN8 XDP_FN9 XDP_FN10 XDP_FN11 XDP_FN12 XDP_FN13 XDP_FN14 XDP_FN15 2 33_0402_5% XDP_FN17 R287 R284 R286 R293 18 CRT_DET 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% R313 1 @ 14 PCH_GPIO20 14 PCH_GPIO18 13 PCH_GPIO21 13 PCH_GPIO19 14,18,38,42 DGPU_PWR_EN 18 VGA_PRSNT_L# 17,18 DGPU_HOLD_RST# 18,36 PCH_TEMP_ALERT# 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 1 1 1 1 1 1 1 1 @ @ @ @ @ @ @ @ 1 1 1 1 R289 1 @ 13 PCH_JTAG_RST# PCH_JTAG_TCK_R PCH_JTAG_TMS_R PCH_JTAG_TDI_R PCH_JTAG_TDO_R PCH_JTAG_RST#_R JP3 XDP_FN0 (XDP_FN1) 17 USB_OC#1_R XDP_FN2 (XDP_FN3) 17 USB_OC#3_R XDP_FN4 (XDP_FN5) 17 USB_OC#5_R (XDP_FN6) 17 USB_OC#6_R (XDP_FN7) 17 USB_OC#7_R 15 SYS_PWROK 5,15,36 PBTN_OUT# +3VS 1 R296 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 0_0402_5% 5 SMB_DATA_S3 5 SMB_CLK_S3 PCH_JTAG_TCK_R GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 CONN@ GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 (XDP_FN16) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 PCH_GPIO28 18 XDP_FN17 XDP_FN8 XDP_FN9 C XDP_FN10 XDP_FN11 XDP_FN12 XDP_FN13 XDP_FN14 XDP_FN15 +3VS 2 1 R295 1K_0402_5% PCH_JTAG_TDO_R PCH_JTAG_RST#_R PCH_JTAG_TDI_R PCH_JTAG_TMS_R PLT_RST# 5,17,32,36 XDP_DBRESET# 5,15 SAMTE_BSH-030-01-L-D-A B +3VS R294 @ 4.7K_0402_5% 1 2 2 C 2 6 12,14,34 PCH_SMBDATA 1 Q21A 2N7002DWH_SOT363-6 @ +3VS R290 @ 4.7K_0402_5% 1 2 IBEXPEAK-M_FCBGA107 +3VS SMB_DATA_S3 5 D AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47 B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49 BB5 BC10 BC14 BC18 BC2 BC22 BC32 BC36 BC40 BC44 BC52 BH9 BD48 BD49 BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50 BE6 BE8 BF3 BF49 BF51 BG18 BG24 BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47 BH7 C12 C50 D51 E12 E16 E20 E24 E30 E34 E38 E42 E46 E48 E6 E8 F49 F5 G10 G14 G18 G2 G22 G32 G36 G40 G44 G52 AF39 H16 H20 H30 H34 H38 H42 3 3 12,14,34 PCH_SMBCLK 4 +3VS SMB_CLK_S3 Q21B 2N7002DWH_SOT363-6 @ A REV1.0 Compal Electronics, Inc. Compal Secret Data Security Classification IBEXPEAK-M_FCBGA107 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 21 of 56
A B C D E U51A I2CS_SCL I2CS_SDA R773 R774 R864 R863 1 1 1 1 DIS@ DIS@ DIS@ DIS@ I2CB_SCL I2CB_SDA HDCP_SCL HDCP_SDA 4 I2CS_SCL 2 2 2 2 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 28 VGA_LCD_CLK 28 VGA_LCD_DATA 29 VGA_DDC_CLK VGA_DDC_DATA CRT29 EC_SMB_CK2 14,36 +1.05VSDGPU +3VSDGPU 5 I2CC_SCL I2CC_SDA I2CB_SCL I2CB_SDA VGA_DDC_CLK G1 VGA_DDC_DATA G4 I2CA_SCL I2CA_SDA F6 G6 I2CH_SCL I2CH_SDA EC_SMB_DA2 14,36 +3VSDGPU 1 C855 DIS@ 2 2 2 N/A N/A IN N/A N/A OUT N/A N/A OUT N/A N/A B 2 @ 22_0402_5% XTAL_OUTBUFF 1 R759 1 VSS 3 XIN/CLKIN R761 10K_0402_5% DIS@ 6 MODOUT 5 VDD OSC_SPREAD 4 2 1 OSC_OUT XOUT 3 +3VSDGPU 1 @ ASM3P2872AF-06OR_TSOT-23-6 2 OSC_SPREAD R763 1 @ C842 0.1U_0402_16V4Z 2 @ 22_0402_5% XTAL_SSIN XTAL_SSIN 12 27M_SSC 2 R756 R757 R758 DIS@ DIS@ DIS@ W4 AA7 AA6 R765 10K_0402_5% DIS@ If External Spread Spectrum not stuff then stuff resistor DACA_RED DACA_GREEN DACA_BLUE AM15 AM14 AL14 VGA_CRT_R 29 VGA_CRT_G 29 VGA_CRT_B 29 AM13 AL13 VGA_CRT_HSYNC VGA_CRT_VSYNC AJ12 AK12 AK13 DACB_RED DACB_GREEN DACB_BLUE BLM18PG181SN1D_0603 1 2 +3VSDGPU L80 DIS ONLY@ 150 mA DACA_VDD 1 1 2 124_0402_1% R770 DIS@ 2 0.1U_0402_16V4Z C849 DIS@ C850 1 AK4 AL4 AJ4 DACB_HSYNC DACB_VSYNC 29 29 AM1 AM2 1 C850 2 10K_0402_5% 0.1U_0402_16V4Z 2 R775 1 AG7 1 2 AK6 10K_0402_5% DIS@ R776 2 DIS@ C854 1 AH7 124_0402_1% DIS@ 2 1 C853 2 1 C851 2 1 C858 1 C857 2 2 2 C859 1 For CRT flicker issue change C858 C857 form .1u to 1u 20100617 4 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 2 1 C852 2009/5/12 Deciphered Date 2009/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: A 2 1 1 DIS@ 2 R764 10K_0402_5% REFOUT 2 2 AE1 V4 DACB_VDD DACB_VREF DACB_RSET 1 C856 DIS@ OUT U53 1 N11P-GE1-B-A2_BGA969 @ BLM18PG181SN1D_0603 SP_PLLVDD 2 1 DIS@ L81 Q60B 2N7002DWH_SOT363-6 DIS@ I2CS_SDA 4 3 E3 E4 G3 G2 HDCP_SCL HDCP_SDA Q60A 2N7002DWH_SOT363-6 1 6 DIS@ 2 VGA_LCD_CLK VGA_LCD_DATA I2CB_SCL I2CB_SDA N/A 0.1U_0402_16V4Z DIS@ 2 2.2K_0402_5% DIS@ 2 2.2K_0402_5% N/A N/A DIS ONLY@ 1 1 L OUT 1U_0402_6.3V6K R771 R772 LVDS OUT 1U_0402_6.3V6K VGA_LCD_CLK VGA_LCD_DATA N/A DIS ONLY@ DIS@ 2 2.2K_0402_5% DIS@ 2 2.2K_0402_5% L OSC_OUT 4.7U_0603_6.3V6M 1 1 I2CS_SCL I2CS_SDA N/A IN DIS ONLY@ R768 R769 VGA_CRT_B DACA_VDD DACA_VREF DACA_RSET E2 E1 N/A External Spread Spectrum VGA_CRT_G DACA_HSYNC DACA_VSYNC XTAL_OUTBUFF XTAL_SSIN I2CS_SCL I2CS_SDA VGA_DDC_CLK VGA_DDC_DATA NVVDD VID1 OUT GPIO14 DIS ONLY@ DIS@ 2 2.2K_0402_5% DIS@ 2 2.2K_0402_5% NVVDD VID0 N/A VGA_CRT_R Y5 W3 AF1 MIOB_CAL_PD_VDDQ MIOB_CAL_PU_GND N/A OUT 1 When the MIOx interface is unused, the interface must still be powered by 3.3V, a decoupling capacitor of 0.1uF should still be placed on thx MIOx_VDDQ power rail and 10k pull down should be used on MIOx_CLKIN 1U_0402_6.3V6K 1 1 XTAL_IN XTAL_OUT D1 D2 4.7U_0603_6.3V6M R766 R767 VID_PLLVDD B1 B2 XTAL_OUTBUFF XTAL_SSIN +3VSDGPU C836 DIS@ 18P_0402_50V8J 1 DIS ONLY@ XTALIN XTALOUT 1 DIS@ 2 R753 10K_0402_5% 4700P_0402_25V7K AD9 C848 DIS@ OUT GPIO13 XTALIN 1 1M_0402_5% 27MHZ_16PF_X5H027000FG1H DIS@ C838 DIS@ 18P_0402_50V8J DIS ONLY@ 2 VGA_BKL_EN GPIO12 2 R754 @ 2 W1 W2 MIOB_DE MIOB_CTL3 MIOB_VREF MIOB_CLKOUT_N H GPIO11 2 0_0402_5% Y5 470P_0402_50V7K C847 DIS@ XTALOUT DIS ONLY@ 2 SP_PLLVDD 1 @ R860 12 27M_CLK PLLVDD AF9 ENVDD OUT Unused MIO interface Y1 Y2 Y3 AB3 AB2 AB1 AC4 AC1 AC2 AC3 AE3 AE2 U6 W6 Y6 MIOB_CLKIN MIOB_CLKOUT AE9 SP_PLLVDD 1 H GPIO9 2 +3VSDGPU 10K_0402_5% OPT@ 1 1 DIS@ PEX_RST_N PEX_TERMP CLK 0.1U_0402_16V4Z 0.1U_0402_16V4Z C846 DIS@ 2 0.1U_0402_16V4Z 2 1U_0402_6.3V6K 4.7U_0603_6.3V6M 22U_0805_6.3V6M C845 DIS@ GPU_PLLVDD 1 VGA_PNL_PWM OUT GPIO10 R747 150_0402_1% 1 HDMI Hot-plug H +3VSDGPU 150_0402_1% 150_0402_1% 36 mA AM16 AG21 2 DIS@ 1 R762 2.49K_0402_1% H OUT GPIO8 2N7002E-T1-GE3_SOT23-3 1 VGA_idle 36 150_0402_1% 17 PLTRST_VGA# 3 USAGE DIS@ 1 PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N R760@ 2 1 200_0402_1% MIOB_HSYNC MIOB_VSYNC IN GPIO7 +3VSDGPU 1 DIS@ 2 R746 10K_0402_5% 1 AJ17 AJ18 1 14 PEG_CLKREQ# 14 CLK_PEG_VGA 14 CLK_PEG_VGA# GPIO1 GPIO5 1 2.2K_0402_5% 1 DIS@ 2 R745 10K_0402_5% 3 N/A +3VSDGPU +3VSDGPU Q54 N/A GPIO6 @ 2 R742 ACTIVE IN GPIO4 GPU_VID0 50 GPU_VID1 50 1 DIS@ 2 R743 DIS@ 10K_0402_5% 1 2 R744 10K_0402_5% I/O GPIO0 GPIO3 1 2.2K_0402_5% ENVDD 28 VGA_BKL_EN 16 2 PEX_REFCLK PEX_REFCLK_N PEX_CLKREQ_N MIOB_D0 MIOB_D1 MIOB_D2 MIOB_D3 MIOB_D4 MIOB_D5 MIOB_D6 MIOB_D7 MIOB_D8 MIOB_D9 MIOBD_10 MIOB_D11 MIOB_D12 MIOB_D13 MIOB_D14 GPIO GPIO2 @ 2 R741 VGA_HDMI_DET 30 VGA_PNL_PWM 28 2 AR16 AR17 AR13 PEX_TXP15 PEX_TXN15 PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N I2C DACs R755 10K_0402_5% DIS@ BLM18PG181SN1D_0603 2 1 +1.05VSDGPU DIS@ L79 1 1 C843 C844 DIS@ DIS@ 2 2 GPIO AL17 AM17 AM18 AM19 AL19 AK19 AL20 AM20 AM21 AM22 AL22 AK22 AL23 AM23 AM24 AM25 AL25 AK25 AL26 AM26 AM27 AM28 AL28 AK28 AK29 AL29 AM29 AM30 AM31 AM32 AN32 AP32 PEX_TXP9 PEX_TXN9 PEX_TXP10 PEX_TXN10 PEX_TXP11 PEX_TXN11 PEX_TXP12 PEX_TXN12 PEX_TXP13 PEX_TXN13 PEX_TXP14 PEX_TXN14 N1 P4 P1 P2 P3 T3 T2 T1 U4 U1 U2 U3 R6 T6 N6 N2 N3 L3 P5 N5 N4 R4 U5 T5 T4 PCI EXPRESS DVO 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PEX_TXP0 PEX_TXN0 PEX_TXP1 PEX_TXN1 PEX_TXP2 PEX_TXN2 PEX_TXP3 PEX_TXN3 PEX_TXP4 PEX_TXN4 PEX_TXP5 PEX_TXN5 PEX_TXP6 PEX_TXN6 PEX_TXP7 PEX_TXN7 PEX_TXP8 PEX_TXN8 MIOA_D0 MIOA_D1 MIOA_D2 MIOA_D3 MIOA_D4 MIOA_D5 MIOA_D6 MIOA_D7 MIOA_D8 MIOA_D9 MIOA_D10 MIOA_D11 MIOA_D12 MIOA_D13 MIOA_D14 MIOA_DE MIOA_HSYNC MIOA_VSYNC MIOA_CTL3 MIOA_VREF MIOA_CLKIN MIOA_CLKOUT MIOA_CAL_PD_VDDQ MIOA_CAL_PD_VDDGND MIOA_CLKOUT_N 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K K1 K2 K3 H3 H2 H1 H4 H5 H6 J7 K4 K5 H7 J4 J6 L1 L2 L4 M4 L7 L5 K6 L6 M6 G 2 PEG_GTX_C_HRX_P0 PEG_GTX_C_HRX_N0 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_N15 +3VSDGPU C807 C808 C810 C811 C812 C813 C814 C815 C816 C817 C818 C819 C820 C821 C822 C823 C824 C825 C826 C827 C828 C829 C830 C831 C832 C833 C834 C835 C837 C839 C840 C841 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 D 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ Part 1 of 7 PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N 1U_0402_6.3V6K 1 AP17 AN17 AN19 AP19 AR19 AR20 AP20 AN20 AN22 AP22 AR22 AR23 AP23 AN23 AN25 AP25 AR25 AR26 AP26 AN26 AN28 AP28 AR28 AR29 AP29 AN29 AN31 AP31 AR31 AR32 AR34 AP34 PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_N15 S S 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 C D Wednesday, June 30, 2010 Sheet E 22 of 56
5 4 3 2 1 U51D Part 4 of 7 AP13 AN13 AN8 AP8 AP10 AN10 AR11 AR10 AN11 AP11 2 GE1@ 1 R782 10K_0402_1% +3VSDGPU D @ 1 2 R777 5.1K_0402_5% 1 DIS@ 2 R778 45.3K_0402_1% GE@ R779 34.8K_0402_1% NonGE@ 34.8K_0402_1% strap1 R780 1 GE@ 2 R781 10K_0402_1% 1 GV2H@ 2 R782 30K_0402_5% strap2 strap0 1 X76@ 2 R783 20K_0402_5% @ 1 2 R784 5.1K_0402_5% ROM_SI 1 DIS@ 2 R785 10K_0402_1% @ 1 2 R786 5.1K_0402_5% ROM_SO GE@ 2 1 R788 15K_0402_5% ROM_SCLK NonGE@ R787 15K_0402_5% Mode E Command Mapping GB2-128 Package Femi C Mode C Command Mapping GB1-128 Package Data Bit 0..31 FBx_CMD1 A8 FBx_CMD2 FBx_CMD2 FBx_CMD21 FBx_CMD3 A7 FBx_CMD4 A2 AL2 AL3 R792 AJ3 4.7K_0402_5% AJ2 DIS@ AJ1 AH1 AH2 AH3 IFPF_L0 IFPF_L0_N IFPF_L1 IFPF_L1_N IFPF_L2 IFPF_L2_N IFPF_L3 IFPF_L3_N A1 FBx_CMD23 FBx_CMD5 A11 A9 FBx_CMD26 FBx_CMD6 A5 A4 FBx_CMD7 FBx_CMD7 A0 A12 FBx_CMD15 FBx_CMD8 CAS* CAS* FBx_CMD13 FBx_CMD9 BA1 A3 FBx_CMD4 FBx_CMD10 A9 A11 FBx_CMD18 FBx_CMD11 FBx_CMD29 FBx_CMD12 BA0 BA0 FBx_CMD27 FBx_CMD13 BA2 A15 FBx_CMD6 FBx_CMD14 A3 BA1 FBx_CMD17 FBx_CMD15 CS1_H FBx_CMD19 FBx_CMD16 ODT_H FBx_CMD22 FBx_CMD17 A4 A5 FBx_CMD12 FBx_CMD18 A13 A14 FBx_CMD28 FBx_CMD19 WE* A10 FBx_CMD10 FBx_CMD20 A1 A2 FBx_CMD25 FBx_CMD21 A10 WE* FBx_CMD9 FBx_CMD22 A12 A0 FBx_CMD1 FBx_CMD23 CS1_L* FBx_CMD11 FBx_CMD24 RAS* A8 CS0_H 1 1 2 2 +3VSDGPU R791 4.7K_0402_5% DIS@ D35 P7 AD20 GND_SENSE_0 GND_SENSE_1 GND_SENSE_2 IFPE_L0 IFPE_L0_N IFPE_L1 IFPE_L1_N IFPE_L2 IFPE_L2_N IFPE_L3 IFPE_L3_N A6 FBx_CMD24 AD19 E35 R7 AP2 AN3 IFPD_AUX_I2CX_SCL IFPD_AUX_I2CX_SDA_N IFPE_AUX_I2CY_SCL IFPE_AUX_I2CY_SDA_N AF3 AF2 IFPF_AUX_I2CZ_SCL IFPF_AUX_I2CZ_SDA_N TESTMODE JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N A7 B7 C7 D6 D7 +3VSDGPU FBx_CMD25 ODT_L FBx_CMD5 FBx_CMD26 A6 FBx_CMD16 FBx_CMD27 FBx_CMD20 FBx_CMD28 RST FBx_CMD29 A14 A13 FBx_CMD30 FBx_CMD30 A15 strap2 ROM_SI H 45K H 35K H 30K L 20K L 10K L 15K 64MX16 Hynix SA000032490 H 45K H 35K H 30K L 15K L 10K L 15K 20100113 Modify For GE1 strap0 ROM_SO ROM_SCLK strap1 strap2 ROM_SI 64MX16 Samsung SA000035720 H 45K H 35K H 10K L 20K L 10K L 15K 64MX16 Hynix SA000032490 H 45K H 35K H 10K L 15K L 10K L 15K strap1 strap2 ROM_SI 20100601 Modify For GE strap0 64MX16 Samsung SA000035720 ROM_SO ROM_SCLK ROM_SO ROM_SCLK H 45K L 35K L 10K L 20K L 10K H 15K 64MX16 Hynix SA000032490 H 45K L 35K L 10K L 15K L 10K H 15K 128MX16 Samsung SA00003MQ40 H 45K L 35K L 10K L 45K L 10K H 15K 128MX16 Hynix SA00003VS10 R790 1 DIS@ R793 1 DIS@ D H 45K L 35K L 10K L 35K L 10K H 15K C +NVVDD_SENSE 50 2 0_0402_5% 2 0_0402_5% R794 1 DIS@ 2 0_0402_5% R796 1 DIS@ 2 0_0402_5% NC NC NC NC NC A4 BUFRST_N NC AP35 AP14 AN14 AN16 AR14 AP16 PAD PAD PAD PAD PAD T25 T26 T27 T28 T29 @ @ @ @ @ R799 ROM_CS_N ROM_SI ROM_SO ROM_SCLK C3 D3 C4 D4 NC A5 N9 CEC JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST 2 R798 1 10K_0402_5% DIS@ SERIAL MULTI_STRAP_REF0_GND AB5 DIS@ 1 R797 2 10K_0402_5% ROM_CS# ROM_SI ROM_SO ROM_SCLK 10K_0402_5%1 2 @ +3VSDGPU DIS@ R801 2 1 40.2K_0402_1% 2 1 40.2K_0402_1% DIS@ R802 RST FBx_CMD14 strap0 B GENERAL DIS@ 10K_0402_5% 2 R800 1 strap1 64MX16 Samsung SA000035720 TEST AE4 AD4 20091214 Modify For GV2H 20091217 For layout convenient del R789 and R795 IFPC_AUX_I2CW_SCL IFPC_AUX_I2CW_SDA_N AP4 AN4 30 VGA_HDMI_SCLK 30 VGA_HDMI_SDATA RAS* FBx_CMD0 A AH6 AH5 AH4 AG4 AF4 AF5 AE6 AE5 CS0_L* A2 C5 D5 E5 E7 F4 G5 G11 G12 G14 G15 G27 G28 G24 G25 H32 J18 J19 J25 J26 L29 M7 M29 P6 P29 R29 U7 V6 Y4 AA4 AB4 AB7 AC5 AD6 AD29 AE29 AF6 AG6 AG20 AG29 AH29 AJ5 AK15 AL7 VDD_SENSE_0 VDD_SENSE_1 VDD_SENSE_2 IFPD_L0 IFPD_L0_N IFPD_L1 IFPD_L1_N IFPD_L2 IFPD_L2_N IFPD_L3 IFPD_L3_N CKE_L FBx_CMD8 B FBx_CMD0 IFPC_L0 IFPC_L0_N IFPC_L1 IFPC_L1_N IFPC_L2 IFPC_L2_N IFPC_L3 IFPC_L3_N AR8 AR7 AP7 AN7 AN5 AP5 AR5 AR4 32..63 FBx_CMD3 IFPB_TXC IFPB_TXC_N IFPB_TXD4 IFPB_TXD4_N IFPB_TXD5 IFPB_TXD5_N IFPB_TXD6 IFPB_TXD6_N IFPB_TXD7 IFPB_TXD7_N AM7 AM6 AL5 AM5 AM3 AM4 AP1 AR2 30 VGA_HDMI_TXD2+ 30 VGA_HDMI_TXD230 VGA_HDMI_TXD1+ 30 VGA_HDMI_TXD130 VGA_HDMI_TXD0+ 30 VGA_HDMI_TXD030 VGA_HDMI_TXC+ 30 VGA_HDMI_TXC- NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Straps MULTI LEVEL STRAPS IFPA_TXC IFPA_TXC_N IFPA_TXD0 IFPA_TXD0_N IFPA_TXD1 IFPA_TXD1_N IFPA_TXD2 IFPA_TXD2_N IFPA_TXD3 IFPA_TXD3_N LVDS/TMDS STRAP0 STRAP1 STRAP2 ROM_SI ROM_SO ROM_SCLK AM11 AM12 AM8 AL8 AM10 AM9 AK10 AL10 AK11 AL11 28 VGA_TXCLK+ 28 VGA_TXCLK28 VGA_TXOUT0+ 28 VGA_TXOUT028 VGA_TXOUT1+ 28 VGA_TXOUT128 VGA_TXOUT2+ 28 VGA_TXOUT2- BA2 STRAP0 STRAP1 STRAP2 A7 CKE_H MULTI_STRAP_REF1_GND W5 W7 V7 N11P-GE1-B-A2_BGA969 @ HIGH Compal Electronics, Inc. Compal Secret Data 2009/5/12 Issued Date LOW B5 B4 A Security Classification FBx_CMD31 M9 THERMDP THERMDN STRAP0 STRAP1 STRAP2 Deciphered Date 2010/04/15 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 Rev 401869 Date: 3 2 Wednesday, June 30, 2010 Sheet 1 23 of 56
5 4 3 2 1 U51E C1042 DIS@ 2 1 C1046 DIS@ 2 PEX_SVDD_3V3 MIOA_VDDQ MIOA_VDDQ MIOA_VDDQ MIOA_VDDQ 2 1 C879 DIS@ 2 1 C891 DIS@ 2 2 C900 DIS@ PEX_IOVDDQ 2 C892 DIS@ 1 C1032 DIS@ 2 2 C897 DIS@ 1 2 C898 DIS@ 1 2 C899 DIS@ C 1 C1031 DIS@ 2 C907 DIS@ 2 C904 DIS@ 2 10K_0402_5% C914 DIS@ C908 C915 DIS@ DIS@ C909 C906 DIS@ DIS@ C905 C916 DIS@ DIS@ C910 C917 DIS@ DIS@ C911 C918 DIS@ DIS@ R810 1 @ C936 0.1U_0603_25V7K DIS@ 2N7002DWH_SOT363-6 Q57A 1 2 1 2 DIS@ C1038 DIS@ C935 0.1U_0603_25V7K DIS@ C923 + 2 1 C924 DIS@ 2 C925 DIS@ 1 2 C926 DIS@ 1 2 C927 DIS@ 1 2 C928 DIS@ 1 2 1U_0402_6.3V6K 2 1 R812 470_0603_5% DIS@ 2N7002DWH_SOT363-6 4 3 1 6 R814 DIS@ 1K_0402_5% 2 1 1 C930 DIS@ 10U_0805_10V4Z 2 1 38,42,50 VGA_ON 2 1 2 R813 DIS@ 3.3K_0402_5% 2 10K_0402_5% DIS@ 4.7U_0603_6.3V6M 1 2 C934 1 OPT@ DIS ONLY@ 0.1U_0402_16V4Z DIS ONLY@ 0.1U_0402_16V4Z DIS ONLY@ 4.7U_0603_6.3V6M DIS ONLY@ 1U_0402_6.3V6K 1 C934 3VSdelay_gate A 1 2 DIS@ G 2 C933 100mil(1.5A) D 2 2 R811 100K_0402_5% C1036 +VGA_CORE AO3413L_SOT23-3 Q56 3 1 DIS@ 385 mA IFPC_IOVDD DIS@ 2 0_0805_5% S BLM18PG181SN1D_0603 2 1 L86 DIS ONLY@ 1 1 C931 C932 C1035 22U_0805_6.3V6M DIS@ 10U_0805_10V4Z 2 DIS@ 22U_0805_6.3V6M C929 1 C1034 0.047U_0402_16V7K DIS@ +3VSDGPU 0.047U_0402_16V7K C1037 2 10K_0402_5% 0.047U_0402_16V7K +3VS C1052 1 0.22U_0603_16V7K C1052 22U_0805_6.3V6M 1 +3VALW +1.05VSDGPU +VGA_CORE DIS@ Q57B 3VSdelay_gate 5 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 VDD_72 VDD_73 VDD_74 VDD_75 VDD_76 VDD_77 VDD_78 VDD_79 VDD_80 VDD_81 VDD_82 VDD_83 VDD_84 VDD_85 VDD_86 VDD_87 VDD_88 VDD_89 VDD_90 VDD_91 VDD_92 VDD_93 VDD_94 VDD_95 VDD_96 VDD_97 VDD_98 VDD_99 VDD_100 VDD_101 VDD_102 VDD_103 VDD_104 VDD_105 VDD_106 VDD_107 VDD_108 VDD_109 VDD_110 Part 7 of 7 POWER IFPF_IOVDD +3VSDGPU 4700P_0402_16V7K 1 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AD12 AD14 AD16 AD18 AD22 AD24 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 M12 M14 M16 M18 M20 M22 M24 P11 P13 P15 P17 P19 0.01U_0402_16V7K IFPE_IOVDD 330U_D2_2V_Y 1 2 120mA 2 1 +3VSDGPU 0_0603_5% DIS@ U51G N11P-GE1-B-A2_BGA969 @ OPT@ C922 DIS ONLY@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 DIS ONLY@ 1 C921 DIS ONLY@ 0.1U_0402_16V4Z 2 2 120mA +VGA_CORE 160 mA C920 2200mA PEX_SVDD_3V3 R803 4700P_0402_16V7K IFPEF_PLLVDD IFPEF_RSET AA9 AB9 W9 Y9 +1.8VS DIS ONLY@ 2 1 +1.05VSDGPU +VGA_CORE MIOB_VDDQ_0 MIOB_VDDQ_1 MIOB_VDDQ_2 MIOB_VDDQ_3 IFPC_PLLVDD 4.7U_0603_6.3V6M C919 DIS ONLY@ 1U_0402_6.3V6K 1 C880 DIS@ 2 PEX_IOVDD 1 4.7U_0603_6.3V6M 1 1U_0603_10V4Z 2 C1026 DIS@ 0.1U_0402_16V4Z 1 0.22U_0603_16V7K BLM18PG181SN1D_0603 D 1 C890 DIS@ +VGA_CORE 1 L85 DIS ONLY@ C1041 DIS@ 2 1 L82 DIS@ BLM18PG181SN1D_0603 0.01U_0402_16V7K AJ6 AL1 follow the DS04644 2 22U_0805_6.3V6M C878 DIS@ 2 10U_0805_6.3V6M 4.7U_0603_6.3V6M 1U_0603_10V4Z 1U_0402_6.3V6K 2 1 1 +3VS_DELAY +3VSDGPU 1 0.1U_0402_16V4Z 1 +3VSDGPU P9 R9 T9 U9 IFPD_IOVDD DIS@ AD7 C1050 1 J10 J11 J12 J13 J9 0.1U_0402_16V4Z VDD33_0 VDD33_1 VDD33_2 VDD33_3 VDD33_4 PWR Sequence B +1.05VSDGPU 22U_0805_6.3V6M 1 10U_0805_6.3V6M 4.7U_0603_6.3V6M 1U_0603_10V4Z 0.1U_0402_16V4Z 1U_0603_10V4Z 0.01U_0402_25V7K 1U_0603_10V4Z 0.1U_0402_16V4Z 4.7U_0603_6.3V6M 2 C889 DIS@ C877 DIS@ 1 0.01U_0402_16V7K 1 C1050 1 2 0.022U_0402_16V7K 1 2 C1043 DIS@ 1 4.7U_0603_6.3V6M AG19 F7 IFPD_PLLVDD IFPD_RSET DIS@ AE7 OPT@ C1049 DIS ONLY@ 2 2 C888 DIS@ C1033 DIS@ 1 0.01U_0402_16V7K R809 1 2 1K_0402_1% R861 1 2 1K_0402_1% 0.1U_0402_16V4Z C913 PEX_SVDD_3V3_0 PEX_SVDD_3V3_1 IFPC_IOVDD AC6 AB6 AK8 1K_0402_5% 1 DIS@ 2 R807 IFPE_RSET 1K_0402_1% 2 DIS@ 1 R808 IFPB_IOVDD 1 2 0.022U_0402_16V7K 2 10K_0402_5% C876 DIS@ 2 0.01U_0402_16V7K 1 DIS ONLY@ 2 0.1U_0402_16V4Z 1U_0402_6.3V6K 2 1 DIS ONLY@ C912 DIS ONLY@ 4.7U_0603_6.3V6M 1 PEX_PLLDVDD IFPC_PLLVDD IFPC_RSET AJ8 IFPC_IOVDD +1.8VSDGPU 2 1 L88 DIS ONLY@ BLM18PG181SN1D_0603 AG14 IFPA_IOVDD IFPB_IOVDD AJ9 AK7 IFPC_PLLVDD DIS@ 1 R806 IFPD_RSET 1K_0402_1% 2 C1048 1 C1048 2 C887 DIS@ 1 0.022U_0402_16V7K 2 C875 DIS@ 2 1 0.01U_0402_16V7K 1 AG9 AG10 IFPC_PLLVDD 2 1 IFPC_RSET DIS@ R805 1K_0402_1% IFPC_IOVDD OPT@ C903 DIS ONLY@ 2 0.1U_0402_16V4Z 2 C902 C1047 DIS@ 1 2 PEX_PLLVDD PEX_PLLVDD IFPA_IOVDD DIS ONLY@ 2 1 0.1U_0402_16V4Z 1U_0402_6.3V6K C901 DIS ONLY@ 1 DIS ONLY@ 1 L84 DIS ONLY@ BLM18PG181SN1D_0603 4.7U_0603_6.3V6M 100 mA #SI Change to +VDDMEM18 2 2 +3VSDGPU IFPA_IOVDD IFPB_IOVDD 2 10K_0402_5% +1.8VSDGPU PEX_IOVDD AK16 AK17 AK21 AK24 AK27 1 PEX_SVDD_3V3 IFPAB_PLLVDD IFPAB_RSET C1045 DIS@ 2 1U_0603_10V4Z 1K_0402_1% 2 R804 @ PEX_PLLDVDD 0.022U_0402_16V7K C895 1 C1053 IFPAB_PLLVDD AK9 IFPAB_RSET AJ11 1 C1044 DIS@ 2 1 +1.05VSDGPU 0.1U_0402_16V4Z 2 OPT@ 1 DIS ONLY@ 2 0.1U_0402_16V4Z 1 C896 0.1U_0402_16V4Z 2 DIS ONLY@ C894 1 1 C895 PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 1 0.1U_0402_16V4Z C884 DIS@ 0.1U_0402_16V4Z C874 DIS@ 0.047U_0402_16V7K C873 DIS@ 0.047U_0402_16V7K C872 DIS@ 2 IFPAB_PLLVDD DIS ONLY@ 1U_0402_6.3V6K 2 follow the DS04644 DIS ONLY@ 0.1U_0402_16V4Z DIS ONLY@ 4.7U_0603_6.3V6M C C893 2 1 100mA BLM18PG181SN1D_0603 2 1 L83 DIS ONLY@ 1 2 DIS@ C870 0.047U_0402_16V7K C869 0.1U_0402_16V4Z 2 1 PEX_IOVDDQ PEX_IOVDD 0.1U_0402_16V4Z +1.05VSDGPU 1 DIS@ 0.1U_0402_16V4Z FBVDDQ PEX_IOVDDQ AG11 AG12 AG13 AG15 AG16 AG17 AG18 AG22 AG23 AG24 AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16 0.1U_0402_16V4Z D PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14 PEX_IOVDDQ_15 PEX_IOVDDQ_16 PEX_IOVDDQ_17 PEX_IOVDDQ_18 PEX_IOVDDQ_19 PEX_IOVDDQ_20 PEX_IOVDDQ_21 PEX_IOVDDQ_22 PEX_IOVDDQ_23 PEX_IOVDDQ_24 0.1U_0402_16V4Z FBVDDQ FBVDDQ_0 FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 POWER J23 J24 J29 AA27 AA29 AA31 AB27 AB29 AC27 AD27 AE27 AJ28 B18 E21 G17 G18 G22 G8 G9 H29 J14 J15 J16 J17 J20 J21 J22 N27 P27 R27 T27 U27 U29 V27 V29 V34 W27 Y27 DIS@ C1051 C868 0.01U_0402_16V7K 0.01U_0402_16V7K DIS@ C867 DIS@ C866 0.01U_0402_16V7K DIS@ C865 2 0.01U_0402_16V7K 1 DIS@ C864 2 0.1U_0402_16V4Z C863 2 1 DIS@ 1 4.7U_0603_6.3V6M 2 4.7U_0603_6.3V6M 2 1 DIS@ 22U_0805_6.3V6M 1 DIS@ C1040 DIS@ C1039 22U_0805_6.3V6M FBVDDQ 0.1U_0402_16V4Z Part 5 of 7 +1.5VSDGPU P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17 V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24 B A 2 N11P-GE1-B-A2_BGA969 @ Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/5/12 Deciphered Date 2009/12/31 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Sheet Wednesday, June 30, 2010 1 24 of 56
A VRAM Interface MDC[15..0] MDA[15..0] MDA[31..16] 26 MDA[31..16] 27 MDC[47..32] MDA[63..48] 26 MDA[63..48] U51C U51B CMDA[30..0] Part 2 of 7 MDA0 L32 MDA1 N33 MDA2 L33 MDA3 N34 MDA4 N35 MDA5 P35 MDA6 P33 MDA7 P34 MDA8 K35 MDA9 K33 MDA10 K34 MDA11 H33 MDA12 G34 MDA13 G33 MDA14 E34 MDA15 E33 MDA16 G31 MDA17 F30 MDA18 G30 MDA19 G32 MDA20 K30 MDA21 K32 MDA22 H30 MDA23 K31 MDA24 L31 MDA25 L30 MDA26 M32 MDA27 N30 MDA28 M30 MDA29 P31 MDA30 R32 MDA31 R30 MDA32 AG30 MDA33 AG32 MDA34AH31 MDA35AF31 MDA36AF30 MDA37AE30 MDA38AC32 MDA39AD30 MDA40AN33 MDA41AL31 MDA42 AM33 MDA43AL33 MDA44AK30 MDA45AK32 MDA46 AJ30 MDA47AH30 MDA48AH33 MDA49AH35 MDA50AH34 MDA51AH32 MDA52 AJ33 MDA53AL35 MDA54 AM34 MDA55 AM35 MDA56AF33 MDA57AE32 MDA58AF34 MDA59AE35 MDA60AE34 MDA61AE33 MDA62AB32 MDA63AC35 FB_PLLAVDD AG27 AF27 FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 MEMORY INTERFACE A 1 FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 P32 H34 J30 P30 AF32 AL32 AL34 AF35 MDC0 MDC1 MDC2 MDC3 MDC4 MDC5 MDC6 MDC7 MDC8 MDC9 MDC10 MDC11 MDC12 MDC13 MDC14 MDC15 MDC16 MDC17 MDC18 MDC19 MDC20 MDC21 MDC22 MDC23 MDC24 MDC25 MDC26 MDC27 MDC28 MDC29 MDC30 MDC31 MDC32 MDC33 MDC34 MDC35 MDC36 MDC37 MDC38 MDC39 MDC40 MDC41 MDC42 MDC43 MDC44 MDC45 MDC46 MDC47 MDC48 MDC49 MDC50 MDC51 MDC52 MDC53 MDC54 MDC55 MDC56 MDC57 MDC58 MDC59 MDC60 MDC61 MDC62 MDC63 DQSA#[3..0] DQSA0 L34 H35 DQSA1 DQSA2 J32 N31 DQSA3 AE31 DQSA4 AJ32 DQSA5 AJ34 DQSA6 AC33 DQSA7 26 DQSA#[7..4] L35 DQSA#0 G35 DQSA#1 H31 DQSA#2 N32 DQSA#3 AD32 DQSA#4 AJ31 DQSA#5 AJ35 DQSA#6 AC34 DQSA#7 FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 DQMA[7..4] 26 26 DQSA[3..0] 26 DQSA[7..4] 26 +1.5VSDGPU B13 D13 A13 A14 C16 B16 A17 D16 C13 B11 C11 A11 C10 C8 B8 A8 E8 F8 F10 F9 F12 D8 D11 E11 D12 E13 F13 F14 F15 E16 F16 F17 D29 F27 F28 E28 D26 F25 D24 E25 E32 F32 D33 E31 C33 F29 D30 E29 B29 C31 C29 B31 C32 B32 B35 B34 A29 B28 A28 C28 C26 D25 B25 A25 40.2_0402_1% 2 DIS@ 1 R815 K27 FBCAL_PD_VDDQ 40.2_0402_1% 2 FBA_CLK0 FBA_CLK0_N T32 T31 FBA_CLK1 FBA_CLK1_N AC31 AC30 DQMC[3..0] 27 DQMC[7..4] 27 DQSC#[3..0] 27 DQSC#[7..4] 27 DQSC[3..0] 27 DQSC[7..4] 27 DIS@ 1 R817 M27 FBCAL_TERM_GND CMDC0 CMDC1 CMDC2 CMDC3 CMDC4 CMDC5 CMDC6 CMDC7 CMDC8 CMDC9 CMDC10 CMDC11 CMDC12 CMDC13 CMDC14 CMDC15 CMDC16 CMDC17 CMDC18 CMDC19 CMDC20 CMDC21 CMDC22 CMDC23 CMDC24 CMDC25 CMDC26 CMDC27 CMDC28 CMDC29 CMDC30 FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3 FBC_DQM4 FBC_DQM5 FBC_DQM6 FBC_DQM7 A16 D10 F11 D15 D27 D34 A34 D28 DQMC0 DQMC1 DQMC2 DQMC3 DQMC4 DQMC5 DQMC6 DQMC7 FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7 B14 B10 D9 E14 F26 D31 A31 A26 DQSC#0 DQSC#1 DQSC#2 DQSC#3 DQSC#4 DQSC#5 DQSC#6 DQSC#7 C14 A10 E10 D14 E26 D32 A32 B26 DQSC0 DQSC1 DQSC2 DQSC3 DQSC4 DQSC5 DQSC6 DQSC7 FBC_CLK0 FBC_CLK0_N E17 D17 CLKC0 27 CLKC0# 27 FBC_CLK1 FBC_CLK1_N D23 E23 CLKC1 27 CLKC1# 27 2 G19 1 @ 10K_0402_5% R818 FBCAL_PU_GND 40.2_0402_1% 2 CLKA0 26 CLKA0# 26 DIS@ 1 R816 L27 CLKA1 26 CLKA1# 26 FB_VREF J27 FB_VREF +1.5VSDGPU 2 1 T30 R819 10K_0402_5% @ FBA_DEBUG 27 C17 B19 D18 F21 A23 D21 B23 E20 G21 F20 F19 F23 A22 C22 B17 F24 C25 E22 C20 B22 A19 D22 D20 E19 D19 F18 C19 F22 C23 B20 A20 FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7 FBC_D00 FBC_D01 FBC_D02 FBC_D03 FBC_D04 FBC_D05 FBC_D06 FBC_D07 FBC_D08 FBC_D09 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63 FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8 FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30 FBC_DEBUG DQMA[3..0] 26 DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7 CMDC[30..0] Part 3 of 7 26 V32 CMDA0 W31 CMDA1 U31 CMDA2 Y32 CMDA3 AB35 CMDA4 AB34 CMDA5 W35 CMDA6 W33 CMDA7 W30 CMDA8 T34 CMDA9 T35 CMDA10 AB31 CMDA11 Y30 CMDA12 Y34 CMDA13 W32 CMDA14 AA30 CMDA15 AA32 CMDA16 Y33 CMDA17 U32 CMDA18 Y31 CMDA19 U34 CMDA20 Y35 CMDA21 W34 CMDA22 V30 CMDA23 U35 CMDA24 U30 CMDA25 U33 CMDA26 AB30 CMDA27 AB33 CMDA28 T33 CMDA29 W29 CMDA30 FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7 FB_DLLAVDD FB_PLLAVDD MDC[63..48] 27 MDC[63..48] MDA[47..32] 26 MDA[47..32] MDC[47..32] MEMORY INTERFACE C 26 MDA[15..0] U51F MDC[31..16] 27 MDC[31..16] +1.5VSDGPU N11P-GE1-B-A2_BGA969 @ +1.5VSDGPU 1 N11P-GE1-B-A2_BGA969 @ Rt 2 R820 @ 1K_0402_1% FB_VREF GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 Part 6 of 7 GND_97 GND_98 GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 V18 V20 V22 V24 V31 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25 AA2 AA5 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA34 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC9 AD2 AD5 AD11 AD13 AD15 AD17 AD21 AD23 AD25 AD31 AD34 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AG2 AG5 AG31 AG34 AK2 AK5 AK14 AK31 AK34 AL6 AL9 AL12 AL15 AL18 AL21 AL24 AL27 AL30 AN2 AN34 AP3 AP6 AP9 AP12 AP15 AP18 AP21 AP24 AP27 AP30 AP33 1 1 1 +1.05VSDGPU L87 DIS@ BLM18PG181SN1D_0603 R821 @ 1K_0402_1% Rb 0.1U_0402_16V4Z 2 C940 C939 1 DIS@ 2 DIS@ 2 1 4.7U_0603_6.3V6M 2 C937 DIS@ 1 DIS@ C938 0.01U_0402_25V7K 1 1U_0402_6.3V6K 0.1U_0402_16V4Z 2 2 FB_PLLAVDD B3 B6 B9 B12 B15 B21 B24 B27 B30 B33 C2 C34 E6 E9 E12 E15 E18 E24 E27 E30 F2 F31 F34 F5 J2 J5 J31 J34 K9 L9 M2 M5 M11 M13 M15 M17 M19 M21 M23 M25 M31 M34 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 P12 P14 P16 P18 P20 P22 P24 R2 R5 R31 R34 T11 T13 T15 T17 T19 T21 T23 T25 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 V2 V5 V9 V12 V14 V16 GND 27 MDC[15..0] 1 2 C941 @ N11P-GE1-B-A2_BGA969 @ Compal Electronics, Inc. Compal Secret Data Security Classification 2009/5/12 Issued Date Deciphered Date 2009/12/31 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: A Wednesday, June 30, 2010 Sheet 25 of 56
5 4 3 2 CMDA0 CMDA25 CMDA28 CMDA16 CMDA27 DQSA#[7..0] DQMA[7..0] MDA[63..0] 25 MDA[63..0] U54 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% X76@ U55 DQMA[7..0] 25 DQMA[7..0] CMDA[30..0] 25 CMDA[30..0] DQSA#[7..0] 25 DQSA#[7..0] MODE C PULL DOWN SIGNAL:RST，CKE，ODT CMDA[30..0] 25 CMDA[30..0] 1 1 1 1 1 DQSA[7..0] 25 DQSA[7..0] MDA[63..0] 25 MDA[63..0] X76@ U56 VDD VDD VDD VDD VDD VDD VDD VDD VDD B2 D9 G7 K2 K8 N1 N9 R1 R9 E7 D3 G3 B7 CMDA28 DQSL DQSU T2 RESET L8 ZQ/ZQ0 E7 D3 DML DMU DQSA#0 DQSA#3 G3 B7 DQSL DQSU A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 CMDA28 T2 RESET ZQA1 L8 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ZQ/ZQ0 1 DIS@ R833 C944 1K_0402_1% DIS@ 1 2 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 B2 D9 G7 K2 K8 N1 N9 R1 R9 2 MEM_VREFA2 1 DIS@ R834 C945 1K_0402_1% DIS@ DIS@ CLKA0# 2 CMDA16 CMDA11 CMDA24 CMDA8 CMDA21 E3 F7 F2 F8 H3 H8 G2 H7 MDA43 MDA45 MDA40 MDA44 MDA41 MDA47 MDA42 MDA46 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDA51 MDA52 MDA48 MDA54 MDA49 MDA55 MDA50 MDA53 VDD VDD VDD VDD VDD VDD VDD VDD VDD B2 D9 G7 K2 K8 N1 N9 R1 R9 CLKA1 J7 CLKA1# K7 CMDA27 K9 CK CK CKE/CKE0 C F3 C7 +1.5VSDGPU VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ VDDQ DQSL VDDQ DQSU VDDQ A1 A8 C1 C9 D2 E9 F1 H2 H9 CMDA16 CMDA11 CMDA24 CMDA8 CMDA21 K1 L2 J3 K3 L3 DQSA5 DQSA6 F3 C7 DML DMU DQSL DQSU CMDA28 T2 CLKA1# 25 CLKA1# D +1.5VSDGPU BA0 BA1 BA2 DQSA#7 G3 DQSA#4 B7 R836 240_0402_1% K1 L2 J3 K3 L3 DQSA7 DQSA4 CLKA1 25 CLKA1 R835 240_0402_1% DIS@ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 CMDA12 M2 CMDA14 N8 CMDA30 M3 RESET VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 L8 ZQ/ZQ0 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B1 B9 D1 D8 E2 E8 F9 G1 G9 J1 L1 J9 L9 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 ZQA2 B1 B9 D1 D8 E2 E8 F9 G1 G9 DIS@ L8 J1 L1 J9 L9 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 ODT/ODT0 CS/CS0 RAS CAS WE ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ VDDQ DQSL VDDQ DQSU VDDQ A1 A8 C1 C9 D2 E9 F1 H2 H9 DQMA5 E7 DQMA6 D3 DML DMU DQSA#5 G3 DQSA#6 B7 DQSL DQSU CMDA28 T2 RESET VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B1 B9 D1 D8 E2 E8 F9 G1 G9 ZQA3 R840 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 CMDA22 N3 CMDA4 P7 CMDA20 P3 CMDA9 N2 CMDA6 P8 CMDA17 P2 CMDA3 R8 CMDA26 R2 CMDA1 T8 CMDA5 R3 CMDA19 L7 CMDA10 R7 CMDA7 N7 CMDA29 T3 CMDA18 T7 CMDA13 M7 DIS@ 243_0402_1% DIS@ J1 L1 J9 L9 CK CK CKE/CKE0 243_0402_1% B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ MDA33 MDA38 MDA32 MDA37 MDA34 MDA39 MDA35 MDA36 VDD VDD VDD VDD VDD VDD VDD VDD VDD VREFCA VREFDQ +1.5VSDGPU R839 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 MEM_VREFA3 1 CLKA0 25 CLKA0 25 CLKA0# J1 L1 J9 L9 D7 C3 C8 C2 A7 A2 B8 A3 X76@ MEM_VREFA3 M8 H1 DQMA7 E7 DQMA4 D3 1 DQMA0 DQMA3 R838 DIS@ 2 F3 C7 A1 A8 C1 C9 D2 E9 F1 H2 H9 243_0402_1% R837 B 243_0402_1% 243_0402_1% 1 ZQA0 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSA0 DQSA3 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ DQSL VDDQ DQSU VDDQ ODT/ODT0 CS/CS0 RAS CAS WE 1 DQSA#2 DQSA#1 DML DMU K1 L2 J3 K3 L3 2 DQMA2 DQMA1 CMDA25 CMDA2 CMDA24 CMDA8 CMDA19 2 F3 C7 VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ VDDQ DQSL VDDQ DQSU VDDQ MDA57 MDA63 MDA62 MDA61 MDA59 MDA56 MDA60 MDA58 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 BA0 BA1 BA2 CLKA1 J7 CLKA1# K7 CMDA27 K9 R832 1K_0402_1% DIS@ 0.1U_0402_10V6K~D DQSA2 DQSA1 +1.5VSDGPU A1 A8 C1 C9 D2 E9 F1 H2 H9 ODT/ODT0 CS/CS0 RAS CAS WE 2 R831 1K_0402_1% DIS@ E3 F7 F2 F8 H3 H8 G2 H7 +1.5VSDGPU CMDA12 M2 CMDA14 N8 CMDA30 M3 +1.5VSDGPU 0.1U_0402_10V6K~D K1 L2 J3 K3 L3 1 +1.5VSDGPU +1.5VSDGPU CMDA25 CMDA2 CMDA24 CMDA8 CMDA19 2 2 +1.5VSDGPU MEM_VREFA1 1 DIS@ R830 C943 1K_0402_1% DIS@ 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 1 CK CK CKE/CKE0 DIS@ R829 C942 1K_0402_1% DIS@ MEM_VREFA0 1 U57 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VREFCA VREFDQ 2 J7 K7 K9 CLKA0 CLKA0# CMDA0 DIS@ 1 C BA0 BA1 BA2 R827 1K_0402_1% CMDA22 N3 CMDA4 P7 CMDA20 P3 CMDA9 N2 CMDA6 P8 CMDA17 P2 CMDA3 R8 CMDA26 R2 CMDA1 T8 CMDA5 R3 CMDA19 L7 CMDA10 R7 CMDA7 N7 CMDA29 T3 CMDA18 T7 CMDA13 M7 R828 1K_0402_1% DIS@ 2 CK CK CKE/CKE0 M2 N8 M3 MDA27 MDA26 MDA31 MDA28 MDA29 MDA25 MDA30 MDA24 MEM_VREFA2 M8 H1 +1.5VSDGPU 1 J7 K7 K9 CLKA0 CLKA0# CMDA0 CMDA12 CMDA9 CMDA13 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD D7 C3 C8 C2 A7 A2 B8 A3 +1.5VSDGPU 2 BA0 BA1 BA2 +1.5VSDGPU A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 MDA0 MDA7 MDA1 MDA4 MDA3 MDA6 MDA2 MDA5 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 E3 F7 F2 F8 H3 H8 G2 H7 1 M2 N8 M3 MDA13 MDA11 MDA14 MDA10 MDA12 MDA8 MDA15 MDA9 CMDA7 CMDA20 CMDA4 CMDA14 CMDA17 CMDA6 CMDA26 CMDA3 CMDA1 CMDA10 CMDA21 CMDA5 CMDA22 CMDA18 CMDA29 CMDA30 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 2 CMDA12 CMDA9 CMDA13 D7 C3 C8 C2 A7 A2 B8 A3 VREFCA VREFDQ 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 MEM_VREFA1 M8 H1 0.1U_0402_10V6K~D N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 MDA21 MDA18 MDA23 MDA16 MDA22 MDA19 MDA20 MDA17 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 CMDA7 CMDA20 CMDA4 CMDA14 CMDA17 CMDA6 CMDA26 CMDA3 CMDA1 CMDA10 CMDA21 CMDA5 CMDA22 CMDA18 CMDA29 CMDA30 E3 F7 F2 F8 H3 H8 G2 H7 0.1U_0402_10V6K~D DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VREFCA VREFDQ 2 MEM_VREFA0 M8 H1 X76@ 1 25 DQMA[7..0] R822 R823 R824 R825 R826 2 25 DQSA[7..0] 25 DQSA#[7..0] D 1 DQSA[7..0] 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 ODT/ODT0 CS/CS0 RAS CAS WE B 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 +1.5VSDGPU +1.5VSDGPU 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 2 2 2 2 2 2 2 1 2 4.7U_0603_6.3V6M 2 1 4.7U_0603_6.3V6M C964 2 1 4.7U_0603_6.3V6M C963 2 1 4.7U_0603_6.3V6M C962 2 1 4.7U_0603_6.3V6M C961 2 1 4.7U_0603_6.3V6M C960 2 1 4.7U_0603_6.3V6M C959 2 1 4.7U_0603_6.3V6M C958 2 1 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ A DIS@ Compal Electronics, Inc. Compal Secret Data Security Classification DIS@ DIS@ 2 C956 4.7U_0603_6.3V6M 2 4.7U_0603_6.3V6M C983 2 4.7U_0603_6.3V6M C982 2 4.7U_0603_6.3V6M C981 2 4.7U_0603_6.3V6M C980 2 4.7U_0603_6.3V6M C979 2 4.7U_0603_6.3V6M C978 2 4.7U_0603_6.3V6M C977 2 4.7U_0603_6.3V6M C976 C975 0.1U_0402_16V4Z 0.1U_0402_16V4Z C974 0.1U_0402_16V4Z C973 C972 0.1U_0402_16V4Z 0.1U_0402_16V4Z C971 0.1U_0402_16V4Z C970 0.1U_0402_16V4Z C969 0.1U_0402_16V4Z C968 0.1U_0402_16V4Z C967 C965 1000P_0402_50V7K C966 2 1 2 1 0.1U_0402_16V7K 0.1U_0402_16V7K 2 1 2 1 C955 0.1U_0402_16V7K 2 1 1 1 C954 0.1U_0402_16V7K 2 1 1 1 C953 C953 0.1U_0402_16V7K 2 1 1 1 C952 0.1U_0402_16V7K 0.1U_0402_16V7K 2 1 1 1 C951 0.1U_0402_16V7K 2 1 1 1 C950 1U_0402_6.3V6K 2 1 1 1 C949 C949 1U_0402_6.3V6K 2 1 1 1 C948 1U_0402_6.3V6K 1 1 1 C947 1U_0402_6.3V6K 1U_0402_6.3V6K A 1 C946 +1.5VSDGPU 4.7U_0603_6.3V6M C957 +1.5VSDGPU 2009/5/12 Issued Date Deciphered Date 2010/04/15 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 26 of 56
3 2 DQSC[7..0] 25 DQSC[7..0] CMDC0 CMDC25 CMDC28 CMDC27 CMDC16 DQSC#[7..0] 25 DQSC#[7..0] DQMC[7..0] 25 DQMC[7..0] R841 R842 R843 R844 R847 1 1 1 1 1 MDC[63..0] 25 MDC[63..0] U58 2 2 2 2 2 DQMC[7..0] 25 DQMC[7..0] 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% DQSC#[7..0] 25 DQSC#[7..0] DQSC[7..0] 25 DQSC[7..0] MDC[63..0] 25 MDC[63..0] X76@ U59 U60 RAM BIT SWAP 20091211 60->60 62->58 58->63 63->57 59->56 56->62 57->61 61->59 CMDC[30..0] 25 CMDC[30..0] MODE C PULL DOWN SIGNAL:RST，CKE，ODT CMDC[30..0] 25 CMDC[30..0] DIS@ DIS@ DIS@ DIS@ DIS@ 1 X76@ U60 B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.5VSDGPU A1 A8 C1 C9 D2 E9 F1 H2 H9 CMDC25 CMDC2 CMDC24 CMDC8 CMDC19 K1 L2 J3 K3 L3 F3 C7 VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ VDDQ DQSL VDDQ DQSU VDDQ DQSC0 DQSC3 DQMC2 DQMC1 E7 D3 DML DMU DQSC#2 DQSC#1 G3 B7 DQSL DQSU A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 F3 C7 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ DQSL VDDQ DQSU VDDQ DQMC0 DQMC3 E7 D3 DML DMU DQSC#0 DQSC#3 G3 B7 DQSL DQSU A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 T2 RESET L8 ZQ/ZQ0 RESET L8 ZQ/ZQ0 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 1 2 1 M2 N8 M3 CLKC1 CLKC1# CMDC27 J7 K7 K9 CK CK CKE/CKE0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 E3 F7 F2 F8 H3 H8 G2 H7 MDC44 MDC43 MDC42 MDC47 MDC41 MDC45 MDC40 MDC46 D7 C3 C8 C2 A7 A2 B8 A3 B2 D9 G7 K2 K8 N1 N9 R1 R9 D MDC48 MDC53 MDC51 MDC54 MDC49 MDC55 MDC50 MDC52 VDD VDD VDD VDD VDD VDD VDD VDD VDD BA0 BA1 BA2 +1.5VSDGPU K1 L2 J3 K3 L3 DQSC5 DQSC6 DML DMU DQSC#7 G3 DQSC#4 B7 DQSL DQSU CMDC28 T2 CLKC1# CMDC16 CMDC11 CMDC24 CMDC8 CMDC21 DQMC7 E7 DQMC4 D3 R855 240_0402_1% A1 A8 C1 C9 D2 E9 F1 H2 H9 RESET VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B1 B9 D1 D8 E2 E8 F9 G1 G9 ZQC2 B1 B9 D1 D8 E2 E8 F9 G1 G9 DIS@ ODT/ODT0 CS/CS0 RAS CAS WE L8 ZQ/ZQ0 J1 L1 J9 L9 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 C +1.5VSDGPU DQSC7 F3 DQSC4 C7 1 1 2 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 CMDC12 CMDC14 CMDC30 F3 C7 VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ VDDQ DQSL VDDQ DQSU VDDQ A1 A8 C1 C9 D2 E9 F1 H2 H9 DQMC5 DQMC6 E7 D3 DML DMU DQSC#5 DQSC#6 G3 B7 DQSL DQSU CMDC28 T2 RESET L8 ZQ/ZQ0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 J1 L1 J9 L9 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B1 B9 D1 D8 E2 E8 F9 G1 G9 ZQC3 R859 R859 DIS@ J1 L1 J9 L9 25 CLKC1# DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DIS@ 243_0402_1% B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ DIS@ CLKC0# 2 CLKC1 R854 240_0402_1% DIS@ B2 D9 G7 K2 K8 N1 N9 R1 R9 X76@ VREFCA VREFDQ CMDC22 CMDC4 CMDC20 CMDC9 CMDC6 CMDC17 CMDC3 CMDC26 CMDC1 CMDC5 CMDC19 CMDC10 CMDC7 CMDC29 CMDC18 CMDC13 VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ VDDQ DQSL VDDQ DQSU VDDQ K1 L2 J3 K3 L3 243_0402_1% 243_0402_1% NC/ODT1 NC/CS1 NC/CE1 NCZQ1 DIS@ R853 C987 1K_0402_1% DIS@ 25 CLKC1 MDC35 MDC39 MDC32 MDC36 MDC33 MDC38 MDC34 MDC37 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 CMDC16 CMDC11 CMDC24 CMDC8 CMDC21 MEM_VREFC3 1 R858 J1 L1 J9 L9 2 CLKC0 25 CLKC0 25 CLKC0# R857 DIS@ 2 T2 ZQC1 243_0402_1% 243_0402_1% R856 B 243_0402_1% 1 ZQC0 CMDC28 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS D7 C3 C8 C2 A7 A2 B8 A3 MEM_VREFC3 M8 H1 +1.5VSDGPU 2 CMDC28 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS MDC60 MDC58 MDC63 MDC57 MDC56 MDC62 MDC61 MDC59 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 BA0 BA1 BA2 CLKC1 J7 CLKC1# K7 CMDC27 K9 R851 1K_0402_1% DIS@ MEM_VREFC2 1 DIS@ R852 C986 1K_0402_1% DIS@ 2 E3 F7 F2 F8 H3 H8 G2 H7 +1.5VSDGPU CMDC12 M2 CMDC14 N8 CMDC30 M3 1 R850 1K_0402_1% DIS@ A1 A8 C1 C9 D2 E9 F1 H2 H9 ODT/ODT0 CS/CS0 RAS CAS WE DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 +1.5VSDGPU 2 DQSC2 DQSC1 ODT/ODT0 CS/CS0 RAS CAS WE MEM_VREFC1 1 DIS@ R849 C985 1K_0402_1% DIS@ 2 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D K1 L2 J3 K3 L3 2 0.1U_0402_10V6K~D CMDC25 CMDC2 CMDC24 CMDC8 CMDC19 MEM_VREFC0 1 +1.5VSDGPU +1.5VSDGPU A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 2 CK CK CKE/CKE0 DIS@ R846 C984 1K_0402_1% DIS@ +1.5VSDGPU VDD VDD VDD VDD VDD VDD VDD VDD VDD DIS@ 1 J7 K7 K9 R848 1K_0402_1% CMDC22 N3 CMDC4 P7 CMDC20 P3 CMDC9 N2 CMDC6 P8 CMDC17 P2 CMDC3 R8 CMDC26 R2 CMDC1 T8 CMDC5 R3 CMDC19 L7 CMDC10 R7 CMDC7 N7 CMDC29 T3 CMDC18 T7 CMDC13 M7 U61 VREFCA VREFDQ R845 1K_0402_1% DIS@ 2 CLKC0 CLKC0# CMDC0 MDC29 MDC26 MDC31 MDC25 MDC30 MDC27 MDC28 MDC24 X76@ MEM_VREFC2 M8 H1 +1.5VSDGPU 1 CK CK CKE/CKE0 BA0 BA1 BA2 D7 C3 C8 C2 A7 A2 B8 A3 +1.5VSDGPU 2 J7 K7 K9 M2 N8 M3 MDC3 MDC7 MDC0 MDC5 MDC2 MDC6 MDC1 MDC4 1 CLKC0 CLKC0# CMDC0 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 CMDC12 CMDC9 CMDC13 +1.5VSDGPU N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 E3 F7 F2 F8 H3 H8 G2 H7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 CMDC7 CMDC20 CMDC4 CMDC14 CMDC17 CMDC6 CMDC26 CMDC3 CMDC1 CMDC10 CMDC21 CMDC5 CMDC22 CMDC18 CMDC29 CMDC30 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 2 BA0 BA1 BA2 MDC15 MDC11 MDC13 MDC9 MDC12 MDC8 MDC14 MDC10 VREFCA VREFDQ 1 M2 N8 M3 D7 C3 C8 C2 A7 A2 B8 A3 MEM_VREFC1 M8 H1 0.1U_0402_10V6K~D A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 CMDC12 CMDC9 CMDC13 C N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 MDC22 MDC16 MDC23 MDC19 MDC18 MDC17 MDC20 MDC21 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 CMDC7 CMDC20 CMDC4 CMDC14 CMDC17 CMDC6 CMDC26 CMDC3 CMDC1 CMDC10 CMDC21 CMDC5 CMDC22 CMDC18 CMDC29 CMDC30 E3 F7 F2 F8 H3 H8 G2 H7 0.1U_0402_10V6K~D DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VREFCA VREFDQ 2 MEM_VREFC0 M8 H1 1 D 1 4 2 5 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 ODT/ODT0 CS/CS0 RAS CAS WE B 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 +1.5VSDGPU DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 2 2 DIS@ DIS@ 2 2 2 2 1 2 1 2 1 2 2009/5/12 Issued Date 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ Deciphered Date Compal Electronics, Inc. 2010/04/15 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 A DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ Compal Secret Data Security Classification 1 4.7U_0603_6.3V6M C1024 1 4.7U_0603_6.3V6M C1023 1 4.7U_0603_6.3V6M C1022 1 4.7U_0603_6.3V6M C1021 1 C1017 1 4.7U_0603_6.3V6M 2 1 4.7U_0603_6.3V6M C1025 2 1 4.7U_0603_6.3V6M C1018 2 1 4.7U_0603_6.3V6M 2 1 4.7U_0603_6.3V6M C1006 2 1 4.7U_0603_6.3V6M C1005 2 1 4.7U_0603_6.3V6M C1004 2 1 4.7U_0603_6.3V6M C1003 2 1 4.7U_0603_6.3V6M C1002 1 4.7U_0603_6.3V6M C1001 2 4.7U_0603_6.3V6M C1000 C998 4.7U_0603_6.3V6M C999 0.1U_0402_16V4Z 0.1U_0402_16V4Z C997 0.1U_0402_16V4Z C996 C995 0.1U_0402_16V4Z 0.1U_0402_16V4Z C994 0.1U_0402_16V4Z C993 0.1U_0402_16V4Z C992 0.1U_0402_16V4Z C991 C988 0.1U_0402_16V4Z C990 2 1 0.1U_0402_16V7K 2 1 C1016 0.1U_0402_16V7K 2 1 C1015 0.1U_0402_16V7K 2 1 C1014 C1014 0.1U_0402_16V7K 2 1 C1013 0.1U_0402_16V7K 0.1U_0402_16V7K 2 1 C1012 0.1U_0402_16V7K 2 1 C1011 1U_0402_6.3V6K DIS@ 2 1 C1010 C1010 1U_0402_6.3V6K DIS@ 2 1 C1009 1U_0402_6.3V6K 1U_0402_6.3V6K A 2 1 C1008 1U_0402_6.3V6K 2 1 C1007 1 1000P_0402_50V7K C989 +1.5VSDGPU 4.7U_0603_6.3V6M C1020 +1.5VSDGPU 4.7U_0603_6.3V6M C1019 +1.5VSDGPU 2 Wednesday, June 30, 2010 Sheet 1 27 of 56
5 4 3 2 +3VS C475 SG@ 0.1U_0402_16V4Z 1 2 LCD POWER CIRCUIT 1 1 UMOP@ R351 100K_0402_5% P 2 2 SG@ 2 DGPU_EDIDSEL_R# 1 R366 0_0402_5% 18 DGPU_EDIDSEL# 2 C459 29 DGPU_EDIDSEL_R# 0.1U_0402_16V4Z 1 0_0402_5% P PWMSEL_1# SG@ 2 1 R361 0_0402_5% 17 DGPU_PWMSEL# 2 A G R371 100K_0402_5% 1 2 UMOP@ 2 G 3 OE# A IGPU_SELECT# 16 SG@ 2 1 R365 100K_0402_5% 74AHC1G14GW_SOT3535 D Y IGPU_EDIDSEL# 4 U26 @ @ 1 R364 74AHC1G14GW_SOT3535 2 100K_0402_5% Y IGPU_PWM_SELECT# 4 U22 SG@ 74AHC1G14GW_SOT3535 1 5 P 2 16 DPST_PWM C 091211 ADD R371 Fix CPT 4sec shut down flash issue R417 3 S IGPU_SELECT# 4 +3VS C469 SG@ 0.1U_0402_16V4Z 1 2 2 3 DIS ONLY@ R367 100K_0402_5% Q31 2N7002E-T1-GE3_SOT23-3 DIS ONLY@ A 5 D 2 G UMOP@ 1 1 ENVDD 1 G P 1 2 4.7U_0805_10V4Z 1 Y U27 SG@ 3 AO3413L_SOT23-3 +LCDVDD +5VS 22 ENVDD A +3VS C474 @ 0.1U_0402_16V4Z 1 2 SN74CBTD3306CPWR_TSSOP8 SG@ W=60mils C462 S 2N7002E-T1-GE3_SOT23-3 2 INVTPWM 1 D 1 Q30 0.047U_0402_16V7K 2 Q29 2 G 3 PCH_ENVDD 16 PCH_ENVDD 3 C466 UMOP@ D G 8 3 6 4 5 S 3 2N7002E-T1-GE3_SOT23-3 S 2 1 2 G VCC 1B 2B GND G 2 1 Q28 4.7U_0805_10V4Z 1A 2A 1OE# 2OE# 3 2 2 R353 1K_0402_5% 2 1 D 2 5 1 7 DGPU_SELECT# 16,17,29 DGPU_SELECT# U23 INVT_PWM DPST_PWM_1 PWMSEL_1# IGPU_PWM_SELECT# C463 NC 1 +5VS 1 R357 100K_0402_5% 1 1 W=60mils R349 300_0603_5% NC 5 +3VS +3V NC +LCDVDD D 1 Y 4 DPST_PWM_1 U24 UMOP@ 74AHCT1G125GW_SOT353-5 INVT_PWM 36 INVT_PWM UMOP@ 1 R358 C DIS ONLY@ 1 2 R356 22_0402_5% VGA_PNL_PWM 1 @ R360 2 22_0402_5% 1 22 VGA_PNL_PWM INVTPWM 2 22_0402_5% Reserved for UMA Only and OPTIMUS R355 10K_0402_5% SM010014520 3000ma 220ohm@100mhz DCR 0.04 +INVPWR_B+ 1 2 5 +3VS 2 3 Vp Vn USB20_CMOS_N8 2 SWITCHABLE 2009/8/27 ADD SWITCHABLE C470 68P_0402_50V8J USB20_CMOS_P8 4 CH4 CH1 L CM1293-04SO_SOT23-6 @ B W=60mils JLVDS1 41 42 43 44 45 46 A G1 G2 G3 G4 G5 G6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 +3VS @ 2 1 +LCDVDD R679 0_0603_5% 1 +LCDVDD +3VS INVTPWM DISPOFF# I2CC_SCL I2CC_SDA Place closed to JLVDS1 +LCDVDD +INVPWR_B+ +LVDD_R UMA W=60mils 2 1 C464 0.1U_0402_16V4Z 2 1 C461 10U_0805_10V4Z 2 C458 0.1U_0402_16V4Z DAC_BRIG 36 TXOUT0TXOUT0+ INVTPWM DISPOFF# DISPOFF# 2 2 2 @ 0_0402_5% 2 @ PCH_TXCLK+ PCH_TXCLKPCH_TXOUT2PCH_TXOUT2+ PCH_TXOUT1+ PCH_TXOUT1PCH_TXOUT0PCH_TXOUT0+ PCH_LCD_CLK PCH_LCD_DATA 220P_0402_50V7K 220P_0402_50V7K 220P_0402_50V7K 0_0402_5% 2 1 R363 10K_0402_5% 2 0_0402_5% 2 0B1 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 46 45 41 40 35 34 30 29 25 26 0B2 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 DGPU_EDIDSEL_R# 54 SEL2 NC NC NC 57 1 C467 1 C468 1 C473 TXOUT2TXOUT2+ TXCLKTXCLK+ 48 47 43 42 37 36 32 31 22 23 52 5 51 DAC_BRIG TXOUT1TXOUT1+ VGA_TXCLK+ VGA_TXCLKVGA_TXOUT2VGA_TXOUT2+ VGA_TXOUT1+ VGA_TXOUT1VGA_TXOUT0VGA_TXOUT0+ VGA_LCD_CLK VGA_LCD_DATA Thermal_GND 1 R362 1 R368 LOCAL_DIM 36 1 R369 BKOFF# 36 COLOR_ENG_EN 36 TXOUT0+ TXOUT0- +3VS_SWITCH 1 1 1 VCC VCC VCC VCC VCC VCC VCC 4 10 18 27 38 50 56 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 2 3 7 8 11 12 14 15 19 20 SEL 17 1 6 9 13 16 21 24 28 33 39 44 49 53 55 SG@ SG@ SG@ 2 2 2 1109 RF request +3VS R1 R2 1 IPEX_20143-040E-20F CONN@ 2 1 0_0402_5% 1 0_0402_5% 1 C805 22P_0402_50V8J @ 2 2 2 C806 22P_0402_50V8J @ 0_0402_5% 2 UMOP@1 0_0402_5% 2 UMOP@1 R405 R410 PCH_TXOUT1+ PCH_TXOUT1- TXOUT2+ TXOUT2- 0_0402_5% 2 UMOP@1 0_0402_5% 2 UMOP@1 R401 R399 PCH_TXOUT2+ PCH_TXOUT2- TXCLK+ TXCLK- 0_0402_5% 2 UMOP@1 0_0402_5% 2 UMOP@1 R393 R396 PCH_TXCLK+ PCH_TXCLK- 0_0402_5% 2 UMOP@1 0_0402_5% 2 UMOP@1 R418 R420 PCH_LCD_CLK PCH_LCD_DATA +3VS PCH_TXOUT1+ 16 PCH_TXOUT1- 16 PCH_TXOUT2+ 16 PCH_TXOUT2- 16 PCH_LCD_CLK 16 PCH_LCD_DATA 16 1 UMOP@ 2 4.7K_0402_5% PCH_LCD_DATA Discrete ONLY TXOUT0+ TXOUT0- 0_0402_5% 2 DIS ONLY@ R26 1 0_0402_5% 2 DIS ONLY@ R24 1 VGA_TXOUT0+ VGA_TXOUT0- TXOUT1+ TXOUT1- 0_0402_5% 2 DIS ONLY@ R22 1 0_0402_5% 2 DIS ONLY@ R23 1 VGA_TXOUT1+ VGA_TXOUT1- TXOUT2+ TXOUT2- 0_0402_5% 2 DIS ONLY@ R21 1 0_0402_5% 2 DIS ONLY@ R20 1 VGA_TXOUT2+ VGA_TXOUT2- TXCLK+ TXCLK- 0_0402_5% 2 DIS ONLY@ R18 1 0_0402_5% 2 DIS ONLY@ R19 1 VGA_TXCLK+ VGA_TXCLK- I2CC_SCL I2CC_SDA 0_0402_5% 2 DIS ONLY@ R419 VGA_LCD_CLK 1 0_0402_5% 2 DIS ONLY@ R421 VGA_LCD_DATA 1 VGA_TXOUT0+ 23 VGA_TXOUT0- 23 VGA_TXOUT1+ 23 VGA_TXOUT1- 23 VGA_TXOUT2+ 23 VGA_TXOUT2- 23 VGA_TXCLK+ 23 VGA_TXCLK- 23 A VGA_LCD_CLK 22 VGA_LCD_DATA 22 PI3LVD400ZFE with 2 SEL pin USB20_N8 17 USB20_P8 17 2009/08/01 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 4 B PCH_TXCLK+ 16 PCH_TXCLK- 16 1 UMOP@ 2 4.7K_0402_5% PCH_LCD_CLK R32 Date: 5 PCH_TXOUT0+ 16 PCH_TXOUT0- 16 5/4 PCH_LCD_CLK& PCH_LCD_DATA Pull high 2.2K change to 4.7K R29 PI3LVD400ZFEX_TQFN56_11X5 SG@ USB20_CMOS_N8 USB20_CMOS_P8 PCH_TXOUT0+ PCH_TXOUT0- DGPU_SELECT# GND GND GND GND GND GND GND GND GND GND GND GND GND GND R416 R412 I2CC_SCL I2CC_SDA C63 C54 C66 TXCLK+ TXCLKTXOUT2TXOUT2+ TXOUT1+ TXOUT1TXOUT0TXOUT0+ I2CC_SCL I2CC_SDA 0_0402_5% 2 UMOP@1 0_0402_5% 2 UMOP@1 TXOUT1+ TXOUT1- R15 0_0603_5% SG@ U3 TS3DV520ERHUR with 1 SEL pin LCD/LED PANEL Conn. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 B2 UMA ONLY / Optimus +3VS DIS H SEL1 SEL2 1 B1 0.1U_0402_16V4Z 1 CH2 4.7U_0603_6.3V6K L30 2 1 FBMA-L11-201209-221LMA30T_0805 C471 680P_0402_50V7K CH3 1 6 B+ 2 L31 2 1 FBMA-L11-201209-221LMA30T_0805 0.1U_0402_16V4Z W=60mils 2 D1 3 2 Sheet Wednesday, June 30, 2010 1 28 of 56
A B C D UMA ONLY & OPTIMUS D17 R372 UMOP@ 1 2 D16 +5VS +R_CRT_VCC +CRT_VCC 1 1 1 2 1 1 2 1.1A_6V_SMD1812P110TF 1 C171 0.1U_0402_16V4Z 3 2 3 2 2 W=40mils +3VS 2 1 Change to 0 ohm for CRT EA rising falling time L41 1 1 2 C598 UMOP@ 1 C590 1 UMOP@ 2 2 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J For CRT flicker issue Change C603 C593 C569 Form 12p to 15p 20100617 A OE# P 2 1 L2 2 MBC1608121YZF_0603 2 MBC1608121YZF_0603 C110 3 16 17 C-H_13-12201513CP CONN@ CRT_DET# 18 100P_0402_50V8J CRT_VSYNC_2 1 1 G G CRT_HSYNC_2 C178 10P_0402_50V8J CRT_HSYNC_1 4 1 2 U7 Y 2 1 L1 1 10K_0402_5% 2 2 DSUB_12 2 2 R41 100K_0402_5% @ 1 C164 10P_0402_50V8J DSUB_15 C208 2 68P_0402_50V8J 1 G CRT_HSYNC 1 R67 5 2 0.1U_0402_16V4Z 2 2 C569 1 2 2 C618 UMOP@ CRT_B_2 C593 1 74AHCT1G125GW_SOT353-5 2 1 2 1 C567 +CRT_VCC C194 1 2 FCM2012CF-800T06_2P C603 1 JCRT1 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 CRT_G_2 2 FCM2012CF-800T06_2P L39 1 CRT_B_1 15P_0402_50V8J 1 DIS ONLY@ For CRT flicker issue Change C607 C592 C567 Form 8p to 6p 20100617 2 C592 6P_0402_50V8J DIS ONLY@ 2 2 150_0402_1% 1 DIS ONLY@ C607 150_0402_1% 6P_0402_50V8J R446 6P_0402_50V8J R464 150_0402_1% CRT_G_1 DIS ONLY@ 2 0_0805_5% DIS ONLY@ 1 1 1 1 R377 CRT_R_2 DIS ONLY@ CRT_B 2 FCM2012CF-800T06_2P 15P_0402_50V8J CRT_G L48 1 DIS ONLY@ CRT_R_1 2 0_0805_5% DIS ONLY@ 1 2 R376 0_0805_5% 15P_0402_50V8J 1 R372 DIS ONLY@ CRT_R 2 F1 CH491DPT_SOT23-3 FCM2012CF-800T06_2P R466 D2 C569 1 3 C593 1 2 2 2 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J FCM2012CF-800T06_2P R377 UMOP@ 1 2 1 C603 1 UMOP@ 2 2 2 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J UMOP@ FCM2012CF-800T06_2P R376 UMOP@ 1 2 C567 1 W=40mils D14 BAV99_SOT-23 BAV99_SOT-23 BAV99_SOT-23 UMOP@ C592 1 UMOP@ UMOP@ UMOP@ C607 1 E 2 C126 +CRT_VCC 68P_0402_50V8J +CRT_VCC U5 Y CRT_VSYNC_1 4 D25 BAV99_SOT-23 BAV99_SOT-23 +CRT_VCC +3VS 1 1 3 D33 74AHCT1G125GW_SOT353-5 1 A G 2 1 5 P CRT_VSYNC 1 2 0.1U_0402_16V4Z OE# C111 1 R78 4.7K_0402_5% 2 2 2 3 2 3 G G 2 R48 4.7K_0402_5% +3VS C280 SG@ 0.1U_0402_16V4Z CRT_DDC_CLK 3 DSUB_12 1 Q3 2N7002E-T1-GE3_SOT23-3 DSUB_15 1 3 D 2 2 0.1U_0402_16V4Z 3 S 2 2 0.1U_0402_16V4Z 3 CRT_DDC_DATA +CRT_VCC 1 D 0.1U_0402_16V4Z 1 1 C273 C290 C271 SG@ SG@ SG@ S 1 G 2009/08/27 2 SWITCHABLE Q2 2N7002E-T1-GE3_SOT23-3 20091214 For NV Recommand +3VS U10 4 16 23 29 32 VDD VDD VDD VDD VDD VGA_CRT_R VGA_CRT_G VGA_CRT_B VGA_CRT_HSYNC VGA_CRT_VSYNC VGA_DDC_CLK VGA_DDC_DATA 27 25 22 20 18 12 14 0B1 1B1 2B1 3B1 4B1 5B1 6B1 PCH_CRT_R PCH_CRT_G PCH_CRT_B PCH_CRT_HSYNC PCH_CRT_VSYNC PCH_CRT_CLK PCH_CRT_DATA 26 24 21 19 17 13 15 0B2 1B2 2B2 3B2 4B2 5B2 6B2 4 A0 A1 A2 A3 A4 1 2 5 6 7 SEL1 8 A5 A6 9 10 SEL2 30 CRT_R CRT_G CRT_B CRT_HSYNC CRT_VSYNC DGPU_SELECT# 16,17,28 22 VGA_CRT_R 22 VGA_CRT_G CRT_DDC_CLK CRT_DDC_DATA 22 VGA_CRT_B DGPU_EDIDSEL_R# 28 22 VGA_CRT_HSYNC 22 VGA_CRT_VSYNC GND GND GND GND GPAD 22 VGA_DDC_CLK 3 11 28 31 33 22 VGA_DDC_DATA B1 B2 R537 2 DIS ONLY@ 1 0_0402_5% CRT_R VGA_CRT_G R535 2 DIS ONLY@ 1 0_0402_5% CRT_G VGA_CRT_B R533 2 DIS ONLY@ 1 0_0402_5% CRT_B VGA_CRT_HSYNC R531 2 DIS ONLY@ 1 0_0402_5% CRT_HSYNC VGA_CRT_VSYNC R529 2 DIS ONLY@ 1 0_0402_5% CRT_VSYNC VGA_DDC_CLK R527 2 DIS ONLY@ 1 0_0402_5% CRT_DDC_CLK VGA_DDC_DATA R526 2 DIS ONLY@ 1 0_0402_5% CRT_DDC_DATA 16 PCH_CRT_R 16 PCH_CRT_G 16 PCH_CRT_B 16 PCH_CRT_HSYNC 16 PCH_CRT_VSYNC 16 PCH_CRT_CLK 16 PCH_CRT_DATA PCH_CRT_R R536 2 UMOP@ 1 0_0402_5% CRT_R PCH_CRT_G R534 2 UMOP@ 1 0_0402_5% CRT_G PCH_CRT_B R532 2 UMOP@ 1 0_0402_5% PCH_CRT_HSYNC R530 2 UMOP@ 1 0_0402_5% CRT_HSYNC PCH_CRT_VSYNC R528 2 UMOP@ 1 0_0402_5% CRT_VSYNC PCH_CRT_CLK R544 2 UMOP@ 1 0_0402_5% PCH_CRT_DATA R543 2 UMOP@ 1 0_0402_5% UMA CRT_DDC_CLK CRT_DDC_DATA 4 2009/08/01 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A CRT_B PCH DDC PU 2.2K on Page 17 DIS H VGA_CRT_R VGA_DDC_DATA and VGA_DDC_CLK Pull high at Page22 PI3V712-AZLEX_TQFN32_6X3~D SG@ L UMA only & Optimus Discrete only B C D SCHEMATICS,MB A5893 Document Number Rev C 401869 Sheet Wednesday, June 30, 2010 E 29 of 56
5 4 3 2 1 +3VS +3VS C725 C730 C731 1 C720 1 C721 C409 2 0_0603_5% UMOP@ UMOP@ 2 UMOP@ 2 0.1U_0402_16V4Z 2 UMOP@ 2 0.1U_0402_16V4Z UMOP@ R616 10K_0402_5% UMOP@ W=40mils 1 +HDMI_5V_OUT D21 UMOP@ UMOP@ 2 2 0.1U_0402_16V4Z HDMI connector 1 0.1U_0402_16V4Z 1 +5VS 2 2 F2 1 +HDMI_5V 1 @ CH491DPT_SOT23-3 OE# 2 1.1A_6V_SMD1812P110TF C707 0.1U_0402_16V4Z D 1 Q43 UMOP@ HDMI_HPD 2 G 3 S 100K_0402_5% 2 HDMI_R_D0+ HDMI_R_D1- SCL_SINK 28 HDMI_SCLK R625 1 D23 2 2.2K_0402_5% 1 SDA_SINK VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V CG_0 CG_1 3 4 29 HDMI_SDATA R627 1 2 2.2K_0402_5% 1 REXT 6 2 0_0402_5% D24 HPD_SINK 32 EQ_0 EQ_1 HDMI_R_D1+ HDMI_R_D2- CH751H-40PT_SOD323-2 2 +HDMI_5V_OUT HDMI_R_D2+ 2 34 35 R629 1 UMOP@ 2 2.2K_0402_5% +3VS R637 2.2K_0402_5% 1 UMOP@ 2 R638 2.2K_0402_5% 1 UMOP@ 2 EQ_S0 R635 @ 1 2 2.2K_0402_5% EQ_S1 R666 @ 1 2 2.2K_0402_5% 2 3.3K_0402_5% 1 2 2.2K_0402_5% R219 UMOP@ 1 +3VS R223 UMOP@ 16 SDVO_SDATA 2 2.2K_0402_5% REXT 16 SDVO_SCLK R211 1 @ R209 UMOP@ 1 +3VS CG0 CG1 CG2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 +3VS R228 1 0 0 0 0 0 2db 2db 0 @ 0 -3db -3db (default) -4db 0 0 0 0 R234 @ 1 SDA SDVO_SCLK 9 SCL CG_2 SM070001310 400ma 90ohm@100mhz DCR 0.3 EQ0 EQ1 0 0 1 1 0 1 0 1 Equalization 12dB 9dB 6dB 3dB (default) OUT_D4+ OUT_D4- IN_D4+ IN_D4- 48 47 PCH_TMDS_D2 16 PCH_TMDS_D2# 16 HDMI_TX1+ HDMI_TX1- 16 17 OUT_D3+ OUT_D3- IN_D3+ IN_D3- 45 44 PCH_TMDS_D1 16 PCH_TMDS_D1# 16 HDMI_CLK+ HDMI_CLK- 19 20 OUT_D2+ OUT_D2- IN_D2+ IN_D2- 42 41 PCH_TMDS_CK 16 PCH_TMDS_CK# 16 HDMI_TX0+ HDMI_TX0- 22 23 OUT_D1+ OUT_D1- IN_D1+ IN_D1- 39 38 PCH_TMDS_D0 16 PCH_TMDS_D0# 16 1 5 12 18 24 27 31 36 37 43 GND GND GND GND GND GND GND GND GND GND GND 49 2 10K_0402_5% 2 4 3 @ ASM1442T_QFN48_7X7 R174 1 2 1 L23 WCM-2012-900T_0805 @ 4 23 VGA_HDMI_TXD023 VGA_HDMI_TXD0+ 23 VGA_HDMI_TXC23 VGA_HDMI_TXC+ 3 R183 1 2 1 1 L25 WCM-2012-900T_0805 @ 4 HDMI_TX2+ R190 HDMI_R_D1+ 2 3 HDMI_R_D1- 0_0402_5% 2 HDMI_R_D2+ 2 4 2 3 1 R188 1 HDMI_R_D0- 0_0402_5% 2 1 1 L26 WCM-2012-900T_0805 @ 4 3 0_0402_5% 3 1 HDMI_R_D0+ 2 0_0402_5% 2 4 R182 HDMI_R_CK- 0_0402_5% 2 HDMI_TX1+ C 3 3 2 B 0_0402_5% HDMI_R_D2- C379 C378 DIS ONLY@ 2 DIS ONLY@ 2 1 0.1U_0402_16V7K HDMI_TX2- R613 1 DIS ONLY@590_0402_1% 2 1 0.1U_0402_16V7K HDMI_TX2+ R614 1 DIS ONLY@590_0402_1% 2 C381 C380 DIS ONLY@ 2 DIS ONLY@ 2 1 0.1U_0402_16V7K HDMI_TX1- R611 1 DIS ONLY@590_0402_1% 2 1 0.1U_0402_16V7K HDMI_TX1+ R612 1 DIS ONLY@590_0402_1% 2 C385 C384 DIS ONLY@ 2 DIS ONLY@ 2 1 0.1U_0402_16V7K HDMI_TX0- R607 1 DIS ONLY@590_0402_1% 2 1 0.1U_0402_16V7K HDMI_TX0+ R608 1 DIS ONLY@590_0402_1% 2 C383 C382 DIS ONLY@ 2 DIS ONLY@ 2 1 0.1U_0402_16V7K HDMI_CLK- R609 1 DIS ONLY@590_0402_1% 2 1 0.1U_0402_16V7K HDMI_CLK+ R610 1 DIS ONLY@590_0402_1% 2 1 S S D HDMI_SDATA Q13 DIS ONLY@ 2N7002E-T1-GE3_SOT23-3 Place closed to JHDMI1 1 C803 12P_0402_50V8J 2 @ 1 1 Q42 DIS ONLY@ S 100K_0402_5% 2N7002E-T1-GE3_SOT23-3 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 A Compal Electronics, Inc. Compal Secret Data Security Classification DDC to HDMI CONN R370 S D C804 12P_0402_50V8J 2 @ D 2 G 3 1 2 2 Q12 3 23 VGA_HDMI_SDATA D G A @ 1 22 VGA_HDMI_DET 1 S 23 VGA_HDMI_SCLK +3VSDGPU 2 G 2 1109 RF request HDMI_SCLK DIS ONLY@ 2N7002E-T1-GE3_SOT23-3 3 C Q52 HDMI_HPD 2 1 DIS ONLY@ 2 B R634 150K_0402_5% MMBT3904_G_SOT23-3 DIS ONLY@ E 1 2 R714 1 3 18 DGPU_HPD_INT# 0_0402_5% DIS ONLY@ R715 Q44 10K_0402_5% 2N7002E-T1-GE3_SOT23-3 DIS ONLY@ SG@ 2 G Pull high at VGA side 3 1 +3VSDGPU 4 HDMI_R_CK+ 2 0_0402_5% 2 R168 1 HDMI_TX2- 23 VGA_HDMI_TXD123 VGA_HDMI_TXD1+ 1 HDMI_TX0- UMOP@ 23 VGA_HDMI_TXD223 VGA_HDMI_TXD2+ +3VSDGPU 2 HDMI_TX1- 20091216 For ASMEDIA AOC Panel Bug ASM1442 PN: SA00003GT00 R177 1 HDMI_TX0+ CG_2 13 14 0_0402_5% 2 1 HDMI_CLK- HDMI_TX2+ HDMI_TX2- HPD_SOURCE R180 1 1 L24 WCM-2012-900T_0805 @ 4 10 2 10K_0402_5% 1 UMOP@ 2 R230 0_0402_5% 16 PCH_DPB_HPD HPD# 8 2 2.2K_0402_5% 2 2.2K_0402_5% Swing Pre-amp Slew-rate 450 420 450 460 340 400 400 420 7 SDVO_SDATA D 20 21 22 23 +3VS 2.2K_0402_5% 1 2 R718 UMOP@ 1 2.2K_0402_5% 1 2 R719 R235 UMOP@ HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ SUYIN_100042MR019S153ZL CONN@ CH751H-40PT_SOD323-2 HDMI_HPD 30 CG_0 CG_1 HPD_SOURCE B @ 1 R618 OE# HDMI_CLK+ Connection to 3.4K external resistor. C HDMI_R_CK+ HDMI_R_D0- 25 DDC_EN 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% HDMI_R_CK- 0.1U_0402_16V4Z OE# 2 11 15 21 26 33 40 46 @ 1 2 1 @ 2 1 UMOP@ 2 1 UMOP@ 2 C410 2 U45 R269 R253 R273 R252 1 R256 2N7002E-T1-GE3_SOT23-3 +3VS 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HDMI_SDATA HDMI_SCLK D 0.1U_0402_16V4Z 2 +3VS JHDMI1 HDMI_HPD +HDMI_5V_OUT 1 C727 1 2 0.1U_0402_16V4Z R590 1 1 1 0.1U_0402_16V4Z 1 3 2 Wednesday, June 30, 2010 Sheet 1 30 of 56
5 4 3 2 1 D D SATA HDD1 Conn. CL 4.0 mm JHDD1 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 C753 1 C751 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K 13 SATA_DTX_C_PRX_N0 13 SATA_DTX_C_PRX_P0 SATA_DTX_C_PRX_N0 SATA_DTX_C_PRX_P0 C749 1 C747 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K 1 2 3 4 5 6 7 SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0 SATA_DTX_PRX_N0 SATA_DTX_PRX_P0 13 SATA_PTX_DRX_P0 13 SATA_PTX_DRX_N0 +3VS 1 2 +5VS R669 1 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 +3VS C745 0.1U_0402_16V4Z 2 0_0805_5% +5VS_HDD1 100mils 10U_0805_10V4Z C735 1 0.1U_0402_16V4Z 1 C734 1 C733 1 C732 C 2 2 2 GND A+ AGND BB+ GND V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12 24 23 GND GND C 2 1U_0402_6.3V4Z SANTA_192301-1 CONN@ 1000P_0402_50V7K SATA ODD Conn. JODD1 B SATA_PTX_C_DRX_P1 SATA_PTX_C_DRX_N1 C680 1 C678 1 13 SATA_DTX_C_PRX_N1 13 SATA_DTX_C_PRX_P1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_DTX_PRX_N1 SATA_DTX_PRX_P1 R516 1 +5VS R105 1 @ 2 1K_0402_1% +5VS_ODD 2 0_0805_5% 80mils 10U_0805_10V4Z C642 Place caps. near ODD CONN. 1 2 1 2 3 4 5 6 7 GND A+ AGND BB+ GND 8 9 10 11 12 13 C687 1 C685 1 13 SATA_PTX_DRX_P1 13 SATA_PTX_DRX_N1 DP +5V +5V MD GND GND B GND GND GND GND 17 16 15 14 0.1U_0402_16V4Z C654 1 C653 2 1 C643 2 1U_0402_6.3V4Z OCTEK_SLS-13SB1G_RV CONN@ 1 2 1000P_0402_50V7K A A 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Sheet Wednesday, June 30, 2010 1 31 of 56
5 4 3 2 1 +3V_LAN +3VALW R599 1 2 60mil 0_1206_5% 1 D BIASVDDH VDDC VDDC VDDC XTALVDDH 14 2 6 15 41 AVDDH 30 AVDDH D +LAN_BIASVDDH 36 1 AVDDL AVDDL AVDDL +LAN_AVDDH SPROM_CLK (EECLK) 38 LAN_MIDI3+ TRD2_N 35 LAN_MIDI2- TRD2_P 34 LAN_MIDI2+ TRD1_N 31 LAN_MIDI1- TRD1_P 32 LAN_MIDI1+ TRD0_N 29 LAN_MIDI0- TRD0_P 24 37 TRD3_P +LAN_GPHYPLLVDDL TRD3_N LAN_MIDI3- 28 LAN_MIDI0+ LAN_MIDI3+ 33 LAN_MIDI2- 33 1 0 AT24C02 LAN_MIDI3- 33 SPROM_DOUT (EEDATA) On chip 1 1 +3V_LAN LAN_MIDI2+ 33 C322 1 GPHY_PLLVDDL +LAN_PCIEPLLVDD 18 PCIE_PLLVDDL 21 PCIE_PLLVDDL LAN_MIDI1- 33 R195 1K_0402_1% @ LAN_MIDI1+ 33 LAN_MIDI0- 33 LAN_MIDI0+ 33 2 0.1U_0402_16V7K 14 PCIE_PTX_C_DRX_P1 14 PCIE_PTX_C_DRX_N1 R592 1 R589 1 R587 1 15,34 PCH_PCIE_WAKE# 36 EC_PME# +3V_LAN @ R597 1 5,17,21,36 PLT_RST# 17 16 22 23 LAN_PME# 4 LAN_RESET# 2 20 19 2 0_0402_5% 2 0_0402_5% 2 4.7K_0402_5% 48 SPD100LED# 47 SPD1000LED# 46 TRAFFICLED# PCIE_TXD_P PCIE_TXD_N PCIE_RXD_P PCIE_RXD_N WAKE# REST# PCIE_REFCLK_P PCIE_REFCLK_N 45 2 R595 0_0402_5% 1 2 R594 0_0402_5% 1 LAN_LINK# 33 VCC WP SCL SDA A0 A1 NC GND 1 2 3 4 C AT24C02_SO8 R196 1K_0402_1% R194 1K_0402_1% @ 1 PCIE_DTX_PRX_P1 PCIE_DTX_PRX_N1 U12 @ 8 7 6 5 1 LINKLED# 0.1U_0402_16V7K 1 2 C699 1 2 C700 14 PCIE_DTX_C_PRX_P1 14 PCIE_DTX_C_PRX_N1 R193 1K_0402_1% SPROM_CLK SPROM_DOUT C 2 0.1U_0402_16V4Z @ 2 +LAN_AVDDL 27 33 39 +LAN_XTALVDDH 1 C493 2 1 VDDC 25 2 2 C492 42 1 2 2 +3V_LAN 1000P_0402_50V7K 2 1 C705 1000P_0402_50V7K 1 C701 C333 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 1 C697 0.1U_0402_16V4Z 4.7U_0603_6.3V6K 091211 EMI add 1000P C715 4.7U_0603_6.3V6K 2 2 0.1U_0402_16V4Z U39 +1.2V_LAN 1 C716 LAN_ACTIVITY# 33 SM010005500 500ma 600ohm@100mhz DCR 0.38 20mil L22 +LAN_XTALVDDH C301 1 2 BLM18AG601SN1D_2P 1 +3V_LAN 0.1U_0402_16V4Z 2 0_0402_5% MODE 20mil 5 2 L64 +LAN_BIASVDDH 14 CLK_PCIE_LAN 14 CLK_PCIE_LAN# C703 1 2 BLM18AG601SN1D_2P 1 0.1U_0402_16V4Z EEDATA R175 1 2 1K_0402_5% 40 R596 1 +3VS 2 10K_0402_5% 1 43 44 20mil SPROM_DOUT EECLK SPROM_CLK L66 VMAIN_PRSINT C712 LOW_PWR 40mil B SR_LX LAN_XTALO_R 13 XTALO LAN_XTALI 12 11 SR_VFB 0.1U_0402_16V4Z L65 +1.2V_LAN_OUT 1 2 4.7UH_PG031B-4R7MS_1.1A_20% XTALI 8 1 LAN_RDAC 26 SR_VDDP 2 C710 10U_0805_10V4Z SR_VDD 14 LAN_CLKREQ# 3 10 9 C318 1 2 2 +1.2V_LAN C695 4.7U_0603_6.3V6K L62 1 2 BLM18AG601SN1D_2P +LAN_GPHYPLLVDDL 7 C698 0.1U_0402_16V4Z 1 1 2 2 1 1 2 2 +1.2V_LAN C696 4.7U_0603_6.3V6K 49 BCM57780A0KMLG_QFN48_7X7 1 20mil PAD NC 1 C311 2 2 4.7U_0603_6.3V6K 0.1U_0402_16V4Z CLKREQ# 0.1U_0402_16V4Z L63 1 2 BLM18AG601SN1D_2P +LAN_PCIEPLLVDD +3V_LAN 1 2 B 0.1U_0402_16V4Z RDAC 2 1 2 BLM18AG601SN1D_2P SM010005500 500ma 600ohm@100mhz DCR 0.38 C302 2 C706 1 20mil 1 2 C708 0.1U_0402_16V4Z 1.24K_0402_1% 1 +1.2V_LAN R575 1 2 +LAN_AVDDH 20mil L21 1 2 BLM18AG601SN1D_2P +LAN_AVDDL LAN_XTALI C709 LAN_XTALO_R 0.1U_0402_16V4Z 4.7U_0603_6.3V6K A 1 A +1.2V_LAN C312 2 R571 200_0402_1% Y3 1 1 2 2 LAN_XTALO 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 1 25MHZ_20PF_7A25000012 C704 C702 27P_0402_50V8J 27P_0402_50V8J 2 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 Rev C 401869 4 3 2 Sheet Wednesday, June 30, 2010 1 32 of 56
5 4 3 2 1 LAN Connector D D T16 TCT1 TD1+ TD1- MCT1 MX1+ MX1- 24 23 22 RJ45_MIDI0+ RJ45_MIDI0- 32 LAN_MIDI1+ 32 LAN_MIDI1- LAN_MIDI1+ LAN_MIDI1- 4 5 6 TCT2 TD2+ TD2- MCT2 MX2+ MX2- 21 20 19 RJ45_MIDI1+ RJ45_MIDI1- 32 LAN_MIDI2+ 32 LAN_MIDI2- LAN_MIDI2+ LAN_MIDI2- 7 8 9 TCT3 TD3+ TD3- MCT3 MX3+ MX3- 18 17 16 RJ45_MIDI2+ RJ45_MIDI2- 32 LAN_MIDI3+ 32 LAN_MIDI3- LAN_MIDI3+ LAN_MIDI3- 10 11 12 TCT4 TD4+ TD4- MCT4 MX4+ MX4- 15 14 13 RJ45_MIDI3+ RJ45_MIDI3- 2 R518 +3V_LAN 1 1K_0402_5% 220P_0402_50V7K C663 LAN_ACTIVITY# LAN_LINK# 1 2 C656 68P_0402_50V8J @ 2 1 JRJ45 Green LED+ Green LED- 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z +3V_LAN 2 R140 40mil 1 1K_0402_5% PR3+ 5 PR3- 6 PR2- 7 PR4+ 8 PR4- C Yellow LED+ 12 LAN_ACTIVITY# 32 LAN_ACTIVITY# Yellow LED- 68P_0402_50V8J 2 2 @ 14 13 SHLD1 SHLD2 11 1 220P_0402_50V7K C297 BOTHHAND: S X'FORM_ GST5009-D LF LAN, SP050006B00 TIMAG:S X'FORM_ IH-160 LAN , SP050006F00 PR2+ 4 RJ45_MIDI3RJ45_GND Place close to TCT pin 3 RJ45_MIDI3+ R522 75_0402_1% PR1- RJ45_MIDI1- 1 1 R525 75_0402_1% 2 RJ45_MIDI2- 1 C690 R541 75_0402_1% 2 0.1U_0402_16V4Z R549 75_0402_1% 1 0.1U_0402_16V4Z 2 2 C686 1 1 C681 1 PR1+ RJ45_MIDI0- 2 2 C671 1 1 RJ45_MIDI1+ 2 1 2 C RJ45_MIDI0+ RJ45_MIDI2+ 350UH_IH-037-2 D22 PJDLC05C_SOT23-3 @ 9 10 LAN_LINK# 32 LAN_LINK# 2 LAN_MIDI0+ LAN_MIDI0- 3 32 LAN_MIDI0+ 32 LAN_MIDI0- 1 2 3 SANTA_130451-K CONN@ 1 C292 RJ45_GND 1 LANGND 1 2 C661 1000P_1206_2KV7K 1 C660 2 2 40mil C659 4.7U_0603_6.3V6K 0.1U_0402_16V4Z B B A A Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 33 of 56
A 2 R302 +3VS B 1 0_1206_5% C D E For Wireless LAN +3VS_WLAN 60mil +3VS_WLAN 1 2 1 +1.5VS 1 C440 4.7U_0805_10V4Z 2 1 C423 0.1U_0402_16V4Z 2 +3VS_WLAN 1 C452 4.7U_0805_10V4Z 2 1 C441 0.1U_0402_16V4Z 2 1 C434 0.1U_0402_16V4Z 2 C442 Mini Card Power Rating 0.1U_0402_16V4Z Power Primary Power (mA) Auxiliary Power (mA) Peak +3VS @ 2 0_0402_5% (WLAN_BT_DATA) (WLAN_BT_CLK) 14 CLK_PCIE_MINI1# 14 CLK_PCIE_MINI1 14 PCIE_DTX_C_PRX_N2 14 PCIE_DTX_C_PRX_P2 14 PCIE_PTX_C_DRX_N2 14 PCIE_PTX_C_DRX_P2 +3VS_WLAN 2 R280 1 E51TXD_P80DATA1_R E51RXD_P80CLK 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 18 20 22 24 26 28 30 32 34 36 38 40 42 (WWAN_LED#) 44 (WLAN_LED#) 46 48 50 52 +1.5VS WL_OFF# PLT_RST_BUF# R303 1 R299 1 @ 750 330 250 250 (wake enable) +1.5VS +3VS_WLAN 500 375 1 5 (Not wake enable) Normal WL_OFF# 36 PLT_RST_BUF# 17 +3VS +3V 2 0_0603_5% 2 0_0603_5% 0_0402_5% MINI1_SMBCLK R292 1 @ 2 @ MINI1_SMBDATA 1 2 R288 0_0402_5% PCH_SMBCLK 12,14,21 PCH_SMBDATA 12,14,21 USB20_N12 17 USB20_P12 17 R291 1 2 0_0402_5% MINI1_LED# 36 2 (9~16mA) R285 100K_0402_5% 53 54 55 56 2 G1 G2 G3 G3 36 E51TXD_P80DATA 36 E51RXD_P80CLK 0_0402_5% 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 14 MINI1_CLKREQ# 1 3 5 7 9 11 13 15 1 R323 1 1000 +3V JMINI1 PCH_PCIE_WAKE# 15,32 PCH_PCIE_WAKE# Normal ACES_88910-5204 CONN@ 4 mm High +3VS_WLAN +3VS_WWAN 1 2 C460 3G@ 0.1U_0402_16V4Z For 3G / GPS +3VS_WWAN To 3G Module Connect (Port 9) +3VS_WWAN Peak: 2.75A Normal: 1.1A 1 3G@ R352 1 2 3 4 5 6 7 8 9 10 GND GND 2 0_1206_5% 1 C465 @ 150U_B2_6.3VM_R35M 1 + 2 1 C801 3G@ 2 2 C173 3G@ 10U_0603_6.3V6M 47P_0402_50V8J Close to WWAN CONN +3VS_WWAN R350 100K_0402_5% JP4 1 2 3 4 5 6 7 8 9 10 11 12 1 +3VS 3 LS-5895 2 3 WWAN_OFF# WWAN_OFF# 36 WWAN_LED# 36 USB20_N13 17 USB20_P13 17 USB20_N10 17 USB20_P10 17 ACES_87036-1001-CP CONN@ 1109 RF request 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: A B C D Wednesday, June 30, 2010 Sheet E 34 of 56
A B C D E +3V +5VALW +USB_VCCB U46 U17 C424 1 R250 100K_0402_5% 8 7 6 5 GND VOUT VIN VOUT VIN VOUT EN FLG 2 1 2 3 4 1 2 R251 10K_0402_5% RT9715BGS_SO8 4.7U_0805_10V4Z 2 1 1 2 3 4 C736 USB_OC#2 17 1 2 1 GND VOUT VIN VOUT VIN VOUT EN FLG 8 7 6 5 R681 100K_0402_5% 2 +USB_VCCA 1 +5VALW 1 +3V 1 2 R680 10K_0402_5% RT9715BGS_SO8 USB_OC#0 17 1 4.7U_0805_10V4Z 2 C408 2 0.1U_0402_16V4Z C744 1 0.1U_0402_16V4Z SYSON# SYSON# 42 SYSON# 2009/08/14 CHANGE cap D26 6 CH3 CH2 3 USB20_N1_1 +USB_VCCA W=100mils USB/B Conn. LS-5891 +USB_VCCA (Port 0,2) 1 5 +USB_VCCA Vp Vn 2 1 + C726 2 220U_6.3V_M_R17 USB20_P1_1 4 CH4 CH1 1 C728 2009/08/25 Update Footprint(follow NAL00) 2 470P_0402_50V7K CM1293-04SO_SOT23-6 R667 1 2 0_0402_5% 1 2 3 4 5 6 7 8 9 10 11 12 USB Conn. (Port 1) JUSB1 USB20_N1 17 USB20_N1 L68 1 1 2 2 USB20_N1_1 USB20_P1_1 2 USB20_P1 17 USB20_P1 4 4 3 3 @ WCM-2012-900T_0805 1 2 R668 0_0402_5% 1 2 3 4 5 6 7 8 +USB_VCCB JUSB2 VBUS DD+ GND GND GND GND GND 13 14 GND GND W=100mils 1 2 3 4 5 6 7 8 9 10 11 12 USB20_N0 USB20_P0 USB20_N2 USB20_P2 USB20_N0 17 USB20_P0 17 USB20_N2 17 USB20_P2 17 2 ACES_85201-1205N CONN@ SUYIN_020133GB004M51PZR CONN@ 3 3 36 BT_ON# +3VS GND GND 8 7 6 5 4 3 2 1 C445 4.7U_0805_10V4Z 1 2 10 9 8 7 6 5 4 3 2 1 BT_ON# 5IN1_LED# 37 USB20_N9 USB20_P9 1 1 BT@ 2 R706 10K_0402_5% C788 BT@ 0.1U_0402_16V4Z 1 S 2 G D 2 (Port 11) 10 2 Q51 BT@ AO3413L_SOT23-3 W=40mils +BT_VCC 1 C796 BT@ 4.7U_0805_10V4Z USB20_N9 17 USB20_P9 17 BT Conn. C790 BT@ 1U_0603_10V4Z 1 LS-5896 2 3 C789 BT@ 0.1U_0402_16V4Z +3VS 1 Card Reader Conn. +3VALW 1 C795 BT@ R713 300_0603_5% BT@ 2 0.1U_0402_16V4Z 1 S 2 G 4 2008/08/10 Issued Date Deciphered Date 8 7 6 5 4 3 2 1 USB20_P11 17 USB20_N11 17 (WLAN_BT_DATA) (WLAN_BT_CLK) ACES_87213-0800G CONN@ BT Wire Cable Note: Pin 3, Pin 4 NC Q50 2N7002E-T1-GE3_SOT23-3 BT@ 4 Compal Electronics, Inc. Compal Secret Data Security Classification GND 8 7 6 5 4 3 2 GND 1 D 3 JCR1 ACES_85201-08051 CONN@ 9 +BT_VCC JBT1 2 2009/08/24 CHANGE Conn to FFC Type 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: A B C D Wednesday, June 30, 2010 Sheet E 35 of 56
4 3 2 1 SM010015410 300ma 80ohm@100mhz DCR 0.3 PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D 18 EC_SCI# 15 PM_CLKRUN# +3VALW C 1 R392 1 R395 1 R422 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 77 78 79 80 SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 PM_SLP_S3# PM_SLP_S5# EC_SMI# EC_ACIN MINI1_LED# LOCAL_DIM COLOR_ENG_EN INVT_PWM FAN_SPEED1 BT_ON# E51TXD_P80DATA E51RXD_P80CLK ON/OFF PWR_SUSP_LED WLAN_LED# 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 2 LID_SW# 100K_0402_5% 1 R374 1 R373 2 KSO1 47K_0402_5% 2 KSO2 47K_0402_5% 1 R426 @ 2 EC_PME# 10K_0402_5% 44 44 14,22 14,22 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 R400 2 R402 1 2 100K_0402_5% EC_SMB_CK2 1 2.2K_0402_5% EC_SMB_DA2 1 2.2K_0402_5% 38 ON/OFF 37 PWR_SUSP_LED 37 WLAN_LED# 2 GFX_CORE_PWRGD 10K_0402_5% 1 E51TXD_P80DATA R508 15 SUSCLK @ 1 R740 2 0_0402_5% EC_CRY1 EC_CRY2 1 R509 2 100K_0402_5% 1 COLOR_ENG_EN R511 PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F 83 84 85 86 87 88 EC_MUTE# GFX_CORE_PWRGD WWAN_LED# VGA_idle TP_CLK TP_DATA 122 123 DAC_BRIG 28 EN_DFAN1 41 IREF 46 CALIBRATE# 46 EC_MUTE# 40 GFX_CORE_PWRGD 52 WWAN_LED# 34 VGA_idle 22 TP_CLK 37 TP_DATA 37 3S/4S# 65W/90W# SBPWR_EN LID_SW# SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS# 119 120 126 128 EC_SI_SPI_SO EC_SO_SPI_SI EC_SPICLK EC_SPICS#/FSEL# CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 73 74 89 90 91 92 93 95 121 127 WWAN_OFF# PCH_TEMP_ALERT# FSTCHG BATT_GRN_LED# 3G_LED# BATT_AMB_LED# PWR_LED SYSON VR_ON ACIN EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 100 101 102 103 104 105 106 107 108 EC_RSMRST# EC_LID_OUT# EC_ON EC_SWI# EC_PWROK BKOFF# WL_OFF# PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 110 112 114 115 116 117 118 V18R 124 SPI Flash ROM 2 R404 TP_DATA 2 R408 65W/90W# C496 VGA_idle GPIO SM Bus GPI 2 R423 2 R424 2 R428 DIS@ EC_SI_SPI_SO 37 EC_SO_SPI_SI 37 EC_SPICLK 37 EC_SPICS#/FSEL# 37 C +3VALW 1 100K_0402_5% 1 100K_0402_5% 1 100K_0402_5% +3VALW WWAN_OFF# 34 PCH_TEMP_ALERT# 18,21 FSTCHG 46 (CAPS_LED#) BATT_GRN_LED# 37 3G_LED# 37 BATT_AMB_LED# 37 PWR_LED 37 SYSON 42,49 VR_ON 38,53 ACIN 37,42,43 EC_RSMRST# 15 EC_LID_OUT# 14 EC_ON 38 EC_SWI# 15 EC_PWROK 15,38 BKOFF# 28 WL_OFF# 34 R394 100K_0402_5% Ra EC_PROJECTID 2 C511 0.1U_0402_16V4Z @ B Project ID definition, Please see page 3. EC_CRY1 PM_SLP_S4# 15 ENBKL 16 EAPD 39 SUS_PWR_DN_ACK SUSP# 38,42,46,48 PBTN_OUT# 5,15,21 EC_PME# 32 ENBKL EAPD SUS_PWR_DN_ACK SUSP# PBTN_OUT# EC_PME# 1 R397 0_0402_5% Rb C536 KB926QFD3_LQFP128_14X14 1 4.7K_0402_5% 1 4.7K_0402_5% PCH_TEMP_ALERT# Pull high at Page 18 (PCH side) @ For Low PWR Pannel use 15P_0402_50V8J EC_CRY2 1 1 2 X1 15 2 C537 15P_0402_50V8J 32.768KHZ_12.5PF_Q13MC14610002 1 2 C539 C490 BATT_TEMP 2 C489 BATT_OVP 2 C534 ACIN 2 4.7U_0805_10V4Z 20mil L33 ECAGND 2 1 FBMA-L11-160808-800LMT_0603 ENBKL 1 R425 2 100K_0402_5% 100P_0402_50V8J 1 100P_0402_50V8J 1 100P_0402_50V8J 1 A SM010015410 300ma 80ohm@100mhz DCR 0.3 Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Issued Date Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 1 2 0.1U_0402_16V4Z TP_CLK 3S/4S# 46 65W/90W# 46 SBPWR_EN 42 LID_SW# 37 SPI Device Interface XCLK1 XCLK0 <BOM Structure> AD_BID0 R382 33K_0402_1% Rb 97 98 99 109 SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0 PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A LOCAL_DIM 2 100K_0402_5% A (NUM_LED#) DAC_BRIG EN_DFAN1 IREF CALIBRATE# R389 100K_0402_5% Ra BATT_TEMP 44 BATT_OVP 46 ADP_I 46 3S/4S# GND GND GND GND GND R398 2 DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F 68 70 71 72 PS2 Interface 11 24 35 94 113 +3VS BATT_TEMP BATT_OVP ADP_I AD_BID0 EC_PROJECTID +5VS B 15 PM_SLP_S3# 15 PM_SLP_S5# 18 EC_SMI# 15 EC_ACIN 34 MINI1_LED# 28 LOCAL_DIM 28 COLOR_ENG_EN 28 INVT_PWM 41 FAN_SPEED1 35 BT_ON# 63 64 65 66 75 76 DA Output KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 2 EC_SMB_CK1 2.2K_0402_5% 2 EC_SMB_DA1 2.2K_0402_5% BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 Board ID definition, Please see page 3. 4 0.1U_0402_16V4Z ACOFF 1 1 AD +3VALW BEEP# 39 ME_OVERRIDE 13 ACOFF 46,47 ECAGND 2 1 C491 0.01U_0402_16V7K OSC 12 13 37 20 38 PWM Output ACES_85205-0400 @ BEEP# OSC 2 5,17,21,32 PLT_RST# 21 23 26 27 NC C487 1 47K_0402_5% INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 4 D E51RXD_P80CLK E51TXD_P80DATA NC R375 2 1 2 3 4 3 EC_RST# EC_SCI# 17 CLK_PCI_LPC +3VALW Place on MiniCard +3VALW 1 2 3 4 2 1 47_0402_5% GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC E51RXD_P80CLK 34 E51TXD_P80DATA 34 JP5 AGND R403 2 1 2 3 4 5 7 8 10 69 C516 22P_0402_50V8J 2 1 EC_GA20 EC_KBRST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 Place on RAM door E51RXD_P80CLK E51TXD_P80DATA ACES_85205-0400 @ AVCC VCC VCC VCC VCC VCC VCC 1109 RF request 18 EC_GA20 18 EC_KBRST# 13 SERIRQ 13 LPC_FRAME# 13 LPC_AD3 13 LPC_AD2 13 LPC_AD1 13 LPC_AD0 0.1U_0402_16V4Z 67 9 22 33 96 111 125 D 2 1 2 3 4 1 2 3 4 C505 1000P_0402_50V7K U32 +3VALW JP6 KSO[0..17] 37 2 1 1 1000P_0402_50V7K KSO[0..17] 1 1 2 2 0.1U_0402_16V4Z C488 2 2 2 0.1U_0402_16V4Z +3VALW_EC 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 2 C519 C533 C538 C524 C512 KSI[0..7] 37 1 1 For EC Tools KSI[0..7] 20mil 2 2 L32 FBMA-L11-160808-800LMT_0603 1 2 +EC_VCCA ECAGND 1 R385 0_0805_5% 40mil 2 +3VALW 1 5 3 2 SCHEMATICS,MB A5893 Document Number Rev C 401869 Wednesday, June 30, 2010 Sheet 1 36 of 56
1 R391 +3VALW 2 0_0603_5% 1 C506 2 0.1U_0402_16V4Z To TP/B Conn. 20mil +5VS 150mils 36 EC_SPICS#/FSEL# JTP1 U31 R406 4.7K_0402_5% 1 2 SPI_WP# 1 2 SPI_HOLD# R390 4.7K_0402_5% +3VALW 1 3 7 4 CE# WP# HOLD# VSS VDD SCK SI SO +SPI_VCC 8 6 5 2 EC_SPICLK 36 EC_SO_SPI_SI 36 EC_SI_SPI_SO 36 (Right) C682 @ 2 2 100P_0402_50V8J 100P_0402_50V8J INT_KBD Conn. 28 27 @ C497 TP_CLK LEFT_BTN# TP_DATA RIGHT_BTN# KSI[0..7] 36 KSO[0..17] +5VS KSO[0..17] 36 1 D19 PJDLC05C_SOT23-3 3 2 KSI[0..7] 3 2 33P_0402_50V8K D18 PJDLC05C_SOT23-3 C684 0.1U_0402_16V4Z LS-5893+LS-5894(Lid Board) LED/B RIGHT (90) LED/B LEFT (70) 1 2 3 4 5 6 7 8 9 10 GND GND ACES_88747-2601 CONN@ 2 100P_0402_50V8J 1 2 100P_0402_50V8J KSO15 C34 1 2 100P_0402_50V8J KSO7 C26 1 2 100P_0402_50V8J KSO14 C33 1 2 100P_0402_50V8J KSO6 C25 1 2 C32 1 2 100P_0402_50V8J KSO5 C24 1 2 C31 1 2 100P_0402_50V8J KSO4 C23 1 2 C37 1 2 100P_0402_50V8J KSO3 C22 1 2 C30 1 2 100P_0402_50V8J KSI4 C41 1 2 C29 1 2 100P_0402_50V8J KSO2 C21 1 2 C38 1 2 100P_0402_50V8J KSO1 C20 1 2 C39 1 2 100P_0402_50V8J KSO0 C19 1 2 100P_0402_50V8J KSO9 C28 1 2 100P_0402_50V8J KSI5 C42 1 2 100P_0402_50V8J KSI3 C40 1 2 100P_0402_50V8J KSI6 C43 1 2 100P_0402_50V8J KSO8 C27 1 2 100P_0402_50V8J KSI7 C44 1 2 +3VS 100P_0402_50V8J KSI2 2 100P_0402_50V8J KSI1 PWR_LED# ON/OFFBTN# 4 100P_0402_50V8J KSO10 ON/OFFBTN# 38 2 +3VALW 100P_0402_50V8J KSO11 +3VS LID_SW# ACIN_LED# 3G_LED# WLAN_LED# MEDIA_LED# 100P_0402_50V8J KSI0 3G_LED# 36 WLAN_LED# 36 1 2 3 4 5 6 7 8 9 10 11 12 100P_0402_50V8J KSO12 1 2 3 4 5 6 7 8 9 10 GND GND 100P_0402_50V8J KSO13 PWR_LED# ON/OFFBTN# +3VALW LID_SW# 36 SW3 SMT1-05-A_4P 1 100P_0402_50V8J ACES_85201-1005N CONN@ ACES_85201-1005N CONN@ +3VS +3VS 2 1 C36 LID_SW# ACIN_LED# 3G_LED# WLAN_LED# MEDIA_LED# 3 RIGHT_BTN# Q4A R272 @ 100K_0402_5% 1 C35 KSO17 4 JLED2 1 2 3 4 5 6 7 8 9 10 11 12 SW2 SMT1-05-A_4P 1 2 KSO16 3 LEFT_BTN# 5 6 JLED1 1 2 1 KSO0 G2 KSO1 G1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 1 C683 @ 5 6 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 1 (Left) TP_CLK 36 TP_DATA 36 LEFT_BTN# RIGHT_BTN# ACES_85201-0605N CONN@ @ R386 0_0402_5% JKB1 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 7 8 2 MX25L1005AMC-12G_SOP8 Reserved for BIOS simulator. Footprint SO8 1 2 3 4 5 6 1 2 3 4 5 6 GND GND 6 1 MEDIA_LED# 3 4 LED Status Power/SUS ON SUS Battery BlueTooth 3G/WLAN Full Charge 3G Blue Amber ACIN WLAN Blue Amber +3VS NEW70/80/90 Blue Amber ACIN_LED# B 1 1 2 2 2.2K_0402_5% PWR_LED# 2 91@ 1 R343 680_0402_5% D 3 LED3 1 71@ R343 PCH_SATALED# 13 2N7002DWH_SOT363-6 5 Q4B +3VS 5IN1_LED# 35 2N7002DWH_SOT363-6 S Q53 @ 2 G 36,42,43 ACIN HT-191NB5_BLUE 2N7002E-T1-GE3_SOT23-3 LED1 +3VALW 1 71@ R344 2 2 3.9K_0402_5% A 1 PWR_SUSP_LED# 2 91@ 1 R344 680_0402_5% HT-191UD5_AMBER 3 PWR_SUSP_LED# 6 PWR_LED# LED4 Q26A BATT_GRN_LED# BATT_GRN_LED# 36 2 91@ 1 R341 680_0402_5% 2 36 PWR_LED 2N7002DWH_SOT363-6 HT-191NB5_BLUE R340 100K_0402_5% Q26B 2N7002DWH_SOT363-6 5 36 PWR_SUSP_LED R335 100K_0402_5% 4 1 2 B 1 2 2 2.2K_0402_5% 2 1 71@ R341 1 71@ R342 2 2 3.9K_0402_5% A 1 BATT_AMB_LED# BATT_AMB_LED# 36 1 LED2 1 +3VALW 2 91@ 1 R342 680_0402_5% HT-191UD5_AMBER Bom option For 71 and 91 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: SCHEMATICS,MB A5893 Document Number Rev C 401869 Wednesday, June 30, 2010 Sheet 37 of 56
A B C D E Power Button ON/OFF switch 2 +3VALW 1 1 R409 37 ON/OFFBTN# 100K_0402_5% 1 TOP Side SW1 SMT1-05-A_4P 1 3 4 51ON# 3 @ EC_ON R413 Bottom Side S Q32 2N7002E-T1-GE3_SOT23-3 10K_0402_5% 1 SW4 SMT1-05-A_4P 1 3 4 6 5 @ D 2 G 2 36 EC_ON 2 51ON# 43 D12 CHN202UPT_SC70-3 1 6 5 ON/OFF 36 1 3 2 2 ON/OFFBTN# 2 2 Test Only Power ON Circuit +3VS +3VALW 1 +3VALW 14 For South Bridge P O 3 I O 4 7 G I 2 U21B SN74LVC14APWLE_TSSOP14 SYS_PWROK_1 1 R332 @ 2 0_0402_5% EC_PWROK 15,36 7 CH751H-40PT_SOD323-2 @ C455 1U_0603_10V6K @ 2 G 1 2 U21A SN74LVC14APWLE_TSSOP14 P 2 1 36,53 VR_ON 14 R331 180K_0402_5% D7 1 3 3 +3VS +3VALW 1 +3VALW Q25 C456 0.1U_0402_16V7K 2N7002E-T1-GE3_SOT23-3 S 14 P P U21D SN74LVC14APWLE_TSSOP14 6 9 I O 8 G O G I 1 R320 2 0_0402_5% VS_ON 51 For VTT 7 42,48 SUSP 5 2 D 2 G 3 SUSP U21C SN74LVC14APWLE_TSSOP14 7 1 36,42,46,48 SUSP# 2 R334 249K_0402_1% SUSP# 1 2 14 R333 10K_0402_1% @ 1 SUSP# 1 R321 @ 2 0_0402_5% +3VS +3VALW 1 3 2N7002E-T1-GE3_SOT23-3 S C447 DIS@ 1U_0603_10V6K 1 14 P 10 13 I O G O G I U21F SN74LVC14APWLE_TSSOP14 12 1 R317 DIS@ 2 0_0402_5% VGA_ON 24,42,50 4 7 Q23 DIS@ 2 G 42 DGPU_PWR_EN# 2 U21E SN74LVC14APWLE_TSSOP14 P 2 11 D 2 0.1U_0402_16V4Z 7 1 14,18,21,42 DGPU_PWR_EN 4 14 R319 31.6K_0402_1% @ R318 10K_0402_1% 1 DIS@ 2 +3VALW C448 1 DGPU_PWR_EN 1 R316 @ 2 0_0402_5% 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D SCHEMATICS,MB A5893 Document Number Rev C 401869 Sheet Wednesday, June 30, 2010 E 38 of 56
5 4 3 2 1 +5VAMP 1 R339 1 R704 SHDN 4 BYP 1 2 C439 0.01U_0402_16V7K @ (output = 300 mA) C780 1 36 BEEP# 2 1U_0402_6.3V4Z C785 1 13 PCH_SPKR 2 1U_0402_6.3V4Z 1 R699 C 2 2 B E 560_0402_5% 1 R701 1 C773 1 1U_0402_6.3V4Z Q49 D MONO_IN 2 GND 1 R694 1 R670 560_0402_5% AVDD1 Place near Codec 2 1 U48 C760 2 1K_0402_1% 1 C775 1 2 C776 1 INT_MIC 2 0.1U_0402_16V4Z LINE2_L LOUT1_L 35 AMP_LEFT LINE2_R LOUT_R 36 AMP_RIGHT MIC2_C_L 16 4.7U_0603_6.3V6K MIC2_C_R 17 4.7U_0603_6.3V6K 23 MIC2_L LOUT2_L LOUT2_R 40 MIC1_R MIC1_L C777 1 MIC1_R C778 1 LINE1_L SPDIFO2 45 LINE1_R DMIC_CLK1/2 46 LINE1_VREFO NC 43 20 40 MIC1_L LINE2_VREFO DMIC_CLK3/4 44 19 MIC2_VREFO MIC1_C_L 21 4.7U_0603_6.3V6K MIC1_C_R 22 2 4.7U_0603_6.3V6K MONO_IN 12 2 BITCLK 8 11 10 13 HDA_SYNC_AUDIO 5 13 HDA_SDOUT_AUDIO 40 MIC_PLUG# 40 HP_PLUG# R695 2 R685 2 36 EAPD 1 20K_0402_1% 1 5.11K_0402_1% MIC1_R MONO_OUT 1 R672 2 0_0402_5% 29 CPVEE MIC1_VREFO 28 HPOUT_R 32 CBN SDATA_OUT 47 EAPD 4 7 1 R687 2 33_0402_5% 13 HDA_SDIN0 13 30 SYNC SPDIFO1 HDA_SDIN0_AUDIO 31 RESET# GPIO0/DMIC_DATA1/2 GPIO1/DMIC_DATA3/4 SENSE A SENSE B 48 For EMI HDA_BITCLK_AUDIO 37 CBP PCBEEP_IN 2 3 13 34 SENSE_A SENSE_B 2 C752 22P_0402_50V8J 2 1 0_0402_5% 6 SDATA_IN 1 R686 MIC1_L B 13 HDA_RST_AUDIO# 272@amp AMP_RIGHT 40 41 18 MIC2_VREFO AMP_LEFT 40 39 MIC2_R 24 Internal MIC REF 272@ C B C754 2.2U_0402_6.3V6M 10mil MIC1_VREFO HP_RIGHT VREF 27 40 HPOUT_L AVSS1 AVSS2 1 C758 2 10mil R673 1 33 HP_RIGHT 40 CODEC_VREF JDREF External MIC REF 272@ 26 42 DVSS1 DVSS2 HP_LEFT 2 20K_0402_1% C764 1 C765 1 MIC2_VREFO 2.2U_0402_6.3V6M 2 0.1U_0402_16V4Z 2 10U_0805_10V4Z Int. MIC Place next pin27 HP_LEFT 40 For EMI 15mil JP1 1 2 1 2 G1 G2 1 R702 2 +3VS C746 10U_0805_10V4Z 2 15 INT_MIC_R L71 1 2 MBK1608121YZF_0603 1 C748 14 External MIC SM010032020 600ma 120ohm@100mhz DCR 0.25 +3VS_DVDD 1 GNDA 9 2 0.1U_0402_16V4Z DVDD 2 DVDD_IO 2 1 38 C 0.1U_0402_16V4Z C772 25 C738 10U_0805_10V4Z 1 AVDD2 +VDDA 2 0_0805_5% GND Place near Codec 10mil 2 0_0805_5% 1 R707 2 +AVDD_HDA 40mil 0.1U_0402_16V4Z 1 1 C739 2 0_0805_5% 1 R308 2SC2411K_SOT23-3 2 HD Audio Codec L70 1 2 FBMA-L11-160808-800LMT_0603 GNDA 2 2.4K_0402_1% D31 CH751H-40PT_SOD323-2 SM010015410 300ma 80ohm@100mhz DCR 0.3 2 0_0805_5% 2 1U_0402_6.3V4Z R696 10K_0402_5% 10K_0402_5% G9191-475T1U_SOT23-5 @ 2 0_0805_5% 1 R283 2 D32 CH751H-40PT_SOD323-2 1 4.75V +VDDA C783 R703 2.2K_0402_5% 15mil INT_MIC_L INT_MIC_R 2 FBMA-L11-160808-700LMT_2P 3 4 L29 1 1 ALC272X-GR_LQFP48_7X7 ACES_88266-02001 CONN@ C786 220P_0402_50V7K 3 AGND 2 2 DGND 2 3 0.1U_0402_16V4Z 5 OUT 2 2 GND 1 2 D IN 2 C438 40mil 3 1 C444 1 2 1 U19 60mil 0.1U_0402_16V4Z 2 L28 1 2 FBMA-L11-201209-221LMA30T_0805 @ L27 1 2 FBMA-L11-201209-221LMA30T_0805 1 +5VAMP +5VS R698 10K_0402_5% +3VS SM010014520 3000ma 220ohm@100mhz DCR 0.04 2 0_0805_5% 1 R329 1 2 0_0805_5% 1 1 R298 D10 PJDLC05C_SOT23-3 SM010004010 300ma 70ohm@100mhz DCR 0.3 A 1 A 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Sheet Wednesday, June 30, 2010 1 39 of 56
A B Ri 90k 70k 45k 25k 0.1U_0402_16V4Z 1 10 dB C457 2 VDD PVDD1 PVDD2 R710 100K_0402_5% 39 AMP_LEFT C791 1 2 1 0.47U_0603_10V7K R712 9 AMP_C_LEFT 2 0_0603_5% 5 EC_MUTE# 19 2 18 SPKR+ ROUT- 14 SPKR- 4 SPKL+ 8 SPKL- RIN- @ R711 100K_0402_5% R708 100K_0402_5% LIN+ LIN- NC 12 BYPASS 10 SHUTDOWN Keep 10 mil width 2 GND5 GND1 GND2 GND3 GND4 36 EC_MUTE# 1 GAIN1 ROUT+ 2 1 GAIN0 3 LOUT- 2 0.47U_0603_10V7K 2 2 C793 1 AMP_C_RIGHT 17 2 0_0603_5% RIN+ 2 1 R697 7 GAIN0 LOUT+ C779 2 0.47U_0603_10V7K 2 0.47U_0603_10V7K @ R709 100K_0402_5% 1 GAIN1 1 +5VAMP 2 1 C453 10U_0805_10V4Z 1 39 AMP_RIGHT E 1 1 U50 C792 1 D +5VAMP 16 15 6 GAIN0 GAIN1 AV(inv) 0 0 6dB 0 1 10dB 1 0 15.6dB 1 1 21.6dB C C794 0.47U_0603_10V7K 21 20 13 11 1 1 2 2 TPA6017A2PWPR_TSSOP20 C787 330P_0402_50V7K 39 HP_LEFT R705 1 2 56.2_0603_1% HPOUT_L_1 39 HP_RIGHT R700 1 2 56.2_0603_1% HPOUT_R_1 1 L78 1 L77 2 1 2 (Use NAL00 PCB Footprint) C784 330P_0402_50V7K 1 Headphone Out JHP1 1 2 2 HPOUT_L_2 FBMA-L11-160808-700LMT_2P 2 HPOUT_R_2 FBMA-L11-160808-700LMT_2P 3 4 SM010004010 300ma 70ohm@100mhz DCR 0.3 39 HP_PLUG# HP_PLUG# 5 3 3 6 MIC1_VREFO SINGA_2SJ-0960-C01 CONN@ 1 2 3 Headphone Out D30 PJDLC05C_SOT23-3 1 1 D29 CH751H-40PT_SOD323-2 1 D27 CH751H-40PT_SOD323-2 Int. Speaker Conn. HP_PLUG# 2 2 MIC_PLUG# Left Side 1 2 R676 4.7K_0402_5% R688 D11 PJDLC05C_SOT23-3 @ G1 G2 39 MIC1_L ACES_88266-02001 CONN@ 39 MIC1_R MIC1_L_1 2 1K_0603_1% MIC1_R_1 2 1K_0603_1% R689 1 R674 1 1 Right Side 1 2 MIC1_R_R 1 C743 220P_0402_50V7K JMIC1 MIC1_L_R L73 1 2 FBMA-L11-160808-700LMT_2P L72 1 2 FBMA-L11-160808-700LMT_2P SM010004010 300ma 70ohm@100mhz DCR 0.3 MIC JACK 4.7K_0402_5% 3 2 3 4 3 2 2 20mil 1 2 1 SPK_L+ SPK_L- 2 0_0603_5% 2 0_0603_5% 2 R354 1 R359 1 2 1 2 3 JSPK2 SPKL+ SPKL- 4 D28 C759 PJDLC05C_SOT23-3 220P_0402_50V7K 39 MIC_PLUG# MIC_PLUG# JSPK1 SPK_R+ SPK_R- 1 2 6 1 2 4 SINGA_2SJ-A960-C01 CONN@ 3 2 0_0603_5% 2 0_0603_5% 2 SPKR+ R348 1 SPKR- R347 1 1 4 5 D9 PJDLC05C_SOT23-3 @ 3 4 G1 G2 ACES_88266-02001 CONN@ 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: A B C D Sheet Wednesday, June 30, 2010 E 40 of 56
@ H16 H_3P0 @ H22 H_3P0 @ 1 @ H3 H_3P0 1 @ H5 H_3P0 1 @ H1 H_3P0 1 @ H2 H_3P0 1 @ H20 H_3P0 1 @ H21 H_3P0 1 @ H17 H_3P0 1 1 1 @ H6 H_3P0 1 H15 H_3P0 1 H10 H_3P0 GNDA H11 H_3P0 H14 H_4P2 H13 H_4P2 H8 H_4P2 @ 1 1 +5VS 10U_0805_10V4Z 2 @ @ @ 1 C542 1 @ 1 +5VS 1 1 FAN1 Conn H9 H_4P2 @ @ C562 1000P_0402_50V7K H7 H_3P0N @ @ JFAN1 1 2 3 FD4 ACES_85205-03001 CONN@ FD2 @ FIDUCIAL_C40M80 2 @ FIDUCIAL_C40M80 FD3 @ FIDUCIAL_C40M80 @ FIDUCIAL_C40M80 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date FD1 1 36 FAN_SPEED1 H19 H_3P0X3P5N 1 40mil +VCC_FAN1 @ 1 H18 H_3P4 C563 1000P_0402_50V7K 1 2 R445 10K_0402_5% 1 @ 1 +3VS H4 H_4P0 1 2 @ BAS16_SOT23-3 C568 10U_0805_10V4Z 1 2 1 1 APL5607KI-TRG_SO8 C570 0.1U_0402_16V4Z 1 2 H12 H_4P0 D15 1 1 2 +VCC_FAN1 1 300_0402_5% D13 1SS355_SOD323-2 @ 8 7 6 5 1 2 R461 GND GND GND GND 2 36 EN_DFAN1 EN VIN VOUT VSET 1 U35 1 2 3 4 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: SCHEMATICS,MB A5893 Document Number Rev C 401869 Wednesday, June 30, 2010 Sheet 41 of 56
C D E +3VALW TO +3V(PCH AUX Power) C1029 1 2 Q47B 20mil @ 1 0.1U_0603_25V7K Q16A SBPWR_EN# 2 SBPWR_EN# DIS@ @ VGA_ON# 5 2N7002DWH_SOT363-6 2 C421 @ 0.1U_0603_25V7K 2 2 5 1 S 2 G R345 100K_0402_5% 2 2 510K_0402_5% 2009/08/17 add VGA_ON# Q38 @ S 2N7002E-T1-GE3_SOT23-3 1 1 24,38,50 VGA_ON R231 DIS@ 22K_0402_5% 1 3 3 2N7002E-T1-GE3_SOT23-3 2N7002E-T1-GE3_SOT23-3 Q36 2 G SUSP S 2N7002E-T1-GE3_SOT23-3 Q37 @ 2 G SYSON# D S Q15 DIS@ 2 G 2N7002E-T1-GE3_SOT23-3 S 2N7002E-T1-GE3_SOT23-3 2009/08/14 CP_S3PowerReduction WhitePaper_Rev0.9 0.75VS speed up discharge 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A 2N7002E-T1-GE3_SOT23-3 4 2 SUSP Q24 DIS@ 3 2 G S VGA_ON# VGA_ON# 1 1 1 Q33 3 SUSP S R232 100K_0402_5% DIS@ 3 1 3 2 D 2 G D 1 D 1 D 2 G 2 R325 100K_0402_5% DIS@ +5VALW R569 470_0603_5% @ 1 R524 470_0603_5% 2 R427 470_0603_5% ACIN D 2 G 14,18,21,38 DGPU_PWR_EN C711 DIS@ 0.1U_0603_25V7K 1 +1.5V 2 2 1 +1.8VS 1 Q1 @ S 2N7002E-T1-GE3_SOT23-3 1 VGA_ON# R30 100K_0402_5% @ 2 1 R584 @ 2 5 D 3 2 G DGPU_PWR_EN# 38 DGPU_PWR_EN# 1 Q40A DIS@ 2 SBPWR_EN# 36 SBPWR_EN 3 1 1 20 SBPWR_EN# 4 1.5VSDGPU_GATE 1 2 1 R586 510K_0402_5% DIS@ VGA_ON# 2 Q40B 2N7002DWH_SOT363-6 DIS@ 6 1 3 Q10 @ S 2N7002E-T1-GE3_SOT23-3 R593 470_0603_5% DIS@ R326 100K_0402_5% DIS@ 2 20mil D 2 G 2 2 1U_0603_10V4Z 10U_0805_10V4Z +5VALW R31 100K_0402_5% @ 3 0.1U_0603_25V7K SI4856ADY_SO8 DIS@ C713 DIS@ 1 1 2 10U_0805_10V4Z +VSB +1.05VS_VTT S 1 2 DIS@ C717 DIS@ 1 1 SUSP 1 2 3 4 2 5 1 S S S G 1 C714 D D D D 3 1 2 C346 +5VALW U40 1 2 1 D Q11 3 R338 10K_0402_5% +1.5VSDGPU 8 7 6 5 2N7002DWH_SOT363-6 4 5 36,38,46,48 SUSP# Q34 @ 2N7002E-T1-GE3_SOT23-3 +1.5V 3 6 @ ACIN R200 22_0603_5% 1 6 VGA_ON# +1.5V to +1.5VSDGPU for GPU R181 470_0603_5% 4 1.5VS_GATE 2 Q9A 2N7002DWH_SOT363-6 +0.75VS 2 Q27B 2N7002DWH_SOT363-6 2N7002DWH_SOT363-6 D 3 1 Q9B 2N7002DWH_SOT363-6 510K_0402_5% 10mil R185 36,37,43 ACIN 2 510K_0402_5% 1 C338 2 1 10U_0805_10V4Z 2 2 1U_0603_10V4Z 4 C389 C328 2 SUSP C650 DIS@ 0.1U_0603_25V7K SUSP 38,48 SUSP Q27A SYSON +1.5VS U13 SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5 2 1 R184 105K_0402_1% +VSB 20mil 2 1 Q35A @ DIS@ 2N7002DWH_SOT363-6 1 2 1 Q35B 2N7002DWH_SOT363-6 DIS@ 1.8VSDGPU_GATE R472 1 2 C374 10U_0805_10V4Z C587 10U_0805_10V4Z C588 0.1U_0402_16V4Z 0.1U_0402_16V4Z 3 2 1 SYSON# 35 SYSON# 36,49 SYSON 10mil 2 1 R505 510K_0402_5% DIS@ +1.5V to +1.5VS 1 2 2 2 1U_0603_10V4Z 10U_0805_10V4Z R346 100K_0402_5% 1 +VSB ACIN 1 R337 100K_0402_5% R502 470_0603_5% DIS@ 1 20mil SUSP 2N7002DWH_SOT363-6 +1.5V 1 1 5 Q22B VGA_ON# 1211 EMI ADD 0.1U close PJ5 C664 DIS@ 3 DIS@ 2 10U_0805_10V4Z 1 2 0.1U_0603_25V7K C648 DIS@ 2 2 2 C450 C670 1 +5VALW 4 1 +5VALW 1 R315 470_0603_5% 4 2 1 3VS_GATE Q22A SUSP C446 1 10mil Q59 @ S 2N7002E-T1-GE3_SOT23-3 2 2 1 R322 200K_0402_5% +VSB 1 10U_0805_10V4Z 2 2 1U_0603_10V4Z 6 20mil U37 DIS@ SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5 6 C451 10U_0805_10V4Z 2 2 10U_0805_10V4Z 2 +1.8VS to +1.8VSDGPU for GPU +1.8VSDGPU 2N7002DWH_SOT363-6 4 3 1 C454 1 4 1 C449 C1030 DIS@ 0.1U_0603_25V7K +1.8VS +3VS U20 SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5 VGA_ON# D 2 G 1 +3VALW TO +3VS 2 2 510K_0402_5% ACIN 2N7002DWH_SOT363-6 +3VALW R867 @ Q16B 2N7002DWH_SOT363-6 1 2N7002DWH_SOT363-6 Q58B DIS@ 1 2 2 +1.05VSDGPU_GATE 2 1 Q58A 2N7002DWH_SOT363-6 DIS@ 3 Q47A 2 5 @ 3V_GATE 1 200K_0402_5% SUSP 1 10K_0402_5% 10mil R255 2 +VSB 2N7002DWH_SOT363-6 C756 10mil R866 4 6 SUSP 4 5 1 20mil +VSB 5VS_GATE 6 10mil 2 1 R684 200K_0402_5% +VSB 4 20mil R865 470_0603_5% DIS@ 2 10U_0805_10V4Z R226 @ 470_0603_5% 10U_0805_10V4Z 2 2 1U_0603_10V4Z 1 + @ C1027 2 330U_D2_2V_Y 1U_0603_10V4Z 2 1 C392 DIS@ C1028 DIS@ 6 1 C393 4A 1 4 40mil +1.05VSDGPU 1 10U_0805_10V4Z +3V 4 1 C407 2 2 +1.05VS_VTT U63 DIS@ SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5 1 1 R692 470_0603_5% 10U_0805_10V4Z 2 2 1U_0603_10V4Z 1 4 C767 1 @ JUMP_43X79 U14 @ SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5 2 C761 1 1 10U_0805_10V4Z 2 2 10U_0805_10V4Z 1 1 3 1 C766 +5VS U49 SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5 4 1 C763 J5 2 +5VALW +1.05VS_VTT to +1.05VSDGPU for GPU Short J5 for PCH VCCSUS3.3 +3VALW 3 1 +5VALW TO +5VS 1 2 B 3 A B C D SCHEMATICS,MB A5893 Document Number Rev C 401869 Sheet Wednesday, June 30, 2010 E 42 of 56
A B C D VIN 1 VIN VIN VS PR296 10K_0402_5% PR297 84.5K_0402_1% 2 1 2 PC210 0.1U_0603_25V7K 2 1 2 PR303 10K_0402_1% 1 2 1 2 2 8 P 3 - O PU18A LM393DG_SO8 PD1 GLZ4.3B_LL34-2 2 PR302 10K_0402_1% + G 1 1 36,37,42 ACIN PR298 22K_0402_5% 1 2 4 1 PC209 1000P_0402_50V7K PR299 10K_0402_5% 1 2 1 PC207 100P_0402_50V8J 46,47 PACIN 2 1 1 PC206 1000P_0402_50V7K PC208 100P_0402_50V8J 2 2 ACES_50305-00441-001 2 1 2 2DC_IN_S2 1 DC_IN_S1 1 2 3 4 GND GND 1 PL24 SMB3025500YA_2P 1 PJP1 PR295 1M_0402_1% 1 2 PR301 20K_0402_1% 1 PC211 1000P_0402_50V7K RTCVREF Vin Dectector 2 Min. H-->L 16.976V L-->H 17.430V Typ 17.525V 17.901V 2 Max. 17.728V 18.384V VIN 2 PJ6 +3VALWP PD2 LL4148_LL34-2 1 1 +3VALW PJ2 +VGFX_COREP PR304 68_1206_5% 2 2 1 38 51ON# 1 +1.5VP VS 1 1 2 PJ11 +VSBP PC213 0.1U_0603_25V7K 2 2 1 1 +VSB JUMP_43X39 2 +1.8VSP 2 2 +1.5V 1 GND PC214 10U_0805_10V4Z +1.8VS 1 +1.05VS_VTT PJ15 PC215 1U_0805_25V4Z - PBJ1 2 ML1220T13RE <BOM Structure> 2 1 1 2 1 1 +VGA_CORE JUMP_43X118 PJ16 2 2 1 1 +0.75VS JUMP_43X39 + 1 2 2 +VGA_COREP 2 +0.75VSP 1 1 JUMP_43X118 PJ17 N2 2 4 1 2 JUMP_43X118 PJ10 2 2 1 1 JUMP_43X118 1 IN 2 1 OUT 1 3 2 1 PR309 200_0603_5% PU14 G920AT24U_SOT89-3 3.3V 2 1 PJ9 RTCVREF +CHGRTC 2 JUMP_43X118 +1.05VS_VTTP PR311 560_0603_5% 1 2 3 JUMP_43X118 PJ7 2 2 1 1 PJ14 PR310 560_0603_5% 1 2 +VGFX_CORE 2 2 PR308 22K_0402_1% 1 2 1 PJ5 1 PC212 0.22U_0603_25V7K 2 PR307 100K_0402_1% 1 JUMP_43X118 +5VALW 1 3 +5VALWP 2 JUMP_43X118 2 N1 PJ8 PR305 68_1206_5% 2 JUMP_43X118 PJ4 2 2 1 1 1 PQ42 TP0610K-T1-E3_SOT23-3 PR306 200_0603_5% CHGRTCP 1 2 1 1 BATT+ 2 JUMP_43X118 2 3 PD3 LL4148_LL34-2 2 1 2 4 JUMP_43X118 +RTCBATT +RTCBATT Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: A B C Wednesday, June 30, 2010 D Sheet 43 of 56
A EC_SMCA TH PI D PH1 under CPU botten side : CPU thermal protection at 92 degree C 2 EC_SMDA C 1 PR542 100_0402_1% 1 2 1 10 9 8 7 6 5 4 3 2 1 GND GND 8 7 6 5 4 3 2 1 B PJP2 SUYIN_200275GR008G13GZR PR543 100_0402_1% VL EC_SMB_DA1 36 1 <40,41> VMB VL GND RHYST1 8 7 3 OT1 TMSNS2 6 OT2 RHYST2 5 G718TM1U_SOT23-8 1 @ PR551 @PR551 47K_0402_1% 1 2 4 2 PR549 9.53K_0402_1% 2 VCC TMSNS1 2 PR550 1K_0402_1% @ PR547 @PR547 100K_0402_1% 2 1 1 PR546 21K_0402_1% 1 PU30 +3VALWP 1 PR545 10K_0402_1% PH1 100K_0402_1%_NCP15WF104F03RC 1 PC380 0.01U_0402_25V7K 2 PC381 0.1U_0603_25V7K PR548 6.49K_0402_1% 2 1 2 1 PR544 1K_0402_5% 1 PC379 1000P_0402_50V7K 2 2 1 2 BATT_S1 EC_SMB_CK1 36 1 <40,41> BATT+ PL44 SMB3025500YA_2P 1 2 2 1 CONN@ 2 BATT_TEMP 36 1 MAINPWON 18,45,47 2 2 2 @ PH2 @PH2 100K_0402_1%_NCP15WF104F03RC +VSBP 2 2 1 1 PC222 0.1U_0603_25V7K 3 3 2 2 PR327 22K_0402_1% 1 2 VL 2 PR325 100K_0402_1% 3 1 1 B+ PC221 0.22U_0603_25V7K PQ44 TP0610K-T1-E3_SOT23-3 PC224 1U_0402_6.3V6K PQ45 2 G D S 2N7002W-T/R7_SOT323-3 2 1 45 SPOK PR330 1K_0402_5% 2 1 1 3 1 PR329 100K_0402_1% 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: A B C Wednesday, June 30, 2010 D Sheet 44 of 56
5 4 3 1 ISL6237_B+ ISL6237_B+ B+ HG5 VBST2 VBST1 17 BST5A 1 0_0603_5% VOUT2 DRVL1 LG5 PGND 22 VOUT1 10 FB1 32 16 18 11 1 2 PC236 0.1U_0603_25V7K REFIN2 1 FB5 20 VSW 9 5V_SKIP EN_LDO PGOOD1 13 TRIP1 12 ILM1 TRIP2 31 ILIM2 GND EN2 TONSE EN1 VREF3 14 21 2 5 PC241 1U_0603_10V6K 2 13/5V_NC VL SPOK 44 RT8206BGQW QFN 32P PR344 402K_0402_1% 2 1 2 1 PR345 267K_0402_1% For +5VALWP Power Budget=8.8A, Ipeak=7A, I max=4.9A Fsw=375KHz by RT8206 setting. ∆I=2.09A, 1/2∆I=1.05A 5uA*PR344=10*Iocpmin*18mΩ*1.2 =>PR344=397KΩ~402KΩ B 13/5V_TON 5uA*402K=10*ILIMTmin*18mΩ*1.2 ILIMTmin=9.305A 5uA*402K=10*ILIMTmax*15mΩ*1.1 ILMIT=12.181A Iocp=10.355A~13.231A For +3VALWP Power Budget=5.98A, Ipeak=5.98A, Imax=4.2A Iocpmin=5.98*1.2=7.2A Fsw=300KHz, ∆I=1.933A, 1/2∆I=0.966A 5uA*PR345=10*Iocpmin*Rdsonmax 5uA*PR345=10*5.7A*18mΩ PR345=266.76K~267K PR350 0_0402_5% 2VREF_ISL6237 2VREF_ISL6237 1 PR347 0_0402_5% 1 TP0610K-T1-E3_SOT23-3 2 2 PC243 @ 0.047U_0402_16V7K 2 1 1 2 PQ50 3 080414:PQ23 ,Del @ 28 2 2 @ 2 2 PR349 PR349 47K_0402_5% 1 1 @ PR346 @PR346 0_0402_5% PC242 0.047U_0402_16V7K 18,44,47 MAINPWON PR348 0_0402_5% 2 1 PGOOD2 27 PD8 1SS355_SOD323-2 PR561 806K_0603_1% NC 2 1 @ PR340 @PR340 0_0402_5% 1 2 PR341 0_0402_5% 2 2 3/5V_EN1 PC240 0.22U_0603_25V7K 1 1 B 4 29 1 VS PR343 200K_0402_5% 1 2 VL EN_LDO C LDOREFIN SKIPSEL PR342 100K_0402_1% 2 PC237 220U_6.3VM_R15 VREF2 8 1 PC238 680P_0603_50V7K + 2 PR339 0_0402_5% 1 2 30 VL EN_LDO-1 1 1 DRVL2 FB3 LL1 LL2 2 23 3 2 1 25 LG3 SW5 PC239 0.22U_0603_25V7K PD7 RLZ5.1B_LL34 1 2 PR336 4.7_1206_5% 2BST5A-1 PR334 1 SW3 2VREF_ISL6237 VS PQ49 AO4712_SO8 @ PR337 61.9K_0402_1% 1 2 15 2 DRVH1 +5VALWP PL27 4.7UH_SIL104R-4R7PF_5.7A_30% 2 1 1 3 2 1 DRVH2 5 6 7 8 7 3 6 19 D PQ47 AO4466_SO8 4 2 2 1 PC232 1U_0603_10V6K 1 2 V5DRV PC234 0.1U_0603_25V7K PR338 @ 10K_0402_1% C 4 2 2 1 4 LDO 24 V5FILT 2 BST3A PR333 1 2 3 PC235 680P_0603_50V7K 26 8 7 6 5 1 UG3 BST3A-1 1 PQ48 0_0603_5% AO4712_SO8 13V_SNB 2 2 2 TP VIN PU16 PR332 4.7_1206_5% PR335 0_0402_5% 1 + PC231 4.7U_0603_6.3V6K 2 1 3/5V_VIN 2 1 PC229 0.1U_0603_25V7K 33 1 PC230 1U_0603_10V6K 3/5V_VCC 1 2 8 7 6 5 PQ46 AO4466_SO8 4 PL28 4.7UH_SIL104R-4R7PF_5.7A_30% 1 2 +3VALWP 5 6 7 8 VL 1 2 3 JUMP_43X118 D PC228 2200P_0402_50V7K 2 1 1 PC226 2200P_0402_50V7K 2 1 1 PC225 10U_1206_25V6M 2 1 2 PC227 10U_1206_25V6M 2 1 PR331 0_0805_5% 1 2 PJ19 2 PC233 220U_6.3VM_R15 2 5uA*267KΩ=10*ILIMTmin*18mΩ ILIMTmin=7.42A 5uA*267KΩ=10*ILIMTmax*15mΩ ILIMTmax=8.9A Iocp=8.39A~9.86A A A 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 45 of 56
A B Iada=0~4.74A(90W/19V=4.736A) Iada=0~3.42A(90W/19V=3.421A) P2 P3 PQ52 AO4407A_SO8 B+ CHG_B+ B+ PR351 0.02_2512_1% PQ53 AO4407A_SO8 PJ18 3 EN CSON 22 CELLS CSOP 21 ICOMP CSIN 20 VCOMP CSIP 19 ICM PHASE 18 8 VREF UGATE 17 CHLIM BOOT 16 ACLIM VDDP 15 D GND PGND 13 PC247 2200P_0402_25V7K 2 1 4 2 PC246 0.1U_0603_25V7K 2 1 1 3 2 1 PR376 4.7_0603_5% PC265 4.7U_0603_6.3V6K 12600mV 2 2 1 4 0.02_1206_1% 3 ISL6251AHAZ-T_QSOP24 3 <40,41> 2 1 PR379 15.4K_0402_1% 1 2 8 2 5 - 6 PR384 105K_0402_1% 2 CV mode 1 1 + PC267 0.01U_0402_25V7K PU13B LM358DT_SO8 7 0 P PR383 10K_0402_1% 1 2 G 36 BATT_OVP PR382 499K_0402_1% 2 2 1 Per cell=4.5V PR380 340K_0402_1% 1 BATT-OVP=0.1112*VMB 4 Kv Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K R=514K//31.6K//(15.4K+3k)=11.372K r=514K//514K//31.6K=28.14K Vcell=0.175*Vadj+3.99v 4.2V=0.175*Vadj+3.99V =>Vadj=1.2V Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K)) 1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899 1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv A=Vref*(R/(R+514K))=0.052 Kv=9.451 VS LI-3S :13.5V----BATT-OVP=1.5012V PC266 0.01U_0402_25V7K 1 PR381 31.6K_0402_1% 4 Normal 3S LI-ON Cells 1 2 1 1 12 RB751V-40_SOD323-2 1 26251VDD 2 LGATE 6251VDDP DL_CHG 3 2 1 VADJ 14 BATT+ PR369 PQ64 AO4466_SO8 4 2 11 PC260 0.1U_0603_25V7K 2 BST_CHGA 2 1 PD13 <40,41> TCR=50ppm / C S Ki Vchlim=Iref*(PR374/(PR372+PR374)) =Iref*(100K/(80.6K+100K)) =Iref*0.5537 Ichanrge=(165mV/PR369)*(Vchlim/3.3V) =(165m/20m)*(1/3.3V)*Iref*0.5537 =1.3842*Iref Iref=0.7224*Ichanrge =>Ki=0.7224 Charging Voltage (0x15) 10 20K_0402_1% PR378 PR373 0_0603_5% BST_CHG 1 2 BATT Type PL29 10UH_MMD-10DZ-100M-X1_6A_20% CHG 1 2 VMB 36 CALIBRATE# CC=0.6~4.48A Iref=0.7224*Ichanrge kI=0.7224 IREF=0.43V~3.24V 2 4 2N7002W-T/R7_SOT323-3 3 CP mode Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) where Vaclm=1.502V, Iinput=4.07A PQ62 AO4466_SO8 5 6 7 8 2 1 3 PQ66 2 G CSOP 2 6251ACLIM 12.1K_0402_1% 36 65W/90W# CSON 1 6251VREF 1 PR375 2 1 PR374 100K_0402_1% 2 .1U_0402_16V7K 2 1 3 IREF 6251VREF PC259 1 2 PR377 PR377 2.55K_0402_1% 36,47 ACOFF 36 PC245 10U_1206_25V6M 2 1 DH_CHG 6 PR368 100_0402_1% 1 2 2 PC258 @ 100P_0402_50V8J PR372 80.6K_0402_1% 2 1 5 2 10K_0402_1% 1 36 ADP_I PR371 22K_0402_5% PACIN 1 2 ACOFF 1 PR366 2 PC256 0.01U_0402_25V7K ACON PQ65 PDTC115EU_SOT323 1 1 43,47 PACIN S 2 1 PC261 0.01U_0402_25V7K 2 1 ACON 1 47 D 2N7002W-T/R7_SOT323-3 3 PQ63 2 G 6800P_0402_25V7K 2 1 PC255 1 3 PR363 20_0402_5% 1 2 PC254 0.047U_0402_16V7K 1 2 PR364 20_0402_5% 2 1 PR365 PC257 20_0402_5% 0.1U_0603_25V7K 1 2 PR367 2_0402_5% LX_CHG 2 7 6251_EN 2 PACIN 2N7002W-T/R7_SOT323-3 G S PC264 10U_1206_25V6M 2 1 23 D PQ61 3 ACSET ACPRN 2 1SS355_SOD323-2 PC263 10U_1206_25V6M 2 1 2 DCIN 24 1 PC253 0.1U_0603_25V7K 2 1 DCIN PD12 2 PR370 4.7_1206_5% VDD wrong Value PC252 0.1U_0603_25V7K 2 1 ACOFF 2 1SS355_SOD323-2 PR357 200K_0402_1% 1 2 VIN PC262 680P_0402_50V7K 1 PD9 5 6 7 8 1 2 S PQ57 PDTC115EU_SOT323 VIN 1 1 1 1 3 PU17 2 2 SUSP# 36,38,42,48 BAS40CW_SOT323-3 9 PQ60 PDTC115EU_SOT323 36 3S/4S# SUSP# 3 100K_0402_1% 1 1 1 1 1 1 2 PC251 .1U_0402_16V7K 2 1 PR352 47K_0402_1% 1 2 PR356 10K_0402_1% FSTCHG 2 1 3 1 D PR360 47K_0402_5% 2 1 PQ55 PDTC115EU_SOT323 PR358 2 4 PR361 150K_0402_1% 2N7002W-T/R7_SOT323-3 3 PQ59 2 G PR359 10K_0402_5% 2 1 FSTCHG DCIN 8 7 6 5 1 PD10 PD11 1SS355_SOD323-2 6251VDD 1 2 6251VDD 2 1 1 2 3 CSIN JUMP_43X118 3 P3 36 FSTCHG PQ58 PDTC115EU_SOT323 1 CSIP 47K 2 2 1 PQ54 TP0610K-T1-E3_SOT23-3 PQ56 PDTA144EU_SOT323-3 47K 3 2 2 PR354 200K_0402_1% 4 2 PC248 5600P_0402_25V7K 1 2 4 3 2 2 1 PR353 47K_0402_1% PC249 0.1U_0603_25V7K 2 1 1 4 1 1 PC244 10U_1206_25V6M 2 1 8 7 6 5 PC250 2.2U_0603_6.3V6K 2 1 1 2 3 PR362 2 1 2 3 100K_0402_1% 8 7 6 5 PR355 100K_0402_1% 2 1 VIN 3 D CP = 85%*Iada ; CP = 4.07A CP = 85%*Iada ; CP = 2.91A ADP_I = 19.9*Iadapter*Rsense PQ51 AO4407A_SO8 C 4 12.60V Issued Date - Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: A B C Wednesday, June 30, 2010 D Sheet 46 of 56
5 4 3 2 1 D D B+ PR385 2.2M_0402_5% 1 PR386 1K_1206_5% 1 2 2 1 PR393 1 2 1 1 2 PC270 0.01U_0402_25V7K 2 PR398 47K_0402_5% 2 2 1 2N7002W-T/R7_SOT323-3 G 3 S PR396 100K_0402_5% 36,46 ACOFF 1 2 1 D PQ69 C PQ68 PDTC115EU_SOT323 2 PQ70 PDTC115EU_SOT323 PACIN 43,46 1 PQ71 PDTC115EU_SOT323 @ PR399 @PR399 66.5K_0402_1% 3 PR397 34K_0402_1% 2 1 2 2 1 PR395 499K_0402_1% B+ 1 1 RTCVREF PR394 191K_0402_1% PRG++ 2 PC268 0.1U_0603_25V7K 1 6 2 2 1 BAS40CW_SOT323-3 - O PR391 1K_1206_5% 1 2 32.4 7 3 3 PR390 1K_1206_5% 1 2 PU18B LM393DG_SO8 5 1 P 1 46 ACON + G 2 PC269 1000P_0402_50V7K 8 2 PD15 1 LL4148_LL34-2 4 18,44,45 MAINPWON TP0610K-T1-E3_SOT23-3 PQ67 PR388 1K_1206_5% 1 2 PD14 2 100K_0402_5% 1 VS PR389 100K_0402_1% C VIN PR387 499K_0402_1% 100K_0402_5% 1 2 PR392 1 VL 2 +5VALW 3 2 3 2 ACIN B Precharge detector Min. typ. Max. H-->L 14.589V 14.84V 15.243V L-->H 15.562V 15.97V 16.388V B BATT ONLY Precharge detector Min. typ. Max. H-->L 6.138V 6.214V 6.359V L-->H 7.196V 7.349V 7.505V A A Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Issued Date Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 47 of 56
5 4 3 2 1 D D C C PL30 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20% 1 2 +1.8VSP 2 LX_1.8V FB 2 GND 3 SW 4 IN 5 BS EN/SYNC 2 1 1 1.8V_EN 10 PC279 22U_0805_6.3V6M 1 1 PC278 22U_0805_6.3V6M 2 PR563 4.7_1206_5% PU20 MP2121DQ-LF-Z_QFN10_3X3 1 PR407 402K_0402_1% 1 2 2 PR405 309K_0402_1% 1 VFB=0.8V 8 IN 6 PC382 680P_0402_50V7K 7 POK 2 SW B @ PD16 @PD16 +1.5V B340A_SMA2 +1.5VS OP1 Short OP1 PR409 PC287 PQ78 OP2 PR409 PJ20 JUMP_43X79 2 PJ25 JUMP_43X79 PU21 2 2 2 1 1 OP2 Short 7 3 6 VOUT NC 5 TP 9 1 VREF VCNTL 4 +3VALW 8 NC 2 PR408 1K_0402_1% 2 1.8V_EN NC GND 2 36,38,42,46 SUSP# OP2@ PR409 0_0402_5% 1 PC284 4.7U_0603_6.3V6K PR401 22K_0402_5% 1 2 VIN 2 2 1 1 11 2 TP 1 1 1 PC283 10U_0805_10V4Z 2 2 PC282 10U_0805_10V4Z PR566 0_0402_5% 1 2 9 1 0.01U_0402_16V7K +5VALW B 2 GND 1 PC281 1 PC285 1U_0402_6.3V6K 1 PR410 1K_0402_1% 2008/08/10 Deciphered Date PC288 10U_0805_6.3V6M A Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date +0.75VSP 1 2N7002W-T/R7_SOT323-3 2 S 2 S G PC286 .1U_0402_16V7K 2 1 D susp 2 1 PQ78 1 PC287 .1U_0402_16V7K A D 2N7002W-T/R7_SOT323-3 3 1 PQ72 2 G 1 PR409 28K_0402_1% 1 2 3 38,42 SUSP PC274 0.47U_0603_16V7K 2 2 1 APL5336KAI-TRL_SOP8P8 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 48 of 56
A B C D B+ PJ21 1 PC290 4.7U_0805_25V6-K 1 1 1 3 2 1 14 +1.5VP 10 1 5 6 7 8 1 2 PR415 4.7_1206_5% 2 1 PC295 4.7U_0805_10V6K 1 + PC293 330U_6.3V_M 2 PC294 680P_0603_50V7K 3 2 1 RT8209BGQW_WQFN14_3P5X3P5 2 4 2 9 PQ74 AO4456_SO8 LG_1.5V 1 LGATE +5VALW PR417 11K_0402_1% NC BOOT PGND 2 LX_1.5V 11 2 Rds=4.5mΩ(Typ) 5.6mΩ(Max) 2 VFB=0.75V VFB=0.75V Vo=VFB*(1+PR418/PR419)=1.52V Freq=282KHz(min) , 300KHz(typ) 1 PR418 5.9K_0402_1% 1 2 2 JUMP_43X118 PL32 1UH_FDUE1040D-1R0M-P3_21.3A_20% 1 2 PC292 1 0.1U_0603_25V7K 2 7 1 @ PC297 47P_0402_50V8J 1 2 PC296 4.7U_0603_6.3V6K 15 1 6 open-drain PGOOD 12 VDDP FB UG_1.5V CS GND PR416 100_0603_1% 1 2 13 PHASE VDD 5 PR414 0_0603_5% 1 2BST_1.5V-1 UGATE VOUT 4 +5VALW TON 3 EN/DEM 2 2 8 1 BST_1.5V PU22 2 4 1.5V_EN @ PC291 @PC291 .1U_0402_16V7K 2 @ PR413 @PR413 47K_0402_5% 2 1 PR411 280K_0402_1% 1 2 1 PR412 0_0402_5% 1 2 36,42 SYSON PQ73 AO4466_SO8 2 5 6 7 8 Because +1.5VSP has 17.74A power budget, it includes DDR3, VGA chip, VRAM, so must use molding choke. 1 PC289 4.7U_0805_25V6-K 51117_1.5V_B+ EN_PSV 1. GND=>Disable SMPS 2. FLOAT=>PWM_only mode 3. HIGH=>Auto_skip mode PR419 5.76K_0402_1% 2 Cesr=15m ohm Ipeak=13.61A Imax=9.527A Vtrip=Rtrip*10uA=0.11V Iocp-min=Vtrip/(Rds(on)(max)*1.2)+Delta I / 2= 18.67A Iocp-max=Vtrip/(Rds(on)(typ)*1.2)+Delta I / 2=22.67A Iocpmin=18.67A ∆I=((19-1.5)*(1.5/19))/(L*Freq)=4.605A 1/2∆I=2.3A Iocp=18.67A~22.67A 3 3 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: A B C Wednesday, June 30, 2010 D Sheet 49 of 56
4 3 2 VGA_CORE Ipeak=27.82A,Imax=19.47A Delta I / 2 = 3.97A , Freq=1/ 75E-12*PR134=300K Hz Iocp(min)=1.2*Ipeak+Delta I / 2 = 37.354A Rsen=Iocp(min)*1.2*Rds(on)(max)/ISEN(min)=6.49K ohm ISEN(min)=19uA , Rds(on)=5.6m ohm(max) ,4.5m ohm(typ) Iocp(max)=ISEN(min)*Rsen/(1.2*Rds(on)(typ))=45.67A Iocp=36.7~45.67A PJ22 1 B+_CORE LX_VCORE VGA@ PR161 0_0603_5% DH_VCORE-1 1 2 VGA@ PR124 0_0603_5% VGA@ PC101 1 2 1 2 BST_VCORE 0.1U_0603_25V7K DH_VCORE 18 VGA_PWROK VGA@ PR126 4.7_0603_5% 1 2 7138_VCORE UG BOOT 2 VIN PVCC 5 1 VGA@ PR125 0_0603_5% 15 1 PHASE PGOOD 14 DCR=1.1mΩ(typ) 2.2U_0603_6.3V6K 7138_VCORE LG PGND 11 VGA@ PL9 0.36UH_ETQP4LR36WFC_24A_20% 1 4 12 ISEN DL_VCORE 13 VCC 0.95V 0.95V @ PR146 10K_0402_5% 1 22 GPU_VID0 VGA@ PR148 10K_0402_5% 1 2 2 G VGA@ PR150 10K_0402_5% 1 1 2 2 1 1 1 @ PR144 10K_0402_1% @ PR145 10K_0402_5% D GE1@ PQ76 2N7002W-T/R7_SOT323-3 D GE1@ PR147 10K_0402_5% 2 2 1 G S VGA@ PQ77 2N7002W-T/R7_SOT323-3 GPU_VID1 22 GE1@ PR149 10K_0402_5% S A 2 A 1 2 VGA@ PC111 4700P_0402_25V7K +3VSDGPU GE1@ PC110 @ PR143 4700P_0402_25V7K 10K_0402_1% 2 0.9V S 1 0 2 G S 3 0 GE1@ PQ38 2N7002W-T/R7_SOT323-3 2 0.9V VGA@ PQ75 2N7002W-T/R7_SOT323-3 2 0.85V D 2 G 2 0.85V VGA@ PR142 10K_0402_5% 2 1 2 0 1 1 3 2 1 1 2 0.85V 3 0.8V 1 reserve +3VSDGPU 2 1 GE1@ PR141 10K_0402_5% 1 2 D Core Voltage Level 0 +3VSDGPU GE1@ PR139 10K_0402_5% VGA@ PR140 10K_0402_5% reserve +NVVDD_SENSE 23 2 +3VSDGPU 1 reserve +NVVDD_SENSE B GE1-1@ PR137 20K_0402_1% 1 reserve C VGA@ PR132 10_0402_5% 2 1 1 GE@ PR137 30.9K_0402_1% 1 1 N11P-GE 1 1 Core Voltage Level 2 VGA@ PR135 4.99K_0402_1% GV2H@ PR136 49.9K_0402_1% 3 Core Voltage Level 5 6 7 8 5 6 7 8 3 2 1 Rds=4.5mΩ(typ) 5.6mΩ(max) 2 1 GE1@ PR136 30.9K_0402_1% 1 GPU_VID1 + ESR=10 mΩ VGA@ PR127 0_0402_5% VGA@ PC106 470P_0603_50V8J @PC998 for IC APW7138 2 GPU_VID0 4 VGA@ PR129 4.7_1206_5% GE@ PR136 60.4K_0402_1% GV2H@ PR138 11.8K_0402_1% N11P-GE1 1 VFB=0.6V GE1@ PR138 28K_0402_1% N11P-GV2H +VGA_COREP 3 VGA@ PC104 390U_2.5V_M VO 10 2 @ PC998 0.01U_0402_25V7K GE@ PR138 14.7K_0402_1% B 2 VGA@ PQ36 AO4456_SO8 4 Layout Note: Close IC 單獨拉回不搭Pin15 1 VGA@ PR134 44.2K_0402_1% 2 1 2 1 2 VGA@ PC109 2200P_0402_25V7K VGA@ PC107 22P_0402_50V8J 2 1 Layout Note: Close IC VGA@ PR133 33K_0402_1% VGA@ PQ35 AO4456_SO8 VGA@ PR131 1 2 6.49K_0402_1% 9 FB NC 6 VGA@ PC105 .1U_0402_16V7K 1 2 C FSET EN 3 2 1 5 1 VGA@ PR130 30K_0402_1% 1 2 APW7138NITRL_SSOP16 VGA@ PC103 2.2U_0603_6.3V6K 7 VGA_ON 24,38,42 VGA_ON 1 2 4 VGA@ PQ34 TPCA8030-H_SOP-ADV8-5 4 Layout Note: Close IC VGA@ PC102 1 2 1 3 +3VSDGPU 16 2 8 GND VGA@ PU998 @ PR128 10K_0402_5% D +5VS 3 2 1 1 2 VGA@ PC100 10U_1206_25V6M VGA@ PC99 10U_1206_25V6M VGA@ PC98 10U_1206_25V6M 2 1 2 D VGA@ PC171 0.1U_0805_50V7K 2 1 1 JUMP_43X118 2 1 1 2 2 2 1 B+ 1 2 5 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: 5 4 3 2 Sheet Wednesday, June 30, 2010 1 50 of 56
5 4 3 2 1 PJ23 6268_B+ LX_1.05VS_VTT 12 5 PC330 2.2U_0603_6.3V6K ISEN 2 4 10 @ PC999 0.01U_0402_25V7K @PC999 for IC APW7138 PR472 5.11K_0402_1% 1 2 @ 4 3 2 1 VO PR467 5.23K_0402_1% 1 2 1 PR470 57.6K_0402_1% 1 PR469 90.9K_0402_1% 1 1 2 11 2 PC336 6800P_0402_25V7K 1 2 22P_0402_50V8J PC334 +1.05VS_VTT Ipeak=20.14A Imax=14.10A Delta I / 2 = 2.176A , Freq=230K Hz Iocp(min)=1.2*Ipeak + Delta I / 2 = 26.34A Rsen=Iocp(min)*1.2*Rds(on)(max)/ISEN(min)=5.23K ohm ISEN(min)=19uA , Rds(on)=3.2m ohm(max) ,2.3m ohm(typ) Iocp(max)=ISEN(min)*Rsen/(1.2*Rds(on)(typ))=36A Iocp=26.34~36A Vref=(Rb/(Rtop+Rbot))*Vo =>0.6=(6.65/(5.11+6.65))*Vo Vo=1.061V 2 7 6 FB NC 1 2 2 PC331 .1U_0402_16V7K FSET EN 9 5 +1.05VS_VTTP 1 1 2 DCR=2.7mΩ(Typ) 3.0mΩ(Max) PL38 1UH_FDUE1040D-1R0M-P3_21.3A_20% 1 2 APW7138NITRL_SSOP16 1 PR465 4.7_1206_5% 1 + PC332 680P_0603_50V7K Rdson=2.3mΩ/3.2mΩ Layout Note: Close IC 單獨拉回不搭Pin15 @ PR471 0_0402_5% 1 2 PC333 390U_2.5V_M 2 C Material Note: 330uF/9 mΩ, number are 3, Power 1, HW 2 +1.05VS_VTTP @ PR473 10_0402_5% 1 2 VTT_SENSE 7 VFB=0.6V PR564 0_0402_5% 1 2 +1.05VS_VTT 1 B PR476 6.49K_0402_1% 2 B Layout Note: Close IC Change PU999 to APW7138 in PVT. @ PR468 10K_0402_5% C 13 PGND 2 PQ95 TPCA8028-H_SOP-ADVANCE8-5 TPCA8028-H_SOP-ADVANCE8-5 LG 1 PC329 2.2U_0603_6.3V6K DL_1.05VS_VTT PQ83 PQ83 TPCA8028-H_SOP-ADVANCE8-5 38 VS_ON 14 PQ82 TPCA8030-H_SOP-ADV8-5 4 1 2 2 6268_VCORE_1.05VS_VTT 4 VCC PR466 57.6K_0402_1% 1 2 PR464 4.7_0603_5% 1 2 6268_VCORE_1.05VS_VTT BOOT PVCC D 2 1 16 UG PHASE PGOOD VIN 2 PR463 0_0603_5% 15 1 2 8 GND PU999 3 1 PC328 0.1U_0603_25V7K +5VS 5 @ PR462 1K_0402_1% 1 2 DH_1.05VS_VTT PR461 BST_1.05VS_VTT 1 2 0_0603_5% 3 2 1 H_VTTPWRGD 5 PGOOD=1V 5 1 2 PC327 10U_1206_25V6M PC326 10U_1206_25V6M 1 2 D +3VS PR458 0_0402_5% 1 2 3 2 1 1 1 1 2 2 JUMP_43X118 PR459 2K_0402_1% 2 B+ A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: 5 4 3 2 Sheet Wednesday, June 30, 2010 1 51 of 56
5 4 3 2 1 Intel Auburndale CPU(Integrate Graphics) Ipeak=22A Imax=15A OCP calculation : Assume DCR=1.1m ohm G1=Rn/(Rn+Rsum)=0.617 where Rn=PR277 // (PR274+PH3)=5.875k ohm Rsum=PR269=3.65k ohm LL=2*Rdroop*G1*DCR/Ri= 6.96m V/A where Rdroop=PR271=8.66k ohm, Ri=PR283=1.69k ohm Iocp=OCP Threshold*Rdroop/LL=24.89A B+ D PJ24 1 2 2 UMA@ PC191 0.22U_0402_6.3V6K GFXVR_IMON 8 ISUMBST_GFX 1 1 14 3 2 1 1 2 2 1 1 VID2 VID3 UMA@ PR274 2.61K_0402_1% UMA@ PH3 1 2 1 2 +5VALW UMA@ PC198 2.2U_0603_6.3V6K Rds=4.5mOHM(typ) Rds=5.6mOHM(max) UMA@ PC199 680P_0603_50V7K Layout Note: Place near Choke 1 UMA@ PR270 0_0402_5% + UMA@ PC130 330U_X_2VM_R6M 2 10K_0402_5%_TSM0A103J4302RE 1 2 UMA@ PR277 11K_0402_1% UMA@ PC202 .1U_0402_16V7K 1 2 Material Note: 330uF/6 mΩ, number are 3, PW 1, HW 1, 1 of HW is backup 2 @ PR279 10K_0402_1% UMA@ PR269 3.65K_0805_1% 2 4 2 1 1 4 UMA@ PR273 1 2 0_0603_5% 22 23 VID5 VID4 24 VID6 3 UMA@ PR268 4.7_1206_5% UMA@ PQ41 AO4456_SO8 2 21 UMA@ PQ40 AO4456_SO8 19 20 +VGFX_COREP 5 6 7 8 5 6 7 8 13 IMON 11 9 10 12 VIN VDD RTN BOOT 17 1 UMA@ PC200 150P_0402_50V8J DCR=1.1 mOHM UMA@ PL10 0.45UH_PCMB104T-R45MN_25A_20% 4 1 18 DL_GFX VID1 VR_ON UMA@ PR276 8.06K_0402_1% 2 1 DPRSLPVR UMA@ PC201 22P_0402_50V8J 1 2 CLK_EN# C 4 16 LX_GFX VID0 PGOOD 25 2 UMA@ PR275 17.8K_0402_1% 1 2 1 1 +VGFX_COREP UMA@ PQ39 TPCA8030-H_SOP-ADV8-5 2 15 DH_GFX VCCP RBIAS 26 147K for CPU 47K for GPU UMA@ PC196 100P_0402_50V8J 2 VSSP LGATE 27 2 UMA@ PC197 1000P_0402_50V7K 2 1 VW 3 UGATE UMA@ PU12 ISL62881HRZ-T_QFN28_4X4 PHASE 28 UMA@ PR272 825K_0402_1% 1 2 1 COMP 4 UMA@ PR271 8.66K_0402_1% 2 1 FB 5 UMA@ PR294 2 1 47K_0402_1% VSEN 6 1 UMA@ PC193 0.22U_0603_25V7K 3 2 1 7 ISUM AGND UMA@ PC195 330P_0402_50V7K 1 UMA@ PR293 10_0402_1% ISUM+ UMA@ PC194 330P_0402_50V7K 29 2 8 1 2 8 VCC_AXG_SENSE +VGFX_COREP 2 UMA@ PR266 0_0603_5% 2 8 VSS_AXG_SENSE 5 ISUM+ UMA@ PC192 1000P_0402_50V7K 1 2 C 2 UMA@ PR265 22.6K_0402_1% 3 2 1 UMA@ PR292 2 1 10_0402_1% VSS_AXG_SENSE 1 UMA@ PC189 1U_0402_6.3V6K 2 1 1 1 UMA@ PR263 0_0603_5% UMA@ PR264 1_0603_5% 2 1 2 +5VALW UMA@ PC190 0.22U_0603_25V7K 1 @ PC188 0.1U_0402_25V6 2 1 2 2 GFX_B+ 1 1 UMA@ PC126 10U_1206_25V6M 2 1 2 JUMP_43X118 UMA@ PC125 10U_1206_25V6M 2 1 2 UMA@ PC187 2200P_0402_50V7K D UMA@ PC203 .1U_0402_16V7K 1 2 GFXVR_VID_0 8 GFXVR_VID_1 8 GFXVR_VID_2 8 GFXVR_VID_3 8 GFXVR_VID_4 8 GFXVR_VID_5 8 GFXVR_VID_6 8 GFXVR_EN 8 GFXVR_DPRSLPVR UMA@ PR283 UMA@ PR288 1.69K_0402_1% 82.5_0402_1% 1 2 1 2 UMA@ PC204 0.01U_0402_16V7K 8 ISUM+ 1 2 B @ PR284 100_0402_1% 1 PR280 PR281 PR282 PR285 PR286 PR287 PR289 PR290 PR291 2 UMA@ 1 UMA@ 1 UMA@ 1 UMA@ 1 UMA@ 1 UMA@ 1 UMA@ 1 UMA@ 1 UMA@ 1 1 2 2 2 2 2 2 2 2 2 1 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 2 36 GFX_CORE_PWRGD B @ PC205 180P_0402_50V8J ISUM- @ PR300 1K_0402_1% 2 reduce system idle power +1.05VS_VTTP A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 SCHEMATICS,MB A5893 Document Number Rev C 401869 Sheet Wednesday, June 30, 2010 1 52 of 56
8 7 6 5 4 3 2 1 +5VS HFM_Icc LL Icc_TDC Auburndale 45W 1.075 50 1.9m 37 35 Auburndale 35W 0.975 38 1.9m 29 27 Clarksfield SV 0.95 51 1.9m 38 39 Clarksfield XE 0.95 65 TBD 48 TBD 1 PH0 7 H_DPRSLPVR PR565 0_0805_5% H_PSI# CPU_VID6 CPU_VID5 CPU_VID4 CPU_VID3 CPU_VID2 CPU_VID1 CPU_VID0 1 2 1 1 3 +5VS_3212 +5VS_3212 1 7 7 7 7 7 7 7 # of PH 0 2 7 PH1 Icc_Dyn H +CPU_B+ PL39 FBMA-L18-453215-900LMA90T_1812 PR481 10_0603_5% 2 SW2 26 PR515 69.8K_0402_1% 1 2 PC341 10U_1206_25V6M 1 2 2 3 2 1 5 CSREF PL41 0.36UH_ETQP4LR36WFC_24A_20% 4 1 3 2 1 SWFB3 3 2 1 @ PQ93 TPCA8028-H_SOP-ADVANCE8-5 1 4 D PR513 10_0402_5% 1 2 3212_DRVL2 4 3 2 1 PWM3 24 OD3 23 ILIM 21 3212_DRVL2 PR519 2.05K_0402_1% PC359 680P_0603_50V7K @ PQ92 TPCA8028-H_SOP-ADVANCE8-5 2 Place PH1 close to PHASE 1 inductor on the same layer PR523 165K_0402_1% 1 2 2 PH6 100K_0402_1%_NCP15WF104F03RC PH7 100K_0402_1%_NCP15WF104F03RC PC364 1U_0603_16V6K 1 2 2 CSREF PR522 73.2K_0402_1% 2 1 1 PC361 1000P_0402_50V7K PC363 1200P_0402_50V7K 1 2 C 1 PC362 680P_0402_50V7K 2 1 2 PR521 0_0402_5% 2 PR520 1K_0402_1% 2 2 1 1 +CPU_B+ PC360 0.01U_0402_50V7K 3212_SW2 PR512 4.7_1206_5% @ 2 TTSense C @ PQ91 TPCA8030-H_SOP-ADV8-5 PC358 0.1U_0603_25V7K 2 1 2.05K PR517 649K_0402_1% Connect to input caps 22 CSCOMP 20 CSSUM 19 CSREF 18 LLINE 3212_CSCOMP PR514 80.6K_0402_1% 3212_CSCOMP 2 1 PR516 162K_0402_1% 1 17 RT 14 1 2 16 13 1 2 1 3212_VRTT 2 G S BST2 2 PR518 7.32K_0402_1% RPM 1 1 +5VS_3212 D 3 PQ94 2 2N7002W-T/R7_SOT323-3 1 5 H_PROCHOT# 15 AGND RAMP GND 49 PR510 @ 499_0402_1% IREF PR511 0_0402_5% D 25 1 1 4 3 2 1 2 1 12 Avoid high dV/dt 2 2 3212_DRVH2 4 5 TTSNS 3212_DRVH2 PR509 0_0603_5% 2 1 PC339 10U_1206_25V6M 5 3 2 1 5 3 2 1 5 1 3212_DRVH2 +3VS PR508 0_0402_5% 1 5 3212_SW2 27 DRVH2 VRTT PQ90 TPCA8030-H_SOP-ADV8-5 @ PC356 0.1U_0603_25V7K 2 11 3212_CS_PH2 E PC355 10U_1206_25V6M 1 2 10 TTSENSE VARFR 3212_DRVL2 PR506 100_0402_1% 1 2 2 9 3212_VRTT 2 28 +CPU_B+ 30 29 SWFB2 1 8 5.11K_0402_1% TRDET +5VS_3212 PR507 0_0402_5% PGND DRVL2 COMP @ PQ89 TPCA8028-H_SOP-ADVANCE8-5 PC350 4.7U_0603_6.3V6K CSREF 7 PQ88 TPCA8028-H_SOP-ADVANCE8-5 1 E 3212_DRVL1 PC347 680P_0603_50V7K @ 3212_CS_PH2 1 ADP3212MNR2G_QFN48_7X7 +5VS 2 PR503 1.65K_0402_1% 1 2 4 3212_CS_PH1 31 F PR500 10_0402_5% 1 DRVL1 3212_CS_PH1 32 FB 3212_DRVL1 4 +CPU_CORE 3 2 PVCC 2 DCR=1.1m OHM 1 FBRTN 2 PL40 0.36UH_ETQP4LR36WFC_24A_20% 1 4 2 33 G + 1 2 3212_DRVL1 3212_SW1 PR502 100_0402_1% 1 2 1 SWFB1 5 PC353 PR504 150P_0402_50V8J 39.2K_0402_1% 1 2 1 2 2 PR505 5 34 B+ 1 PR499 4.7_1206_5% @ 3212_DRVH1 3 2 1 SW1 PC346 0.1U_0603_25V7K 2 1 PC354 10U_1206_25V6M 36 35 CLKEN 12P_0402_50V8J 3212_FB PC352 6 PC351 150P_0402_50V8J 1 2 @ PQ86 TPCA8030-H_SOP-ADV8-5 PR498 0_0603_5% 2 1 1 4 5 VCC BST1 DRVH1 4 3212_FBRTN 2 3212_DRVH1 4 3 2 1 2 1 38 IMON @ 3212_SW1 2 1 1 PC349 1000P_0402_50V7K CLK_EN# PC348 0.068U_0402_16V7K~N 2 PR501 5.49K_0402_1% PQ87 TPCA8030-H_SOP-ADV8-5 PGND AGND 37 PH1 39 40 PSI PH0 0_0402_5% 1 499_0402_1% 1 PR490 2 41 0_0402_5% 1 PR489 2 VID6 42 0_0402_5% 1 PR488 2 VID5 43 0_0402_5% 1 PR487 2 VID4 44 0_0402_5% 1 PR486 2 VID3 45 0_0402_5% 1 PR485 2 46 0_0402_5% 1 PR484 2 PR491 0_0603_5% 2 1 1 PWRGD 3 IMVP_IMON 2 7 IMVP_IMON PC344 1U_0603_16V6K 3212_DRVH1 EN 2 PR496 0_0402_5% 2 @ 48 1 1 F 2 DPRSLP 1 12,15 VGATE VID2 +1.05VS_VTT VID0 12 CLK_ENABLE# CLK_EN# PR497 0_0402_5% 2 PU27 PR494 2 1 0_0402_5% 1 1 2 PR493 3K_0402_5% 1 PR495 0_0402_5% VID1 2 +3VS PR492 3K_0402_5% PR483 2 +3VS 47 0_0402_5% 1 PR482 2 G PC342 2200P_0402_50V7K 2 1 PC345 0.1U_0603_25V7K 2 1 2 36,38 VR_ON PC343 220U_25V_M HFM_VID H PR524 2 1 2 B PR525 @ PR526 100_0402_1% 2 1 VCCSENSE 3212_CS_PH1 3212_CS_PH2 1 B 130K_0603_1% +CPU_CORE VCCSENSE 7 VSSSENSE 2 130K_0603_1% 1 VSSSENSE 7 1 @ PR527 100_0402_1% A A Compal Secret Data Security Classification 2009/02/04 Issued Date Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 8 7 6 5 4 3 2 Compal Electronics, Inc. SCHEMATICS,MB A5893 Document Number Rev C 401869 Wednesday, June 30, 2010 Sheet 53 1 of 56
5 4 3 2 Version change list (P.I.R. List) Item D 1 2 3 4 5 6 Fixed Issue Reason for change Modify VGA_COREP circuit Reduce component quantity Modify CPU_COREP circuit Rev. PG# Modify List 1 Page 1 of 1 for PWR Date Change PL9 to SH12036BM00(S COIL .36UH +-20% ETQP4LR36WFC 24A) Phase 2009-1222 PVT D 0.1 50 Arrandale CPU commond design(1 HS, 1LS MOS) 0.1 53 Modify VGA_COREP circuit PVT-2 add N11P-GE1 VGA, change VID setting. 0.2 50 Modify +VSBP circuit Add PC224 for 3VS spike issue 0.2 44 Modify +1.05VS_VTTP circuit Change voltage level from 1.061V to 1.072V. 0.2 51 Change PR476 to SD034649180(S RES 1/16W 6.49K +-1% 0402) 2010-0201 PVT-2 Modify +0.75VSP circuit Change RC for HW timing.(S3 shutdown issue) 0.2 48 Change PR409 to SD034280280(S RES 1/16W 28K +1% 0402) 2010-0201 PVT-2 Change PC287 to SE076104K80(S CER CAP .1U 16V K X7R 0402) Change PQ89/PQ93 SB00000GL00(S TR TPCA8028-H 1N SOP ADVANCE) BOM structure to @ Change PR136/PR138 BOM structure to GV2H@ Change PR137/139/141/143/147/149, PC110 and PQ38/76 BOM structure to GE1@ 2009-1222 PVT add PC224 to SE000000K80(S CER CAP 1U 6.3V K X5R 0402) 2010-0113 PVT-2 2010-0113 PVT-2 7 C 8 C 9 10 11 12 13 14 B 15 B 16 17 18 19 20 21 22 A A 23 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 54 of 56
5 4 3 2 1 A -->Modify item D D C C B B A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 55 of 56
A B C D E BOM Config PEW71 SKU N11P-GE DISCRETE ONLY without 3G BT@,DIS@,DIS ONLY@,NonSG@,71@,X7621@,GE@,NonOPT@ 431869BOL21 PEW71 SKU N11P-GV2H-A3 DISCTETE ONLY without 3G 1 BT@,DIS@,DIS ONLY@,NonSG@,71@,X7621@,GV2H@,GV2HA3@,NonOPT@,NonGE@ 431869BOL22 1 2 2 3 3 PCB GV2HA2@ GV2HA3@ GE1@ GE@ ZZZ U51 U51 U51 U51 LA-5893P REV0 M/B N11P-GV2H-A2_BGA969 N11P-GV2H-A3_BGA969 N11P-GE1-A3 BGA 969P N11P-GE-A1 BGA 969P ZZZ2 ZZZ1 X7622@ X76198BOL22 4 ALT. GROUP PARTS 2G HYN X7621@ X76198BOL21 ALT. GROUP PARTS 1G HYN 4 ALT. GROUP PARTS 1G SAM Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: A B C D Wednesday, June 30, 2010 Sheet E 56 of 56

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Aspire 4551 g

  • 1.
    A B C D E 1 1 Compal Confidential 2 2 PEW71/91/51 M/BSchematics Document Intel Arrandale Processor with DDRIII + Ibex Peak-M NV N11P-GV2H and N11P-GE 2010-06-07 3 3 REV:1.0 4 4 2009/08/01 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: A B C D Sheet Wednesday, June 30, 2010 E 1 of 56
  • 2.
    A B C D E Clock Generator Compal Confidential IDT:9LVS3199AKLFT Realtek: RTM890N-631-VB-GRT Model Name : NEW71/91 File Name : LA5893P 133/120/100/96/14.318MHZ to PCH Fan Control page 41 page 12 1 1 PEG(DIS) 100MHz PCI-E 2.0x16 5GT/s PER LANE page 4,5,6,7,8,9 CRT(DIS) FDI x8 (UMA) CRT Conn. page 30 2 LVDS Conn. page 29 DMI x4 100MHz 1GB/s x4 MINI Card x2 WLAN, WWAN USB port 12,13 page 34 port 1 page 38 DC/DC Interface CKT. page 42 4 Power Circuit DC/DC page 43~53 3.3V 24MHz ALC272X SPI page 39 port 0 SATA HDD Conn. page 31 TI TPS6017 40 page page 13 SATA CDROM Conn. page 31 LPC BUS 3 33MHz Int. Speaker ENE KB926 Phone Jack x 2 page 40 page 40 page 36 USB/B 2 Ports USB Port 0,2 page 35 Card Reader USB Port9 RTS5160 Audio AMP port 1 Touch Pad Int.KBD page 37 page 37 CPU XDP page 35 page 5 EC ROM LS-5893P page 37 LS-5894P Power/B PCH XDP LID_SW/B 4 page 38 page 21 LS-5895P 3G USB Port10,13 2009/08/01 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification page 35 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A page 35 2 SPI ROM x1 page 32 LS-5896P Power On/Off CKT. USB port 9 page 28 3.3V 48MHz BCM57780 Sub-board LS-5891P page 15 USB port 8 page 35 HDA Codec page 13,14,15,16 17,18,19,20,21 100MHz page 33 RTC CKT. USB port 11 LAN(GbE) RJ45 3 Card Reader RTS5160 PCH 100MHz SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) CMOS Camera HD Audio Intel Ibex Peak-M page 30 PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) Bluetooth Conn USB port 1 USBx14 LVDS(UMA) CRT(UMA) TMDS(UMA) HDMI Level Shift USB conn x3 USB port 0, 2 on USB/B page 35 100MHz 2.7GT/s page 28 HDMI(UMA) port 2 page 10,11 1.5V DDRIII 800/1066 Processor rPGA988A LVDS(DIS) HDMI Conn. BANK 0, 1, 2, 3 Arrandale (UMA/DIS) page 22,23,24,25,26,27 HDMI(DIS) Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2 Dual Channel Intel 133MHz NV N11P-GV2H NV N11P-GE B C D SCHEMATICS,MB A5893 Document Number Rev C 401869 Sheet Wednesday, June 30, 2010 E 2 of 56
  • 3.
    A B C D Voltage Rails Power Plane S1 Description S3 VIN N/A N/A N/A Batterypower supply (12.6V) N/A N/A N/A B+ AC or battery power rail for power circuit. N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF +VGA_CORE Core voltage for GPU ON OFF OFF +VGFX_CORE Core voltage for Arrandale GPU (only for arrandaleCPU) ON OFF OFF +0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF +1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF +1.05VS_VTTP to +1.05VS_VTT switched power rail for ARD CPU ON OFF +1.05VS_VTT to +1.05VS_PCH power for PCH ON OFF OFF +1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF +1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Vcc Ra/Rc/Re +1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF Board ID +1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF +3VALW +3VALW always on power rail ON ON ON* +3VALW_EC +3VALW always to KBC ON ON ON* +3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* +3V +3VALW to +3V power rail for PCH (Short Jumper) ON ON ON* +3VS +3VALW to +3VS power rail ON OFF OFF +5VALW +5VALWP to +5VALW power rail ON ON ON* +5V +5VALW to +5V switched power rail for PCH (Short resister) ON ON ON* 0 1 2 3 4 5 6 7 +5VS +5VALW to +5VS switched power rail ON OFF +VSBP to +VSB always on power rail for sequence control ON ON ON* +RTCVCC RTC power ON ON ON +V +VS Clock OFF +VSB +VALW OFF +1.05VS_PCH SLP_S1# SLP_S3# SLP_S4# SLP_S5# OFF +1.05VS_VTT 2 Adapter power supply (19V) BATT+ 1 SIGNAL STATE S5 E HIGH HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Full ON Board ID / SKU ID Table for AD channel Device Device Board ID 0 1 2 3 4 5 6 7 0001 011X b Address PCH SM Bus address Device Address Clock Generator (9LVS3199AKLFT, RTM890N-631-VB-GRT) 1001 000Xb DDR DIMM2 1001 010Xb V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V BTO Item UMA ONLY Discrete Discrete Only VRAM Switchable UMA ONLY & OPTIMUS 3G Blue Tooth OPTIMUS NonSG SKU NEW71 NEW91 N11P-GV2H N11P-GE1 N11P-GV2H-A2 N11P-GV2H-A3 Non OPT SKU SG or OPT USB Port Table USB 2.0 USB 1.1 Port 3 UHCI0 BOM Config move to page 56 UHCI1 EHCI1 UHCI2 VRAM BOM Config X7621@: X76198BOL21 ALT. GROUP PARTS 1G SAM UHCI3 X7622@ UHCI4 X76198BOL22 V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BTO Option Table PCB Revision 0.1 0.2 0.3 1.0 1101 0010b DDR DIMM0 V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V BOARD ID Table EC SM Bus2 address Address Smart Battery 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC 2 Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. EC SM Bus1 address 1 ALT. GROUP PARTS 1G HYN EHCI2 UHCI5 UHCI6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 3 External USB Port USB/B (Right Side) USB Port (Left Side) USB/B (Right Side) Camera Card Reader SIM Card Blue Tooth Mini Card(WLAN) Mini Card(GPS) BOM Structure UMA ONLY@ DIS@ DIS ONLY@ X76@ SG@ UMOP@ 3G@ BT@ OPT@ NonSG@ 71@ 91@ GV2H@ GE1@ GV2HA2@ GV2HA3@ NonOPT@ SGOPT@ 3 VRAM P/N : Samsung : SA000035720 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA ABO!) Hynix : SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA ABO! ) 4 4 2009/08/01 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D SCHEMATICS,MB A5893 Document Number Rev C 401869 Sheet Wednesday, June 30, 2010 E 3 of 56
  • 4.
    5 4 3 2 1 JCPU1E PEG_IRCOMP R485 1 2 49.9_0402_1% EXP_RBIAS R493 1 2 750_0402_1% RSVD32 RSVD33 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] B24 D23 B23 A22 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_HTX_PRX_N0 DMI_HTX_PRX_N1 DMI_HTX_PRX_N2 DMI_HTX_PRX_N3 D24 G24 F23 H23 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3 D25 F24 E23 G23 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7 D22 C21 D20 C18 G22 E20 F20 G19 FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] 15H_FDI_FSYNC0 15 H_FDI_FSYNC1 F17 E17 FDI_FSYNC[0] FDI_FSYNC[1] 15 H_FDI_INT C17 FDI_INT 15 H_FDI_LSYNC0 15 H_FDI_LSYNC1 F18 D17 FDI_LSYNC[0] FDI_LSYNC[1] C PCI EXPRESS -- GRAPHICS E22 D21 D19 D18 G21 E19 F21 G18 Intel(R) FDI H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7 15mil DMI DMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2 DMI_PTX_HRX_P3 D A24 C23 B22 A21 B PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS B26 A26 B27 A25 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 PEG_GTX_C_HRX_N15 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N0 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P0 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 PEG_HTX_GRX_N15 PEG_HTX_GRX_N14 PEG_HTX_GRX_N13 PEG_HTX_GRX_N12 PEG_HTX_GRX_N11 PEG_HTX_GRX_N10 PEG_HTX_GRX_N9 PEG_HTX_GRX_N8 PEG_HTX_GRX_N7 PEG_HTX_GRX_N6 PEG_HTX_GRX_N5 PEG_HTX_GRX_N4 PEG_HTX_GRX_N3 PEG_HTX_GRX_N2 PEG_HTX_GRX_N1 PEG_HTX_GRX_N0 C586 C561 C584 C559 C582 C557 C580 C555 C578 C553 C576 C551 C574 C549 C572 C547 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_N0 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] 10mil L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 PEG_HTX_GRX_P15 PEG_HTX_GRX_P14 PEG_HTX_GRX_P13 PEG_HTX_GRX_P12 PEG_HTX_GRX_P11 PEG_HTX_GRX_P10 PEG_HTX_GRX_P9 PEG_HTX_GRX_P8 PEG_HTX_GRX_P7 PEG_HTX_GRX_P6 PEG_HTX_GRX_P5 PEG_HTX_GRX_P4 PEG_HTX_GRX_P3 PEG_HTX_GRX_P2 PEG_HTX_GRX_P1 PEG_HTX_GRX_P0 C585 C560 C583 C558 C581 C556 C579 C554 C577 C552 C575 C550 C573 C548 C571 C546 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_P0 AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30 AJ13 AJ12 RSVD34 RSVD35 AH25 AK26 RSVD36 RSVD_NCTF_37 AL26 AR2 RSVD38 RSVD39 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 SA_DIMM_VREF (CFD Only) SB_DIMM_VREF (CFD Only) RSVD11 RSVD12 RSVD13 RSVD14 AJ26 AJ27 1 @ R61 3.01K_0402_1% R60 3.01K_0402_1% 1 DIS@ @ 1 R59 3.01K_0402_1% 1 @ 2 CFG0 2 2 CFG3 CFG4 2 CFG7 WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1 AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86 B19 A19 R501 0_0402_5% DMI_PTX_HRX_N[0..3] 15 DMI_PTX_HRX_P[0..3] 15 H_FDI_TXN[0..7] H_FDI_TXP[0..7] 15 15 RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75 AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 RSVD21 RSVD22 RSVD_NCTF_23 RSVD_NCTF_24 RSVD26 RSVD27 A34 A33 RSVD_NCTF_28 RSVD_NCTF_29 C35 B35 PEG_HTX_C_GRX_N[0..15] 22 PEG_HTX_C_GRX_P[0..15] 22 E15 F15 A2 D15 C15 AJ15 AH15 RSVD19 RSVD20 J29 J28 PEG_GTX_C_HRX_N[0..15] 22 PEG_GTX_C_HRX_P[0..15] 22 RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65 RSVD17 RSVD18 C1 A3 DMI_HTX_PRX_N[0..3] 15 DMI_HTX_PRX_P[0..3] 15 AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32 RSVD15 RSVD16 AC9 AB9 H_RSVD17_R H_RSVD18_R A20 B20 U9 T9 R497 0_0402_5% @ 1 2 @ 1 2 AT3 AR1 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58 D AP1 AT2 RSVD_NCTF_42 RSVD_NCTF_43 R58 3.01K_0402_1% RSVD_NCTF_40 RSVD_NCTF_41 RESERVED JCPU1A DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3 RSVD_NCTF_30 RSVD_NCTF_31 IC,AUB_CFD_rPGA,R1P0 CONN@ VSS C R146 0_0402_5% RSVD64_R 2 @ @ RSVD65_R 2 R147 0_0402_5% 1 1 B AP34 IC,AUB_CFD_rPGA,R1P0 CONN@ A eDP Signals Mapping eDP Singal PEG Singals PEG_HTX_C_GRX_P15 eDP_TX0 eDP_TX#0 PEG_HTX_C_GRX_N15 eDP_TX1 PEG_HTX_C_GRX_P14 eDP_TX#1 PEG_HTX_C_GRX_N14 eDP_TX2 PEG_HTX_C_GRX_P13 eDP_TX#2 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_P12 eDP_TX3 eDP_TX#3 PEG_HTX_C_GRX_N12 eDP_AUX PEG_GTX_C_HRX_P13 eDP_AUX# PEG_GTX_C_HRX_N13 eDP_HPD# PEG_GTX_C_HRX_P12 H_FDI_FSYNC0 H_FDI_FSYNC1 R519 1 DIS ONLY@ 2 R517 1 DIS ONLY@ 2 1K_0402_5% 1K_0402_5% H_FDI_INT R513 1 DIS ONLY@ 2 1K_0402_5% H_FDI_LSYNC0 H_FDI_LSYNC1 Lane Reversal PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_P3 R520 1 DIS ONLY@ 2 R515 1 DIS ONLY@ 2 CFG0 - PCI-Express Configuration Select CFG4 - Display Port Presence *1:Single PEG 0:Bifurcation enabled *1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port 1K_0402_5% 1K_0402_5% CheckList0.8 1.22 Auburndale Graphics Disable CFG3 - PCI-Express Static Lane Reversal *:Default *1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ... A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 SCHEMATICS,MB A5893 Document Number Rev C 401869 Wednesday, June 30, 2010 Sheet 1 4 of 56
  • 5.
    5 4 3 2 1 JCPU1B AT23 COMP3 R507 2 1 20_0402_1% H_COMP2 AT24 COMP2 R5212 1 49.9_0402_1% H_COMP1 G16 COMP1 R503 2 1 49.9_0402_1% H_COMP0 AT26 COMP0 SKTOCC#_R AH24 SKTOCC# T7 @ PAD D H_CATERR# H_PECI_R 2 AT15 CATERR# THERMAL THERMAL R547 1 0_0402_5% 18 H_PECI AK14 PECI BCLK BCLK# A16 B16 BCLK_ITP BCLK_ITP# E16 D16 DPLL_REF_SSCLK DPLL_REF_SSCLK# A18 A17 CLK_CPU_XDP CLK_CPU_XDP# AR30 AT30 PEG_CLK PEG_CLK# CLK_CPU_BCLK 18 CLK_CPU_BCLK# 18 SM_DRAMRST# CLK_CPU_DMI 14 CLK_CPU_DMI# 14 THERMTRIP# AP26 RESET_OBS# R123 1 0_0402_5% C 2 H_PM_SYNC_R AL15 PM_SYNC R122 1 0_0402_5% 15 H_PM_SYNC 2 H_CPUPWRGD_1 AN14 VCCPWRGOOD_1 R121 1 0_0402_5% 18 H_CPUPWRGD R150 1 0_0402_5% 15 PM_DRAM_PWRGD 2 R489 1 0_0402_5% VCCPWRGOOD_0 AK13 2 H_VTTPWRGD_R 0_0402_5% SM_DRAMPWROK VTTPWRGOOD AM26 TAPPWRGOOD PLT_RST#_R 2 AM15 H_PWRGD_XDP_R AL14 +1.05VS_VTT 2009/08/14 #425302 CP_S3PowerReduction WhitePaper_Rev1.0 SM_DRAMRST# 10 PM_EXT_TS#[0] PM_EXT_TS#[1] AN15 AP15 PM_EXTTS#0 PM_EXTTS#1_R AT28 AP27 XDP_PRDY# XDP_PREQ# TCK TMS TRST# AN28 AP28 AT27 XDP_TCLK XDP_TMS XDP_TRST# TDI TDO TDI_M TDO_M AT29 AR27 AR29 AP29 XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M DBR# AN25 XDP_DBR#_R BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23 RSTIN# 1 R567 2 100K_0402_5% R539 1 R538 1 R548 1 +1.05VS_VTT 2 10K_0402_5% 2 10K_0402_5% 2 0_0402_5% SM_RCOMP_0 R578 1 SM_RCOMP_1 R576 1 SM_RCOMP_2 R573 1 R89 R496 R495 R90 R62 R499 1 XDP_TDI_R XDP_TDO_M SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 XDP_PRDY# XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TCLK XDP_TRST# AL1 AM1 AN1 @ @ @ @ @ R488 1 R475 1 1 1 1 1 1 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 2 2 2 2 2 PM_EXTTS#0_1 10,11 2 51_0402_5% 2 100_0402_1% 2 24.9_0402_1% 2 130_0402_1% 2 0_0402_5% 2 0_0402_5% @ XDP_TDI XDP_TDO R87 1 R480 0_0402_5% 2 0_0402_5% XDP_DBRESET# XDP_DBRESET# 15,21 XDP_TDI_M XDP_TDO_R XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7 C @ 1 R481 1 R476 2 2 0_0402_5% 0_0402_5% JTAG MAPPING 2009/09/16 update 2009/2/4 #414044 DG Update Rev1.11 R125 750_0402_1% STUFF -> R488 ,R475 NO STUFF -> R480 , R481 , R476 STUFF -> R481,R476 NO STUFF -> R488, R475 , R480 2 IC,AUB_CFD_rPGA,R1P0 CONN@ STUFF -> R488 , R480 , R476 NO STUFF -> R475 , R481 CPU Only 2009/2/4 Delete dampling resistor for power noise and Layout space issue 1 2 Scan Chain (Default) GMCH Only R126 1 1.5K_0402_1% 17,21,32,36 PLT_RST# AN27 PM_DRAM_PWRGD_R H_VTTPWRGD 1 @ R540 H_PWRGD_XDP H_CPUPWRGD_0 2 PWR MANAGEMENT PWR MANAGEMENT H_CPURST# 2 0_0402_5% 2 0_0402_5% 1 AK15 DDR3 MISC H_THERMTRIP#_R 2 PROCHOT# R504 1 R510 1 D F6 SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] JTAG & BPM R124 1 0_0402_5% 18 H_THERMTRIP# AN26 CLK_CPU_DP_R CLK_CPU_DP#_R CLK_CPU_DP_R CLK_CPU_DP#_R PRDY# PREQ# H_PROCHOT# 53 H_PROCHOT# 2009/08/14 remove DP REF SSCLK 2 H_COMP3 CLOCKS 1 20_0402_1% MISC MISC R512 2 +1.05VS_VTT R127 R88 R91 2 2 2 @ 1 49.9_0402_1% 1 68_0402_5% 1 68_0402_5% H_CATERR# H_PROCHOT# H_CPURST# JP2 B 2009/8/14 change back to 2K B 1 A P U38 H_VTTPWRGD 2 5 +3VALW MC74VHC1G08DFT2G_SC70-5 4 H_VTTPWRGD_R XDP_OBS2 XDP_OBS3 1 G Y XDP_OBS0 XDP_OBS1 R550 2K_0402_1% 1 2 R542 3 51 H_VTTPWRGD XDP_PREQ# XDP_PRDY# 1K_0402_1% 2 XDP_OBS4 XDP_OBS5 #425302 CP_S3PowerReduction WhitePaper_Rev0.7 XDP_OBS6 XDP_OBS7 +3VALW P G 5 Need to check Voltage Level +1.5V_1 3 R152 @ 1.1K_0402_1% R151 H_VTTPWRGD 1 MC74VHC1G08DFT2G_SC70-5 R197 1K_0402_5% H_CPUPWRGD 1 2 H_PWRGOOD_R R84 1 2 PBTN_OUT#_XDP 15,21,36 PBTN_OUT# 0_0402_5% +1.05VS_VTT H_PWRGD_XDP 1 C211 @ 21 SMB_DATA_S3 0.1U_0402_16V4Z 21 SMB_CLK_S3 2 1.5K_0402_1% XDP_TCLK 2 2 A A Y 1 1 4 U11 B 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 XDP Connector GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 CONN@ B H_RESET#_R R83 1K_0402_5% 1 2 @ 1 2 H_CPURST# PLT_RST# R85 0_0402_5% CLK_CPU_XDP CLK_CPU_XDP# H_RESET#_R XDP_DBRESET# XDP_TDO XDP_TRST# XDP_TDI XDP_TMS +1.05VS_VTT 2 R81 1K_0402_5% 2 R79 51_0402_5% 1 1 +3VS +1.05VS_VTT A SAMTE_BSH-030-01-L-D-A 1 1 PM_DRAM_PWRGD_R 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 2 R149 2009/04/23 Intel CRB 1.55 Update Change R68 to 1.1K_1%, R71 to 3.01K_1% Compal Electronics, Inc. Compal Secret Data Security Classification 750_0402_1% 2 R148 @ 3.01K_0402_1% 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 SCHEMATICS,MB A5893 Document Number Rev C 401869 Wednesday, June 30, 2010 Sheet 1 5 of 56
  • 6.
    4 C B 10 DDR_A_BS0 10 DDR_A_BS1 10DDR_A_BS2 10 DDR_A_CAS# 10 DDR_A_RAS# 10 DDR_A_WE# A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AC3 AB2 U7 DDR_A_CAS# DDR_A_RAS# DDR_A_WE# AE1 AB3 AE9 SA_CK[0] SA_CK#[0] SA_CKE[0] SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_RAS# SA_WE# AA6 AA7 P7 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDR_A_CLK0 10 DDR_A_CLK0# 10 DDR_A_CKE0 10 SA_CK[1] SA_CK#[1] SA_CKE[1] Y6 Y5 P6 DDR_A_CLK1 10 DDR_A_CLK1# 10 DDR_A_CKE1 10 SA_CS#[0] SA_CS#[1] AE2 AE8 DDR_A_CS0# 10 DDR_A_CS1# 10 SA_ODT[0] SA_ODT[1] AD8 AF9 DDR_A_ODT0 10 DDR_A_ODT1 10 SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] DDR SYSTEM MEMORY A DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 2 B9 D7 H7 M7 AG6 AM7 AN10 AN13 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] C9 F8 J9 N9 AH7 AK9 AP11 AT13 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] C8 F9 H9 M9 AH8 AK10 AN11 AR13 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 11 DDR_B_CAS# 11 DDR_B_RAS# 11 DDR_B_WE# B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 SB_CK[0] SB_CK#[0] SB_CKE[0] DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AB1 W5 R7 AC5 Y7 AC6 V7 V6 M2 DDR_B_CLK1 11 DDR_B_CLK1# 11 DDR_B_CKE1 11 AB8 AD6 DDR_B_CS0# 11 DDR_B_CS1# 11 SB_ODT[0] SB_ODT[1] AC7 AD1 DDR_B_ODT0 11 DDR_B_ODT1 11 SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] D4 E1 H3 K1 AH1 AL2 AR4 AT8 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D5 F4 J4 L4 AH2 AL4 AR5 AR8 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C5 E3 H4 M5 AG2 AL5 AP5 AR7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] SB_CAS# SB_RAS# SB_WE# DDR_B_CLK0 11 DDR_B_CLK0# 11 DDR_B_CKE0 11 SB_CS#[0] SB_CS#[1] SB_BS[0] SB_BS[1] SB_BS[2] W8 W9 M3 SB_CK[1] SB_CK#[1] SB_CKE[1] SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] DDR_B_CAS# DDR_B_RAS# DDR_B_WE# 11 DDR_B_BS0 11 DDR_B_BS1 11 DDR_B_BS2 1 JCPU1D 11 DDR_B_D[0..63] 11 DDR_B_DM[0..7] 11 DDR_B_DQS#[0..7] 11 DDR_B_DQS[0..7] 11 DDR_B_MA[0..15] JCPU1C 10 DDR_A_D[0..63] 10 DDR_A_DM[0..7] 10 DDR_A_DQS#[0..7] 10 DDR_A_DQS[0..7] 10 DDR_A_MA[0..15] D 3 DDR SYSTEM MEMORY - B 5 U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 D C B IC,AUB_CFD_rPGA,R1P0 CONN@ IC,AUB_CFD_rPGA,R1P0 CONN@ A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 SCHEMATICS,MB A5893 Document Number Rev C 401869 Wednesday, June 30, 2010 Sheet 1 6 of 56
  • 7.
    5 4 3 2 1 JCPU1F WW15 MOW +CPU_CORE Peak 21A 48A A 1.1VRAIL POWER VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15 10U_0805_6.3V6M +CPU_CORE 1 1 C258 2 1 C274 2 1 C286 2 C282 2 10U_0805_6.3V6M 1 C288 2 1 C284 2 10U_0805_6.3V6M 1 C281 10U_0805_6.3V6M 1 2 10U_0805_6.3V6M 10U_0805_6.3V6M 1 C676 2 10U_0805_6.3V6M C677 2 1 10U_0805_6.3V6M 1 C669 2 1 C674 2 10U_0805_6.3V6M 10U_0805_6.3V6M 1 C657 2 1 C652 2 10U_0805_6.3V6M 10U_0805_6.3V6M 1 C679 2 1 C262 2 10U_0805_6.3V6M C232 2 10U_0805_6.3V6M (Place these capacitors between inductor and socket on Bottom) +CPU_CORE 1 + 10U_0805_6.3V6M 1 C268 2 + C667 1 1 C242 10U_0805_6.3V6M 1 C223 1 C257 10U_0805_6.3V6M 1 C261 1 C269 1 C275 C155 2 2 330U_X_2VM_R6M 2 2 2 2 2 2 330U_X_2VM_R6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors under CPU socket, top layer) CSC (Current Sense Configuration) 8/25 +1.05VS_VTT R436 1 R451 1 @ 2 1K_0402_1% 2 1K_0402_1% CPU_VID1 R437 1 R452 1 @ 2 1K_0402_1% 2 1K_0402_1% CPU_VID2 R438 1 R453 1 @ CPU_VID3 R439 1 R454 1 @ 2 1K_0402_1% 2 1K_0402_1% CPU_VID4 R440 1 R455 1 @ 2 1K_0402_1% 2 1K_0402_1% 22U_0805_6.3V6M C278 1 C277 1 2 2 22U_0805_6.3V6M CPU_VID5 CPU_VID6 R441 1 R456 1 R442 1 R457 1 @ @ H_DPRSLPVR R443 1 R458 1 PSI# AN33 AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 @ R444 1 R459 1 22U_0805_6.3V6M 2 1K_0402_1% 2 1K_0402_1% C157 @ G15 H_VTTVID1 C276 2 1 22U_0805_6.3V6M C270 2 1 C256 2 1 22U_0805_6.3V6M C241 2 1 C231 2 22U_0805_6.3V6M 1 2 22U_0805_6.3V6M (Place these capacitors on CPU cavity, Bottom Layer) 2 1K_0402_1% 2 1K_0402_1% 2 1K_0402_1% 2 1K_0402_1% +CPU_CORE 2 1K_0402_1% 2 1K_0402_1% 22U_0805_6.3V6M 2 1K_0402_1% 2 1K_0402_1% C222 CPU_VID0 53 CPU_VID1 53 CPU_VID2 53 CPU_VID3 53 CPU_VID4 53 CPU_VID5 53 CPU_VID6 53 H_DPRSLPVR 53 VTT_SELECT 1 22U_0805_6.3V6M H_PSI# 53 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] PROC_DPRSLPVR @ H_PSI# C +CPU_CORE 1 C651 2 1 22U_0805_6.3V6M C658 2 1 C666 2 22U_0805_6.3V6M 1 22U_0805_6.3V6M C665 2 1 C668 2 22U_0805_6.3V6M 1 2 22U_0805_6.3V6M (Place these capacitors on CPU cavity, Bottom Layer) B T8 PAD VTT Rail H_VTTVID1 = low, 1.1V H_VTTVID1 = high, 1.05V Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V +CPU_CORE ISENSE VCC_SENSE VSS_SENSE VTT_SENSE VSS_SENSE_VTT AN35 AJ34 AJ35 B15 A15 4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF) IMVP_IMON 53 VCCSENSE_R R450 1 VSSSENSE_R R449 1 1 R435 VCCSENSE VSSSENSE 2 0_0402_5% 2 0_0402_5% VTT_SENSE 51 VSS_SENSE_VTT R523 1 2 100_0402_1% 1 R448 2 100_0402_1% +CPU_CORE VCCSENSE 53 VSSSENSE 53 1 + 1 + C541 2 330U_X_2VM_R6M 2 0_0402_5% 2 1 @ 330U_X_2VM_R6M + C136 2 1 + C251 2 330U_X_2VM_R6M 330U_X_2VM_R6M C134 2 330U_X_2VM_R6M TOP side (under inductor) +CPU-CORE Decoupling SPCAP,Polymer 2009/08/01 Issued Date C,uF ESR, mohm 4X470uF 3m ohm/12 16X10uF Stuffing Option 4m ohm/4 16X22uF 3m ohm/16 2X470uF A Compal Electronics, Inc. Compal Secret Data Security Classification IC,AUB_CFD_rPGA,R1P0 CONN@ 1 + C97 MLCC 0805 X5R 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 D +1.05VS_VTT CPU_VID0 POWER B +1.05VS_VTT 10U_0805_6.3V6M 10U_0805_6.3V6M AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 +1.05VS_VTT CPU VIDS C VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 SENSE LINES D CPU CORE SUPPLY AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 Continuous 18A 4 3 2 Sheet Wednesday, June 30, 2010 1 7 of 56
  • 8.
    5 4 3 2 1 +VGFX_CORE JCPU1G 10U_0805_6.3V6M C802 0.1U_0402_16V4Z UMOP@ 2 1 UMOP@ 1 UMOP@ UMOP@ 2 2 C673 1 C672 1 UMOP@ UMOP@ 2 2 2 330U_X_2VM_R6M22U_0805_6.3V6M 10U_0805_6.3V6M C J24 J23 H25 VTT1_45 VTT1_46 VTT1_47 15A GRAPHICS GRAPHICS 091211 EMI ADD 0.1U VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 3A 1 2 2 C260 FDI 22U_0805_6.3V6M 1 AR22 AT22 GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] AM22 AP22 AN22 AP23 AM23 AP24 AN24 GFX_VR_EN GFX_DPRSLPVR GFX_IMON AR25 AT25 AM24 VCC_AXG_SENSE 52 VSS_AXG_SENSE 52 D GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6 GFXVR_EN GFXVR_DPRSLPVR_R R92 R99 52 52 52 52 52 52 52 UMOP@ 2 330_0402_5% 1 R98 Reserved for +1.5V to +1.5V_1 1 2 DIS ONLY@ +1.5V_1 GFXVR_EN 52 GFXVR_DPRSLPVR 52 GFXVR_IMON 52 2 0_0402_5% 1 22U_0805_6.3V6M VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 1U_0402_6.3V4Z 2 1K_0402_5% 1U_0402_6.3V4Z 22U_0805_6.3V6M 2 C307 1 C308 2 1 C309 2 1 C306 2 1 C310 2 1 C303 2 1 2 C315 1 2 22U_0805_6.3V6M 1.1V 2 VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58 1 1 J2 2 2 2 1 1 1U_0402_6.3V4Z 1U_0402_6.3V4Z +1.5VS 1U_0402_6.3V4Z C 22U_0805_6.3V6M Short for +1.5VS to +1.5V_1 11/03 add four 0.1u 0402 Intel suggest for S3 reduse +1.5V_1 +1.5V 1 1 1 VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68 J22 J20 J18 H21 H20 H19 VCCPLL1 VCCPLL2 VCCPLL3 L26 L27 M26 1 2 0.1U_0402_16V4Z 1 C267 0.1U_0402_16V4Z C798 2 C799 2 0.1U_0402_16V4Z 1 P10 N10 L10 K10 C797 2 C800 2 0.1U_0402_16V4Z 10U_0805_6.3V6M C283 22U_0805_6.3V6M B +1.8VS 0.6A 1.8V 2 K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25 2 +1.05VS_VTT VTT0_59 VTT0_60 VTT0_61 VTT0_62 PEG & DMI 22U_0805_6.3V6M B C285 1 @ JUMP_43X118 2 1 1 @ JUMP_43X118 + C326 330U_D2_2V_Y +1.05VS_VTT 1 2 @ JUMP_43X118 1 +1.05VS_VTT C287 +1.5V J4 J3 +1.05VS_VTT C253 VAXG_SENSE VSSAXG_SENSE - 1.5V RAILS R514 0_0402_5% DIS ONLY@ C272 DDR3 D + 1 SENSE LINES 1 2 C250 GRAPHICS VIDs C675 1 AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16 POWER 22U_0805_6.3V6M 2.2U_0603_6.3V4Z +1.8VS_VCCSFR C230 1U_0402_6.3V4Z IC,AUB_CFD_rPGA,R1P0 CONN@ 1 2 1 2 C224 1 2 1U_0402_6.3V4Z C235 1 R97 0_0805_5% 1 2 40mil C234 2 1 C233 2 22U_0805_6.3V6M 4.7U_0805_10V4Z A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 8 of 56
  • 9.
    5 4 3 2 D C B VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 JCPU1I VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30 K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9 IC,AUB_CFD_rPGA,R1P0 CONN@ VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 D C VSS NCTF JCPU1H AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35 1 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 AT35 AT1 AR34 B34 B2 B1 A35 H_NCTF1 H_NCTF2 @ @ PAD T14 PAD T19 H_NCTF6 H_NCTF7 @ @ PADT18 PAD T15 B IC,AUB_CFD_rPGA,R1P0 CONN@ A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 9 of 56
  • 10.
    5 4 3 2 1 +1.5V DIMMA VREFDQ M1Circuit JDIMM1 6 DDR_A_DQS#[0..7] +DIMM_VREFDQA +1.5V 6 DDR_A_D[0..63] 1 6 DDR_A_DM[0..7] +DIMM_VREFDQA R222 1 1 DDR_A_D0 DDR_A_D1 C402 DDR_A_DM0 0.1U_0402_16V4Z 6 DDR_A_MA[0..15] 20mil 2 C401 6 DDR_A_DQS[0..7] 1K_0402_1% 2 2 2.2U_0603_6.3V4Z DDR_A_D2 DDR_A_D3 1 DDR_A_D8 DDR_A_D9 R227 D DDR_A_DQS#1 DDR_A_DQS1 2 1K_0402_1% DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DIMMA & DIMMB VREFCA circuit +1.5V 1 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 +DIMM_VREFCA R203 DDR_A_DM3 1K_0402_1% +1.5V R201 R254 0_0402_5% 1 @ 2 1K_0402_1% DDR_A_CKE0 2 6 DDR_A_CKE0 D S DIMM_DRAMRST# 1 Q17 BSS138LT1G_SOT23-3 3 5 SM_DRAMRST# G G C 2 18 RST_GATE DIMM_DRAMRST# 11 DDR_A_BS2 6 DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 C422 RST_GATE 1 DDR_A_MA8 DDR_A_MA5 2 DDR_A_MA3 DDR_A_MA1 0.047U_0402_16V7K DDR_A_CLK0 DDR_A_CLK0# 6 DDR_A_CLK0 6 DDR_A_CLK0# DDR_A_MA10 DDR_A_BS0 6 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# 6 DDR_A_WE# 6 DDR_A_CAS# DDR_A_MA13 DDR_A_CS1# 6 DDR_A_CS1# DDR_A_D32 DDR_A_D33 Layout Note: Place near JDIMM1 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 Layout Note: Place these 4 Caps near Command and Control signals of DIMMA DDR_A_D40 DDR_A_D41 B +1.5V DDR_A_DM5 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_A_D42 DDR_A_D43 1 10U_0805_6.3V6M C355 2 1 C356 2 10U_0805_6.3V6M 1 C405 2 1 C404 2 10U_0805_6.3V6M 1 C406 2 10U_0805_6.3V6M 1 1 2 2 C362 0.1U_0402_16V4Z 1 2 C363 1 C399 2 1 C400 2 C354 1 2 + C425 330U_2.5V_M_R15 @ DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 0.1U_0402_16V4Z DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59 Layout Note: Place near JDIMM1.203 & JDIMM1.204 R218 1 2 10K_0402_5% 1U_0402_6.3V4Z 1 2 C403 2.2U_0603_6.3V4Z 1U_0402_6.3V4Z 1 2 C398 1 +3VS +0.75VS 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDR_A_D4 DDR_A_D5 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 D DDR_A_DM1 DIMM_DRAMRST# DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 R274 2 1K_0402_1% DDR_A_D26 DDR_A_D27 1 #425302 CP_S3PowerReduction WhitePaper_Rev1.0 1 2 20mil +1.5V R217 0.1U_0402_16V4Z 10K_0402_5% 205 G2 G1 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_A_CKE1 206 DDR_A_CKE1 6 DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 C DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_CLK1 DDR_A_CLK1# DDR_A_CLK1 6 DDR_A_CLK1# 6 DDR_A_BS1 DDR_A_RAS# DDR_A_BS1 6 DDR_A_RAS# 6 DDR_A_CS0# DDR_A_ODT0 DDR_A_CS0# 6 DDR_A_ODT0 6 DDR_A_ODT1 +DIMM_VREFCA DDR_A_ODT1 6 20mil DDR_VREF_CA_DIMMA R202 1 2 0_0402_5% DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 C358 2.2U_0603_6.3V4Z DDR_A_D44 DDR_A_D45 1 1 2 2 C361 0.1U_0402_16V4Z B DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK PM_EXTTS#0_1 5,11 D_CK_SDATA 11,12 D_CK_SCLK 11,12 +0.75VS FOX_AS0A626-U8RN-7F A 2 A CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 1 C391 2 1 C388 2 1 C397 2 1 C396 1 2 2 DDR3 SO-DIMM A H=8mm C394 10U_0805_6.3V6M 2009/08/01 Issued Date 1U_0402_6.3V4Z Compal Electronics, Inc. Compal Secret Data Security Classification 1U_0402_6.3V4Z 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Sheet Wednesday, June 30, 2010 1 10 of 56
  • 11.
    5 4 3 2 1 +1.5V +1.5V JDIMM2 2008/9/8 #400755 Calpella Clarksfield DDR3SO-DIMM VREFDQ Platform Design Guide Change Details 6 DDR_B_DQS#[0..7] 6 DDR_B_D[0..63] 6 DDR_B_DM[0..7] 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 C433 2.2U_0603_6.3V4Z 6 DDR_B_DQS[0..7] 1 C431 2 DDR_B_D0 DDR_B_D1 1 DDR_B_DM0 2 DDR_B_D2 DDR_B_D3 6 DDR_B_MA[0..15] 0.1U_0402_16V4Z DDR_B_D8 DDR_B_D9 D DDR_B_DQS#1 DDR_B_DQS1 DIMMB VREFDQ M1 Circuit DDR_B_D10 DDR_B_D11 +1.5V 1 DDR_B_D16 DDR_B_D17 +DIMM_VREFDQB R282 DDR_B_DQS#2 DDR_B_DQS2 1K_0402_1% DDR_B_D18 DDR_B_D19 1 2 20mil DDR_B_D24 DDR_B_D25 R281 1K_0402_1% 2 DDR_B_DM3 DDR_B_D26 DDR_B_D27 DDR_B_CKE0 6 DDR_B_CKE0 DDR_B_BS2 6 DDR_B_BS2 C DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 DDR_B_CLK0 DDR_B_CLK0# 6 DDR_B_CLK0 6 DDR_B_CLK0# DDR_B_MA10 DDR_B_BS0 6 DDR_B_BS0 DDR_B_WE# DDR_B_CAS# 6 DDR_B_WE# 6 DDR_B_CAS# Layout Note: Place near JDIMM2 DDR_B_MA13 DDR_B_CS1# 6 DDR_B_CS1# Layout Note: Place these 4 Caps near Command and Control signals of DIMMB DDR_B_D32 DDR_B_D33 +1.5V 10U_0805_6.3V6M 0.1U_0402_16V4Z DDR_B_DQS#4 DDR_B_DQS4 0.1U_0402_16V4Z DDR_B_D34 DDR_B_D35 1 10U_0805_6.3V6M C436 10U_0805_6.3V6M 2 2 1 C420 2 1 C418 2 1 C416 2 1 C429 2 1 2 C430 1 C417 2 1 C419 2 1 2 + C395 330U_2.5V_M_R15 DDR_B_D40 DDR_B_D41 2 C437 1 C435 B 1 DDR_B_DM5 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z DDR_B_D42 DDR_B_D43 0.1U_0402_16V4Z DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 Layout Note: Place near JDIMM2.203 & JDIMM2.204 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 +0.75VS DDR_B_DM7 1U_0402_6.3V4Z DDR_B_D58 DDR_B_D59 C413 1 2 1U_0402_6.3V4Z C412 1 C427 2 1 2 C426 1 1 C411 R279 1 +3VS 2 2 10U_0805_6.3V6M R278 C432 1 1 1 C428 A 2.2U_0603_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 2 0.1U_0402_16V4Z 2 10K_0402_5% 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 G1 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 G2 DDR_B_D4 DDR_B_D5 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D6 DDR_B_D7 DDR_B_D12 DDR_B_D13 D DDR_B_DM1 DIMM_DRAMRST# 2009/08/01 DIMM_DRAMRST# 10 DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21 DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 DDR_B_CKE1 206 DDR_B_CKE1 6 DDR_B_MA15 DDR_B_MA14 C DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_CLK1 DDR_B_CLK1# DDR_B_BS1 DDR_B_RAS# DDR_B_CS0# DDR_B_ODT0 DDR_B_ODT1 20mil DDR_B_CLK1 6 DDR_B_CLK1# 6 DDR_B_BS1 6 DDR_B_RAS# 6 DDR_B_CS0# 6 DDR_B_ODT0 6 DDR_B_ODT1 6 DDR_VREF_CA_DIMMB R270 1 +DIMM_VREFCA 2 0_0402_5% DDR_B_D36 DDR_B_D37 DDR_B_DM4 DDR_B_D38 DDR_B_D39 C414 2.2U_0603_6.3V4Z DDR_B_D44 DDR_B_D45 1 1 2 2 C415 0.1U_0402_16V4Z B DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK PM_EXTTS#0_1 5,10 D_CK_SDATA 10,12 D_CK_SCLK 10,12 +0.75VS A DDR3 SO-DIMM B H=4mm FOX_AS0A626-U4RN-7F CONN@ Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 2 10K_0402_5% VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 205 +DIMM_VREFDQB 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Sheet Wednesday, June 30, 2010 1 11 of 56
  • 12.
    A B C D E F G H SM010014520 3000ma 220ohm@100mhzDCR 0.04 +1.05VS_VTT 1 +CLK_3VS SM010014520 3000ma 220ohm@100mhz DCR 0.04 +CLK_1.05VS 40mil 40mil 0.1U_0402_16V4Z L76 2 1 FBMA-L11-201209-221LMA30T_0805 1 1 1 1 C774 C757 C770 C782 10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 L69 2 1 FBMA-L11-201209-221LMA30T_0805 +3VS 1 C737 1 1 2 C740 10U_0805_10V4Z 2 2 10U_0805_10V4Z 1 2 1 40mil 0.1U_0402_16V4Z C768 C781 10U_0805_10V4Z C741 2 L75 2 1 FBMA-L11-201209-221LMA30T_0805 +1.5VS 1 0.1U_0402_16V4Z L74 2 1 FBMA-L11-201209-221LMA30T_0805 +CLK_1.5VS @ SM010014520 3000ma 220ohm@100mhz DCR 0.04 C750 10U_0805_10V4Z 1 1 2 2 C742 1 1 C771 2 2 C769 0.1U_0402_16V4Z 0.1U_0402_16V4Z +CLK_3VS 2 2 +CLK_3VS Clock Generator +CLK_1.5VS U47 14 CLK_BUF_DREF_96M 14 CLK_BUF_DREF_96M# 22 27M_CLK 22 27M_SSC 14 CLK_BUF_PCIE_SATA 14 CLK_BUF_PCIE_SATA# 14 CLK_BUF_CPU_DMI 14 CLK_BUF_CPU_DMI# CLK_BUF_DREF_96M CLK_BUF_DREF_96M# R717 0_0402_5% @ 1 2 1 2 R716 0_0402_5% @ 27M_CLK_R 27M_SSC_R CLK_BUF_PCIE_SATA CLK_BUF_PCIE_SATA# CLK_BUF_CPU_DMI CLK_BUF_CPU_DMI# +CLK_1.05VS H_STP_CPU# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 SCL SDA REF_0/CPU_SEL VDD_REF XTAL_IN XTAL_OUT VSS_REF CKPWRGD/PD# 32 31 30 29 28 27 26 25 VDD_CPU CPU_0 CPU_0# VSS_CPU CPU_1 CPU_1# VDD_CPU_IO VDD_SRC VDD_USB_48 VSS_48M DOT_96 DOT_96# VDD_27 27MHZ 27MHZ_SS USB_48 24 23 22 21 20 19 18 17 VSS_27M SATA SATA# VSS_SRC SRC_1 SRC_1# VDD_SRC_IO CPU_STOP# D_CK_SCLK D_CK_SDATA REF_0/CPU_SEL R682 1 D_CK_SCLK 10,11 D_CK_SDATA 10,11 CLK_BUF_ICH_14M 14 2 33_0402_5% CLK_XTAL_IN CLK_XTAL_OUT CK505_PWRGD CLK_BUF_CPU_BCLK CLK_BUF_CPU_BCLK# CLK_BUF_CPU_BCLK 14 CLK_BUF_CPU_BCLK# 14 +CLK_1.05VS +CLK_1.5VS IDT SA00003HR00 TGND SLG8SP587VTR_QFN32_5X5 IDT: 9LRS3199AKLFT, SA000030P00 3 3 SILEGO: SLG8SP587V(WF), SA00002XY10 +3VS Low Power: +3VS R678 4.7K_0402_5% 1 2 1 1 3 2 S D_CK_SCLK Y4 14.31818MHZ 20PF 7A14300003 Q45 2N7002E-T1-GE3_SOT23-3 133MHz 100MHz 14,21,34 PCH_SMBCLK CLK_XTAL_IN +3VS 1 R677 4.7K_0402_5% 1 2 D CPU_1 133MHz VGATE 15,53 2 CLK_ENABLE# 53 G Q48 2N7002E-T1-GE3_SOT23-3 C755 1 27P_0402_50V8J C762 27P_0402_50V8J 2 1 100MHz Change to 5x3.2 2009/08/01 Deciphered Date 4 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date CLK_XTAL_OUT 2 0 (Default) CPU_0 R691 0_0402_5% @ 1 2 +3VS 2 10K_0402_5% REF_0/CPU_SEL PIN 30 4 S Q46 2N7002E-T1-GE3_SOT23-3 2 G R683 1 D_CK_SDATA 3 FOR Realtek CK505_PWRGD D +3VS S 14,21,34 PCH_SMBDATA 1 D IDT Have Internal Pull-Down 1 +3VS H_STP_CPU# 1 2 10K_0402_5% 2 G R690 1 R693 10K_0402_5% Realtek: RTM890N-631-VB-GRT, SA00003HQ10 Silego Have Internal Pull-Up 3 IDT 9LVS3199AKLFT NC 2 IDT: 9LVS3199AKLFT, SA00003HR00 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: A B C D E F Wednesday, June 30, 2010 G Sheet 12 of H 56
  • 13.
    5 4 3 2 1 +RTCBATT PCH_RTCRST# PCH_RTCX1 OSC 4 NC OSC 1 R615 2 32.768KHZ_12.5PF_Q13MC14610002 C722 2 1 D U41A 10M_0402_5% +RTCBATT_R REV1.0 FWH0 / LAD0 FWH1/ LAD1 FWH2 / LAD2 FWH3 / LAD3 D33 B33 C32 A32 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 FWH4 / LFRAME# B13 D13 PCH_RTCX2 C34 LPC_FRAME# LDRQ0# LDRQ1# / GPIO23 A34 F34 SERIRQ AB9 SERIRQ SATA0RXN SATA0RXP SATA0TXN SATA0TXP AK7 AK6 AK11 AK9 SATA_DTX_C_PRX_N0 SATA_DTX_C_PRX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 SATA_DTX_C_PRX_N0 31 SATA_DTX_C_PRX_P0 31 SATA_PTX_DRX_N0 31 SATA_PTX_DRX_P0 31 SATA1RXN SATA1RXP SATA1TXN SATA1TXP AH6 AH5 AH9 AH8 SATA_DTX_C_PRX_N1 SATA_DTX_C_PRX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 SATA_DTX_C_PRX_N1 31 SATA_DTX_C_PRX_P1 31 SATA_PTX_DRX_N1 31 SATA_PTX_DRX_P1 31 SATA2RXN SATA2RXP SATA2TXN SATA2TXP AF11 AF9 AF7 AF6 SATA3RXN SATA3RXP SATA3TXN SATA3TXP AH3 AH1 AF3 AF1 SATA4RXN SATA4RXP SATA4TXN SATA4TXP AD9 AD8 AD6 AD5 SATA5RXN SATA5RXP SATA5TXN SATA5TXP AD3 AD1 AB3 AB1 RTCX1 RTCX2 18P_0402_50V8J close to RAM door modify to 330K 1 2 R675 @ 10K_0603_5% C365 1U_0603_10V6K 1 2 RTCRST# PCH_SRTCRST# +RTCVCC RC Delay 18~25mS C14 D17 SRTCRST# R213 1 2 1M_0402_5% SM_INTRUDER# A16 INTRUDER# R212 1 2 330K_0402_1% PCH_INTVRMEN A14 INTVRMEN HDA_BITCLK_PCH A30 HDA_BCLK HDA_SYNC_PCH D29 HDA_SYNC R327 1 2 33_0402_5% 2 33_0402_5% 39 PCH_SPKR (SPKR Have internal Pull-Down) 39 HDA_RST_AUDIO# 1 R328 PCH_SPKR 1 HDA_RST_PCH# 2 33_0402_5% P1 SPKR C30 HDA_RST# G30 39 HDA_SDIN0 HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 F32 HDA_SDIN3 HDA_SDOUT_PCH B29 HDA_SDO PCH_GPIO33# H32 HDA_DOCK_EN# / GPIO33 J30 HDA_DOCK_RST# / GPIO13 M3 JTAG_TCK K3 JTAG_TMS 21 PCH_JTAG_TDI K1 JTAG_TDI 21 PCH_JTAG_TDO J2 JTAG_TDO J4 TRST# HDA_SDO ,This signal has a weak internal pull-down resistor. Should not be Pull High C IHDA F30 E32 PCH_SPKR Have internal PD SERIRQ 39 HDA_SDOUT_AUDIO R324 If GPIO33 pull down, ME will not working. For factory update ME, pull down resistor pull under door. 1 2 33_0402_5% GPIO33 can not pull down (manufacturing environments) 1 PCH_GPIO33# D 2 G PCH_JTAG_TCK 21 PCH_JTAG_TCK Q39 21 PCH_JTAG_TMS S 2N7002E-T1-GE3_SOT23-3 3 1 36 ME_OVERRIDE 2 21 PCH_JTAG_RST# GPIO33 has a weak internal pull-up NOTE: Asserting the GPIO33 low on the rising edge of PWROK will also halt Intel Management Engine after chipset bringup and disable runtime Intel Management Engine features. This is a debug mode and must not be asserted after manfacturing/ debug. +1.05VS_PCH PCH_SPI_CLK_1 R665 1 2 0_0402_5% PCH_SPI_CLK PCH_SPI_CS0# 2 15_0402_5% PCH_SPI_CS0#_R AV3 2009/08/23 Debug Port DG1.7 P27.28 R662 1 T24 PAD PCH_SPI_MOSI_1 R664 1 TDO,TDI,TMS Pull Up for Production Units PCH_SPI_MISO_1 R661 1 unpop TDO,TDI,TMS resister PCH_SPI_CS1# @ BA2 1 SERIRQ 36 AY3 SATAICOMPI AF15 R205 1 PCH_SPI_MOSI AY1 SATA_COMP 2 10K_0402_5% +3VS SATALED# SPI_MOSI 2 33_0402_5% PCH_SPI_MISO AV1 @ 1 R644 1 R724 1 R722 PCH_JTAG_TDO 51_0402_5% 2 200_0402_5% 2 100_0402_5% 2 @ 1 R645 1 R728 1 R727 T3 PCH_SATALED# 37 SATA0GP / GPIO21 Y9 GPIO21 Project ID2 SPI_MISO SATA1GP / GPIO19 V1 PCH_JTAG_TDI 51_0402_5% 2 20K_0402_5% 2 10K_0402_5% 2 @ 1 R643 1 R721 1 R723 PCH_JTAG_RST# PCH_GPIO21 21 PCH_GPIO19 21 +3VS B 2 10K_0402_5% R259 NonSG@ 10K_0402_5% R268 @ 10K_0402_5% +3VS U18 +3VS R301 1 R271 1 2 3.3K_0402_5% 2 3.3K_0402_5% PCH_SPI_CS0# SPI_WP1# SPI_HOLD1# 1 3 7 4 CS# WP# HOLD# GND VCC SCLK SI SO 8 6 5 2 PCH_SPI_CLK_1 PCH_SPI_MOSI_1 PCH_SPI_MISO_1 PCH_SPI_CLK_1 @ 2 10P_0402_50V8J GPIO19 OPT PCH_JTAG_TCK 1 C729 dGPU iGPU SG GPIO37 PCH_GPIO19 MX25L3205DM2I-12G SOP 8P SA000021A00 SPI ROM Footprint 200mil R647 +3VS R267 1 R260 1 SGOPT@ 10K_0402_5% 2 TDO: Reserved on ES1 Sample Mount R724, R722 on ES2 Sample MP mount R646, R644, R645, R643 and remove others SATA for ODD 2 37.4_0402_1% PCH_SATALED# R652 1 SPI_CS1# 2 15_0402_5% SATA for HDD1 AF16 2 PCH_JTAG_TMS 51_0402_5% 2 200_0402_5% 2 100_0402_5% 2 1 20mil 0.1U_0402_16V4Z +1.05VS_PCH SATAICOMPO IBEXPEAK-M_FCBGA107 1 R646 1 R726 1 R725 2 2 +CHGRTC C724 2/10 SATA2, SATA3 not support on HM55 2008 Intel MOW36/MOW50 @ 4.7K_0402_5% VGA_PRSNT_L# 0 0 1 0 1 0 A S3 CRB 1.1 Change to 4.7K @ 1 R663 PCH_SPI_MOSI Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MOSI This signal has a weak internal pull-down resistor. This signal must be sampled low. 5 2009/08/01 Issued Date enable iTPM: SPI_MOSI High Compal Electronics, Inc. Compal Secret Data Security Classification 1K_0402_5% 2 D C SPI_CS0# +3V 51_0402_5% 2 200_0402_5% 2 100_0402_5% 2 A 20mil LPC_FRAME# 36 SPI_CLK SPI B D8 BAS40-04_SOT23-3 +RTCVCC 1 R580 100K_0402_5% JTAG 1 2 R237 10K_0402_5% 36 36 36 36 1 R330 SATA 39 HDA_BITCLK_AUDIO HDA_SYNC On Die PLL VR is supplied by 1.5V when sampled High, 1.8V when sampled Low. R650 1K_0402_5% @ 1 2 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 INTVRMEN - Integrated SUS 1.05V VRM Enable High - Enable Internal VRs HDA for AUDIO (HDA_SYNC Have internal Pull-Down) 39 HDA_SYNC_AUDIO +3VS LPC PCH_RTCRST# RTC +RTCVCC PCH_SRTCRST# 1 2 R214 20K_0402_1% 1 NC 2 1 1 3 2 1 2 R671 @ 10K_0603_5% C366 1U_0603_10V6K 1 2 R336 1K_0402_5% 20mil X2 3 close to RAM door 2 C723 18P_0402_50V8J 2 1 RC Delay 18~25mS 2 1 2 R215 20K_0402_1% +RTCVCC Rev C 401869 Date: 4 3 2 Wednesday, June 30, 2010 Sheet 1 13 of 56
  • 14.
    4 3 REV1.0 PERN7 PERP7 PETN7 PETP7 2 0_0402_5% R266 1 PCH_GPIO73 20_0402_5% P9 AM43 AM45 34 CLK_PCIE_MINI1# 34 CLK_PCIE_MINI1 For Wireless LAN 34 MINI1_CLKREQ# 21 PCH_GPIO18 PCH_GPIO18 U4 AM47 AM48 PCH_GPIO20 21 PCH_GPIO20 N4 AH42 AH41 PCH_GPIO25 2009/08/25: Change back to +3V remove mini2 +3V 2009/08/25: remove mini2 clk 1 B A8 R241 MINI2_CLKREQ#_1 AM51 AM53 M9 SMBus C6 G8 D M14 PCH_GPIO74 SML1CLK / GPIO58 E10 PCH_SML1CLK SML1DATA / GPIO75 G12 PCH_SML1DAT DGPU_PWR_EN +3V 1 T13 T11 CL_RST1# T9 H1 10K_0402_5% PEG_CLKREQ#_R 1 1 AD43 AD45 CLKOUT_DMI_N CLKOUT_DMI_P CLK_CPU_DMI# 5 CLK_CPU_DMI 5 CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P CLKOUT_PCIE0N CLKOUT_PCIE0P PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P PCIECLKRQ1# / GPIO18 CLKOUT_PCIE2N CLKOUT_PCIE2P 2N7002E-T1-GE3_SOT23-3 AW24 BA24 CLKIN_BCLK_N CLKIN_BCLK_P AP3 AP1 CLK_BUF_CPU_BCLK# 12 CLK_BUF_CPU_BCLK 12 CLKIN_DOT_96N CLKIN_DOT_96P F18 E18 CLK_BUF_DREF_96M# 12 CLK_BUF_DREF_96M 12 AH13 AH12 CLK_BUF_PCIE_SATA# 12 CLK_BUF_PCIE_SATA 12 REFCLK14IN CLKIN_PCILOOPBACK J42 1 R163 XTAL25_IN XTAL25_OUT PCIECLKRQ4# / GPIO26 AF38 2 10_0402_5% 1 C319 10K_0402_5% 2 10K_0402_5% 2 H6 1 R265 MINI1_CLKREQ# PCH_GPIO20 1 R649 AK53 AK51 PCH_GPIO56 Schematic_Checklist_Rev1.6 GPIO18 GPIO25 Main (core) power well (+V3.3S) Muxed with PCIECLKRQ1#. If not used, requires 8.2-k to 10-k pull-up to +Vcc_3.3 (+V3.3S) Resume (Sus) well (+V3.3A) P13 PCIECLKRQ5# / GPIO44 CLKOUT_PEG_B_N CLKOUT_PEG_B_P PEG_B_CLKRQ# / GPIO56 XCLK_RCOMP R170 1 2 90.9_0402_1% CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 T42 CLKOUTFLEX3 / GPIO67 1 R623 1 R602 1 R626 10K_0402_5% 2 1 R208 1 R639 1 R249 PCH_SML1CLK PCH_SML1DAT 10K_0402_5% 2 1 R207 PCH_GPIO74 2.2K_0402_5% 2.2K_0402_5% 1 R624 5 PCH_GPIO25 *Discrete *Optimus 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 1 R244 1 R206 1 R257 4 PCH_GPIO44 PCH_GPIO56 PCH_GPIO73 2 C694 27P_0402_50V8J UMOP@ +3VS 0 GPIO66 ID0 0 PCH_SML1CLK 2009/08/01 6 Structure 1 NEW70 1 +3VS NEW80 1 0 NEW90 1 0 0 NEW71/91 1 1 0 Deciphered Date EC_SMB_CK2 EC_SMB_CK2 22,36 Q19A 2N7002DWH_SOT363-6 PCH_SML1DAT Pull high +3VS at KB926 side 3 4 EC_SMB_DA2 EC_SMB_DA2 22,36 Q19B 2N7002DWH_SOT363-6 NEW71/91 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 2009/08/13: Change back to +3V Change to 5x3.2 1 PCH_GPIO60 2 2 GPIO65 ID1 0 0 EC_LID_OUT# PCH_SMBCLK PCH_SMBDATA B Y2 25MHZ_20PF_7A25000012 UMOP@ 2 10K_0402_5% R144 1 2 10K_0402_5% NonOPT@ R157 1 2 10K_0402_5% @ R167 1 2 10K_0402_5% PROJECT_ID0 Project Structure GPIO21 ID2 0 10K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 10K_0402_5% 2 OPT@ +3VS R564 1M_0402_5% UMOP@ IBEXPEAK-M_FCBGA107 0 9/1: Change to +3VS R156 1 +1.05VS_PCH N50 +3V +3V Project Structure ID T45 P43 PROJECT_ID1 Muxed with PCIECLKREQ3# If not used, requires 8.2-k to 10-k pull-up to +V3.3A rail. A C693 UMOP@ 27P_0402_50V8J 1 2 XTAL25_IN XTAL25_OUT 2 PCH_GPIO44 CLKOUTFLEX0 / GPIO64 1109 RF request 5 +3VS CLKOUT_PCIE5N CLKOUT_PCIE5P R563 DIS ONLY@ 0_0402_5% 1 2 12 2 10P_0402_50V8J CLK_PCI_FB 17 AH51 AH53 XCLK_RCOMP CLKOUT_PCIE4N CLKOUT_PCIE4P 6/9 MOW23 Request add 25MHz crystal supporting Integrated Graphics CLK_BUF_ICH_14M P41 CLKOUT_PCIE3N CLKOUT_PCIE3P PCIECLKRQ3# / GPIO25 C CLK_BUF_CPU_DMI# 12 CLK_BUF_CPU_DMI 12 CLKIN_DMI_N CLKIN_DMI_P Clock Flex 2 AJ50 AJ52 PEG_CLKREQ# 22 R276 @ 2.2K_0402_5% AT1 AT3 CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P PCIECLKRQ2# / GPIO20 3 Q18 R247 DIS@ @ 2.2K_0402_5% CLK_PEG_VGA# 22 CLK_PEG_VGA 22 AN4 AN2 CLKOUT_PEG_A_N CLKOUT_PEG_A_P 10K_0402_5% MINI2_CLKREQ#_1 R275 DIS@ 10K_0402_5% R636 2 G Link Controller CL_CLK1 CL_DATA1 PEG_A_CLKRQ# / GPIO47 PERN8 PERP8 PETN8 PETP8 18,21,38,42 1 SML1ALERT# / GPIO74 1 R258 1 SML0CLK 2 32 LAN_CLKREQ# PCH_GPIO60 1 AK48 AK47 32 CLK_PCIE_LAN# 32 CLK_PCIE_LAN For PCIE LAN PCH_SMBDATA 12,21,34 J14 2 C PCH_SMBDATA SML0DATA PEG BG34 BJ34 BG36 BJ36 PCH_SMBCLK 12,21,34 C8 EC_LID_OUT# 36 2 AT34 AU34 AU36 AV36 2/10 PCIE7, PCIE8 not support on HM55 SML0ALERT# / GPIO60 PCH_SMBCLK 1 PERN6 PERP6 PETN6 PETP6 SMBDATA H14 1. Connect Directly EXPRESS CARD, MINI1, MINI2 2. Level Shift1, Pull-Up to +3VS CLOCK GEN, DIMM1, DIMM2 3. Level Shift2, Pull-Up to +3VS LAN 4. Level Shift3, Pull-Up to +3VS CPU & PCH XDP 2 PERN5 PERP5 PETN5 PETP5 2009/08/25: remove PCIE5 For Mini2 SMBCLK EC_LID_OUT# S PERN4 PERP4 PETN4 PETP4 SMBALERT# / GPIO11 B9 D PERN3 PERP3 PETN3 PETP3 D PERN1 PERP1 PETN1 PETP1 PCI-E* C332 2 C334 2 PERN2 PERP2 PETN2 PETP2 BF33 BH33 BG32 BJ32 2 2 From CLK BUFFER PCIE_DTX_C_PRX_N2 PCIE_DTX_C_PRX_P2 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 1 1 BA34 AW34 BC34 BD34 34 34 34 34 C335 C339 PCIE_DTX_C_PRX_N2 AW30 PCIE_DTX_C_PRX_P2 BA30 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BC30 0.1U_0402_16V7K PCIE_PTX_DRX_P2 BD30 BA32 BB32 BD32 BE32 For Wireless LAN PCIE_DTX_C_PRX_N1 PCIE_DTX_C_PRX_P1 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 1 1 AU30 AT30 AU32 AV32 32 32 32 32 For PCIE LAN 1 2 U41B PCIE_DTX_C_PRX_N1 PCIE_DTX_C_PRX_P1 0.1U_0402_16V7K PCIE_PTX_DRX_N1 0.1U_0402_16V7K PCIE_PTX_DRX_P1 BG30 BJ30 BF29 BH29 2 2 5 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 3 2 Wednesday, June 30, 2010 Sheet 1 14 of 56 A
  • 15.
    5 4 3 DMI_HTX_PRX_P[0..3] 4 DMI_HTX_PRX_P[0..3] DMI_PTX_HRX_N[0..3] 4 DMI_PTX_HRX_N[0..3] DMI_PTX_HRX_P[0..3] 4DMI_PTX_HRX_P[0..3] H_FDI_TXN[0..7] U41C H_FDI_TXP[0..7] DMI_HTX_PRX_N0 BC24 DMI_HTX_PRX_N1 BJ22 DMI_HTX_PRX_N2 AW20 DMI_HTX_PRX_N3 BJ20 DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3 BD22 BH21 BC20 BD18 DMI0TXP DMI1TXP DMI2TXP DMI3TXP @ 4 BJ12 H_FDI_LSYNC0 4 BG14 H_FDI_LSYNC1 4 DMI_IRCOMP T6 SYS_RESET# WAKE# SYS_PWROK_R 1 0_0402_5% 1 0_0402_5% M6 SYS_PWROK B17 K5 LAN_RST# A10 D9 5 PM_DRAM_PWRGD PCH_RSMRST# 36 SUS_PWR_DN_ACK H_FDI_FSYNC1 XDP_DBRESET# SYS_PWROK B BH13 C16 SUS_PWR_DN_ACK M1 PWROK MEPWROK LAN_RST# DRAMPWROK RSMRST# 36 EC_SWI# Y1 PM_CLKRUN# SUS_STAT# / GPIO61 P8 PCH_GPIO61 SUSCLK PCH_ACIN P7 4 C 32,34 PM_CLKRUN# 36 @ PAD T10 SUSCLK / GPIO62 SLP_S5# / GPIO63 E4 PM_SLP_S5# 36 SLP_S4# H7 PM_SLP_S4# 36 SLP_S3# P12 SLP_M# K8 PM_SLP_M# @ PAD T11 TP23 N2 PM_SLP_DSW# @ PAD T22 ACPRESENT / GPIO31 A6 BATLOW# / GPIO72 SUSCLK 36 PM_SLP_S3# 36 B @ 1 0_0402_5% R605 2 Q41 MMBT3906_SOT23-3 PCH_RSMRST# 1 3 EC_RSMRST# 36 E PWRBTN# PCH_PCIE_WAKE# F3 SUS_PWR_DN_ACK / GPIO30 P5 PCH_GPIO72 5,21,36 PBTN_OUT# 2 10K_0402_5% 2 D6 CH751H-40PT_SOD323-2 PCH_PCIE_WAKE# CLKRUN# / GPIO32 PBTN_OUT# 1 R240 1 J12 4 EC_SWI# F14 PMSYNCH RI# SLP_LAN# / GPIO29 BJ10 F6 H_PM_SYNC 5 2 B R620 2 R631 2 H_FDI_FSYNC0 FDI_FSYNC1 DMI_ZCOMP H_FDI_INT C BF25 BJ14 BF13 FDI_LSYNC1 BH25 DMI_COMP FDI_INT 09/09/14 WW37 PCH WAKE# PU 10K SYS_PWROK VGATE 36 EC_ACIN H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7 FDI_FSYNC0 FDI R600 49.9_0402_1% 1 2 5,21 XDP_DBRESET# +3V BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12 R604 10K_0402_5% PM_SLP_LAN# 1 R598 IBEXPEAK-M_FCBGA107 2 4.7K_0402_5% +3V D20A 2 C DMI0TXN DMI1TXN DMI2TXN DMI3TXN D H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7 FDI_LSYNC0 +1.05VS_PCH SUS_PWR_DN_ACK 2 10K_0402_5% PCH_GPIO72 2 8.2K_0402_5% EC_SWI# 2 10K_0402_5% PCH_PCIE_WAKE# 2 10K_0402_5% PM_SLP_LAN# 2 10K_0402_5% BE22 BF21 BD20 BE18 BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2 DMI_PTX_HRX_P3 +3V BD24 BG22 BA20 BG20 DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3 PM_CLKRUN# 2 8.2K_0402_5% FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 1 +3VS REV1.0 DMI0RXN DMI1RXN DMI2RXN DMI3RXN DMI 4 H_FDI_TXP[0..7] System Power Management 4 H_FDI_TXN[0..7] D 1 R648 1 R628 1 R198 1 R641 1 @ R248 1 DMI_HTX_PRX_N[0..3] 4 DMI_HTX_PRX_N[0..3] 1 R657 2 1 6 2 BAV99DW-7_SOT363 D20B 4 A Y 1 VGATE 4 3 EC_PWROK 36,38 5 VGATE 12,53 R591 2.2K_0402_5% BAV99DW-7_SOT363 MC74VHC1G08DFT2G_SC70-5 2 3 21 SYS_PWROK EC_PWROK 1 U44 2 P SYS_PWROK B G 5 +3VS A SYS_PWROK 1 R606 2 10K_0402_5% EC_PWROK 1 R632 2 10K_0402_5% LAN_RST# 1 R617 2 10K_0402_5% Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. No used Integrated LAN, connecting LAN_RST# to GND Rev C 401869 Date: 5 A 4 3 2 Wednesday, June 30, 2010 Sheet 1 15 of 56
  • 16.
    5 4 3 2 1 U41D IGPU_BKLT_EN T48 T47 28 DPST_PWM L_BKLTCTL PCH_LCD_CLK PCH_LCD_DATA AB48 Y45 AB46 V48 SDVO_STALLN SDVO_STALLP SDVO_INTN SDVO_INTP AP39 AP41 LVD_VREF AT43 AT42 LVD_VREFH LVD_VREFL SDVO_CTRLCLK SDVO_CTRLDATA R131 1 @ 22.2K_0402_5% PCH_LCD_DATA 2 10K_0402_5% LCTLA_CLK R132 1 R133 1 2 10K_0402_5% 2 2.2K_0402_5% LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 PCH_TXOUT0+ PCH_TXOUT1+ PCH_TXOUT2+ BB48 BA50 AY49 AV48 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 AA52 AB53 AD53 CRT_BLUE CRT_GREEN CRT_RED PCH_CRT_CLK 2 2.2K_0402_5% BB47 BA52 AY48 AV47 LCTLB_DATA R546 1 R545 1 C 28 PCH_TXOUT0+ 28 PCH_TXOUT1+ 28 PCH_TXOUT2+ PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2- PCH_CRT_DATA R551 R552 R553 1 1 1 UMOP@ UMOP@ UMOP@ PCH_CRT_B 150_0402_1% PCH_CRT_G 150_0402_1% PCH_CRT_R 150_0402_1% 2 2 2 29 PCH_CRT_B 29 PCH_CRT_G 29 PCH_CRT_R 29 PCH_CRT_CLK 29 PCH_CRT_DATA PCH_CRT_B PCH_CRT_G PCH_CRT_R PCH_CRT_CLK PCH_CRT_DATA B ENBKL R135 1 UMOP@ 2 0_0402_5% V51 V53 1 UMA ONLY & OPTIMUS USE DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38 PCH_DPB_N0 PCH_DPB_P0 PCH_DPB_N1 PCH_DPB_P1 PCH_DPB_N2 PCH_DPB_P2 PCH_DPB_N3 PCH_DPB_P3 DDPC_CTRLCLK DDPC_CTRLDATA Y49 AB49 DDPC_AUXN DDPC_AUXP DDPC_HPD BE44 BD44 AV40 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P 2 100K_0402_5% BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36 PCH_DPB_HPD C313 C305 C320 C323 C317 C314 C327 C325 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 UMOP@ UMOP@ UMOP@ UMOP@ UMOP@ UMOP@ UMOP@ UMOP@ 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 30 PCH_TMDS_D2# 30 PCH_TMDS_D2 30 PCH_TMDS_D1# 30 PCH_TMDS_D1 30 PCH_TMDS_D0# 30 PCH_TMDS_D0 30 PCH_TMDS_CK# 30 PCH_TMDS_CK 30 HDMI D2 HDMI D1 HDMI D0 HDMI CLK C U50 U52 DDPD_AUXN DDPD_AUXP DDPD_HPD REV1.0 BC46 BD46 AT38 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36 B 1 R143 1K_0402_0.5% 2 2 R103 1 DIS ONLY@ 2 R171 1 IBEXPEAK-M_FCBGA107 R134 100K_0402_5% ENBKL DAC_IREF CRT_IRTN SDVO_SCLK 30 SDVO_SDATA 30 PCH_DPB_HPD CRT_HSYNC CRT_VSYNC CRT_IREF AD48 AB51 IGPU_BKLT_EN T51 T53 BG44 BJ44 AU38 CRT_DDC_CLK CRT_DDC_DATA Y53 Y51 29 PCH_CRT_HSYNC 29 PCH_CRT_VSYNC D DDPB_AUXN DDPB_AUXP DDPB_HPD DDPD_CTRLCLK DDPD_CTRLDATA CRT PCH_LCD_CLK LVDSA_CLK# LVDSA_CLK AY51 AT48 AU50 AT51 2 2.2K_0402_5% AV53 AV51 AY53 AT49 AU52 AT53 @ 28 PCH_TXOUT028 PCH_TXOUT128 PCH_TXOUT2- PCH_TXCLKPCH_TXCLK+ AP48 AP47 28 PCH_TXCLK28 PCH_TXCLK+ R130 1 BF45 BH45 SDVO_CTRLDATA strap Pull High at Level Shift Page LVD_IBG LVD_VBG Digital Display Interface LVDS_IBG R162 1 UMOP@ 2 0_0402_5% 11/21 intel JIM suggest Pull high at LVDS Conn BJ48 BG48 L_CTRL_CLK L_CTRL_DATA R166 1 UMOP@ 2 2.37K_0402_1% +3VS BJ46 BG46 L_DDC_CLK L_DDC_DATA LCTLA_CLK LCTLB_DATA 28 PCH_LCD_CLK 28 PCH_LCD_DATA SDVO_TVCLKINN SDVO_TVCLKINP LVDS D L_BKLTEN L_VDD_EN Y48 28 PCH_ENVDD 2/3 Change to 1K_0402_0.5% from Intel Suggestion. (EDS 1.0 is incorrect) 0_0402_5% VGA_BKL_EN DIS ONLY USE +5VS U25 22 VGA_BKL_EN IGPU_BKLT_EN A 17,28,29 DGPU_SELECT# 28 IGPU_SELECT# 2 5 1 7 1A 2A 1OE# 2OE# VCC 1B 2B GND 8 3 6 4 C472 SG@ 0.1U_0402_16V4Z 1 2 ENBKL A ENBKL 36 SN74CBTD3306CPWR_TSSOP8 SG@ Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 16 of 56
  • 17.
    R577 R574 R572 R153 R568 R570 R565 R566 C 1 1 1 1 2 2 2 2 1 1 1 1 2 2 2 2 1 1 1 1 2 2 2 2 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 16,28,29 DGPU_SELECT# 28 DGPU_PWMSEL# PCI_GNT2#ESI Strap (Server Only) this signal should not be pulled low GNT0# GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# T12 PAD @ TP_PCI_RST# K6 PCIRST# E44 E50 SERR# PERR# A42 H44 F46 C46 IRDY# PAR DEVSEL# FRAME# PCI_PLOCK# D49 PCI_STOP# PCI_TRDY# D41 C48 STOP# TRDY# M7 R561 R142 1 1 2 22_0402_5% 2 22_0402_5% CLK_PCI_LPC_R CLK_PCI_FB_R B 1 A Y MC74VHC1G08DFT2G_SC70-5 DIS@ NV_RCOMP R660 1 @ +1.8VS NV_ALE R233 1 @ 2 1K_0402_5% If not implemented, the dual channel NAND interface signals, including NV_RCOMP, can be left as No Connect. NV_CLE R225 1 @ 2 1K_0402_5% Intel Anti-Theft Techonlogy USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 B25 USB_BIAS D25 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 N16 J16 F16 L16 E14 G16 F12 T15 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 35 35 35 35 35 35 NV_ALE USB/B (Right Side) USB Port (Left Side) NV_CLE 0 LPC 0 1 Reserved (NAND) 1 0 PCI 1 1 SPI Set to Vcc when HIGH Set to Vss when LOW Disable Intel Anti-Theft Technology：floating(internal PD) CMOS Camera (LVDS) Card Reader NV_CLE Mini Card(SIM Card) DMI termination voltage. weak internal PU, don't PD EHCI 2 Bluetooth Mini Card(WLAN) Mini Card(WWAN) B D5 1 2 R191 22.6_0402_1% USB_OC#0_R USB_OC#0_R 21 USB_OC#2_R PLTRST# N52 P53 P46 P51 P48 CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 USB_OC#0_R USB_OC#1_R USB_OC#2_R USB_OC#3_R USB_OC#4_R USB_OC#5_R USB_OC#6_R USB_OC#7_R R216 1 2 0_0402_5% R210 1 2 0_0402_5% USB_OC#2_R 21 (For USB Port0, 2) USB_OC#0 35 USB_OC#1_R 21 USB_OC#2 35 USB_OC#3_R 21 USB_OC#4_R 21 USB_OC#5_R 21 USB_OC#6_R 21 USB_OC#7_R 21 (For USB Port1) RP1 USB_OC#3_R USB_OC#5_R USB_OC#6_R USB_OC#7_R 1 2 3 4 8 7 6 5 +3V 10K_1206_8P4R_5% PCI_GNT0# R137 1 @ 2 1K_0402_5% @ 2 1K_0402_5% @ 2 1K_0402_5% USB_OC#1_R PCI_GNT1# R159 1 R601 1 2 10K_0402_5% USB_OC#4_R Have internal PU R603 1 2 10K_0402_5% Have internal PU PCI_GNT3# R558 1 A Have internal PU A16 swap overide Strap/Top-Block Swap Override jumper Compal Electronics, Inc. Compal Secret Data Security Classification Low=A16 swap override/Top-Block PCI_GNT3# Swap Override enabled High=Default * 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 * NV_ALE Enable Intel Anti-Theft Technology：8.2K PU to +3VS 2/10 USB6, USB7 not support on HM55 USB20_N8 28 USB20_P8 28 USB20_N9 35 USB20_P9 35 USB20_N10 34 USB20_P10 34 USB20_N11 35 USB20_P11 35 USB20_N12 34 USB20_P12 34 USB20_N13 34 USB20_P13 34 C DMI Termination Voltage USB/B (Right Side) EHCI 1 USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11 USB20_N12 USB20_P12 USB20_N13 USB20_P13 High=Endabled Low=Disable(floating) Boot BIOS Location 0 * PLTRST_VGA# 22 2 32.4_0402_1% OC[0..3] use for EHCI 1 OC[4..7] use for EHCI 2 PCI_GNT#1 2 R622 100K_0402_5% DIS@ IBEXPEAK-M_FCBGA107 A R619 1 DIS@ 100_0402_5% 4 Design Guide 1.5 Ver: 3.26.13 Terminating Unused Braidwood Interface Boot BIOS Strap PCI_GNT#0 D NV_ALE,NV_CLE has a weak internal pull-down NV_ALE NV_CLE H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24 PME# 2008/1/6 2009MOW01 change to 22 ohm 18,21 DGPU_HOLD_RST# USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P PLOCK# PLT_RST# U43 2 USBRBIAS PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 PCI_DEVSEL# PCI_FRAME# 36 CLK_PCI_LPC 14 CLK_PCI_FB AV11 BF5 R621 100K_0402_5% 2 +3VSDGPU USBRBIAS# B41 K53 A36 A48 PCI_IRDY# 5,21,32,36 PLT_RST# AY8 AY5 NV_WE#_CK0 NV_WE#_CK1 PCI_SERR# PCI_PERR# B NV_WR#0_RE# NV_WR#1_RE# PLT_RST_BUF# 34 1 REQ0# REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 AV7 @ 0.1U_0402_16V7K 4 2 F51 A46 B45 M53 AU2 NV_RB# Y 1 PIRQA# PIRQB# PIRQC# PIRQD# PCI_GNT0# F48 PCI_GNT1# K45 DGPU_PWMSEL# F36 PCI_GNT3# H53 PCI_GNT0#,PCI_GNT1#,PCI_GNT2#,PCI_GNT3# has a weak internal pull-up NV_RCOMP A 5 G38 H51 B37 A44 PCI_REQ0# PCI_REQ1# DGPU_SELECT# PCI_REQ3# PCI_FRAME# PCI_REQ1# PCI_PIRQH# PCI_TRDY# BD3 AY6 B 1 1 P PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_IRDY# PCI_PIRQD# DGPU_SELECT# PCI_DEVSEL# NV_ALE NV_CLE C443 2 G C/BE0# C/BE1# C/BE2# C/BE3# PCI_REQ0# PCI_PIRQB# PCI_PIRQF# PCI_REQ3# U42 PLT_RST# 3 J50 G42 H47 G34 PCI_PLOCK# PCI_PERR# PCI_PIRQE# PCI_STOP# AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6 MC74VHC1G08DFT2G_SC70-5 5 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% AV9 BG8 NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 +3VS AY9 BD1 AP15 BD8 NV_DQS0 NV_DQS1 NVRAM 2 2 2 2 PCI_PIRQA# PCI_PIRQG# PCI_PIRQC# PCI_SERR# 1 2 R556 R557 R559 R560 1 1 1 1 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 USB R554 R555 R581 R579 2 2 2 2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCI D 1 1 1 1 REV1.0 H40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H36 2 P U41E +3VS R160 R588 R585 R158 3 G 4 3 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 17 of 56
  • 18.
    5 4 3 2 1 +3VS +3VS EC_GA20 CRT_DET 2 10K_0402_5% PCH_GPIO22 R6511 2 10K_0402_5% PCH_GPIO39 R264 1 @ TACH3 / GPIO7 EC_SMI# F10 PCH_GPIO12 K9 T7 2 10K_0402_5% PCH_GPIO48 2 10K_0402_5% PCH_TEMP_ALERT# 17,21 DGPU_HOLD_RST# 2 10K_0402_5% VGA_PWROK R161 1 50 VGA_PWROK 0_0402_5% 2 10K_0402_5% PCH_GPIO34 2 10K_0402_5% EC_SCI# R243 1 R178 1 LAN_PHY_PWR_CTRL / GPIO12 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N AM3 CLK_CPU_BCLK# 5 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_CPU_BCLK 5 H10 GPIO24 AB12 GPIO27 PCH_GPIO28 V13 GPIO28 PCH_GPIO34 M11 STP_PCI# / GPIO34 PCH_GPIO35 V6 21 PCH_GPIO28 2 10K_0402_5% PCH_GPIO24 SCLOCK / GPIO22 PECI RCIN# BG10 T1 PROCPWRGD BD10 DIS@ R262 1 2 10K_0402_5% VGA_PRSNT_L# R659 1 2 10K_0402_5% DGPU_HOLD_RST# R154 1 @ 2 10K_0402_5% DGPU_PWROK_1 10 RST_GATE AB7 SATA2GP / GPIO36 TP1 AB13 SATA3GP / GPIO37 TP2 AW22 V3 SLOAD / GPIO38 TP3 R229 1 2 10K_0402_5% PCH_GPIO35 R263 1 @ SDATAOUT0 / GPIO39 TP4 H3 PCIECLKRQ6# / GPIO45 TP5 F1 PCIECLKRQ7# / GPIO46 TP6 AV43 SDATAOUT1 / GPIO48 TP7 AV45 SATA5GP / GPIO49 TP8 AF13 GPIO19 2 1 CRT_DET 1 High: CRT Plugged 2 G 2N7002E-T1-GE3_SOT23-3 dGPU iGPU * SG GPIO37 PCH_GPIO19 VGA_PRSNT_L# 0 0 1 0 1 0 D Q20 @ 3 29 CRT_DET# S GPIO8 This signal has a weak internal pull up can't Pull low GPIO27 On-Die PLL Voltage Regulator This signal has a weak internal pull up * H：On-Die voltage regulator enable L：On-Die PLL Voltage Regulator disable Note: the internal pull-up is disabled after RSMRST# de-asserts. The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is disabled. A F8 A4 A49 A5 A50 A52 A53 B2 B4 B52 B53 BE1 BE53 BF1 BF53 BH1 BH2 BH52 BH53 BJ1 BJ2 BJ4 BJ49 BJ5 BJ50 BJ52 BJ53 D1 D2 D53 E1 E53 TP9 C MAINPWON 44,45,47 +1.05VS_PCH R224 @ 330_0402_5% 1 2 C 2 B E VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 N18 TP11 AK41 TP13 AK42 TP14 M32 TP15 N32 TP16 M30 TP17 N30 TP18 H12 TP19 AB38 NC_3 AB42 NC_4 AB41 NC_5 B AB45 NC_2 H_THERMTRIP# AA23 NC_1 T39 INIT3_3V# REV1.0 Q14 2SC2411K_SOT23-3 @ AJ24 TP12 GPIO57 M18 TP10 R656 10K_0402_5% B AB6 PCH_TEMP_ALERT# AA4 PCH_GPIO57 +3VS +1.05VS_PCH AY46 RST_GATE H_THERMTRIP# 5 1 56_0402_5% AY45 2 10K_0402_5% PCH_GPIO27 GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable Low: VCCVRM VR Disable H_THERMTRIP# BB22 P3 PCH_GPIO48 21,36 PCH_TEMP_ALERT# 5 1 56_0402_5% 2009/08/23 Series resistor of 56±5% Pull-up of 56±5% to VTT (both these should be close to PCH) BA22 VGA_PRSNT_L# PCH_GPIO45 21 VGA_PRSNT_L# DGPU_PWR_EN VGA_PRSNT_R# 14,21,38,42 DGPU_PWR_EN PCH_GPIO28 PCH_GPIO57 PCH_GPIO45 RST_GATE 2 R221 3 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% H_CPUPWRGD THRMTRIP_PCH# SATACLKREQ# / GPIO35 RSVD 2 2 2 2 EC_KBRST# 36 BE10 THRMTRIP# H_PECI 5 EC_KBRST# 2 R220 NCTF C 1 1 1 1 EC_GA20 36 F38 PCH_GPIO39 R642 R640 R633 R630 EC_GA20 AA2 PCH_GPIO24 2 1K_0402_5% PCH_GPIO15 @ U2 DGPU_PWROK_1 Y7 10/7 Not Use PCH_GPIO15 PU 1K to +3V R242 1 A20GATE GPIO15 PCH_GPIO22 2 10K_0402_5% PCH_GPIO12 2 10K_0402_5% EC_SMI# R239 1 D GPIO8 (GPIO8 Have Internal Pull High,Should not be Pull-Low) (GPIO27 Have Internal Pull High) PCH_GPIO27 R245 1 R246 1 AF48 AF47 DGPU_HOLD_RST# 2 2009/09/07 GPIO24 pull high +3V +3V CLKOUT_PCIE7N CLKOUT_PCIE7P TACH2 / GPIO6 J32 (GPIO15 Have Internal Pull Down) PCH_GPIO15 R236 1 R658 1 R155 1 2 10K_0402_5% AH45 AH46 TACH1 / GPIO1 D37 EC_SCI# 36 EC_SMI# 2 10K_0402_5% DGPU_PWR_EN C38 DGPU_HPD_INT# 36 EC_SCI# CLKOUT_PCIE6N CLKOUT_PCIE6P BMBUSY# / GPIO0 DGPU_EDIDSEL# 30 DGPU_HPD_INT# DGPU_PWR_EN Pull Low at Page 43 Y3 CPU D 2 10K_0402_5% 1 21 CRT_DET 28 DGPU_EDIDSEL# R238 1 R654 1 EC_KBRST# R653 1 U41F 10K_0402_5% VGA_PRSNT_R# 10K_0402_5% VGA_PRSNT_L# 2 2 UMA ONLY@ MISC R655 1 R261 1 2 10K_0402_5% DGPU_EDIDSEL# 2 10K_0402_5% DGPU_HPD_INT# GPIO R582 1 R583 1 TP24 P6 2009/08/23 (Have internal PH,Do not pull down) C10 TP24_SST @ PAD T21 INIT3_3V This signal has weak internal PH, can't pull low IBEXPEAK-M_FCBGA107 A GPIO15 L：Intel ME Crypto Transport Layer Security(TLS) chiper suite with no confidentiality H：Intel ME Crypto Transport Layer Security(TLS) chiper suite with confidentiality * Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. CRB has a 1-k pull-up on this signal to +3.3VA rail. 5 Rev C 401869 Date: 4 3 2 Wednesday, June 30, 2010 Sheet 1 18 of 56
  • 19.
    5 4 3 2 1 Need Modify 180 ohm@ 100MHz Bead +1.05VS_VTT +1.05VS_PCH +3VS Near AB24 Near AB24 Top Side Intel suggest follow CRB 8/21 All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V rails DG 1.6 (Page 329) Have Internal VRM C +1.05VS_PCH 10U_0805_10V4Z 1 C719 Near AN20 1 C321 2 Top Side 1U_0402_6.3V4Z 1 C342 2 1 C345 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 C348 2 2 1U_0402_6.3V4Z +3VS Follow Intel suggestion 8/21 Near AN35 0.1U_0402_16V4Z C329 2 1 B DG 1.6 (Page 329) T9 PAD Have Internal VRM +VCCAPLL_FDI @ +1.05VS_PCH 1 AF51 300mA VCCALVDS LVDS 42mA VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] VCCIO[50] VCCIO[51] VCCIO[52] VCCIO[53] AN30 AN31 VCCIO[54] VCCIO[55] AN35 VCC3_3[1] VCCFDIPLL AM23 VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4] AB34 VCC3_3[3] AD35 VCCIO[1] C331 Near AE50 61mA 6mA +3VS L20 UMOP@ 2 1 0.1UH_MLF1608DR10KT_10%_1608 0.1uH inductor, 200mA 1 2 R145 DIS ONLY@ 0_0402_5% +3VS 1 C Near AB34 VCCDMI[2] 2 0_0805_5% +1.05VS_PCH R192 1 2 0_0805_5% +1.8VS +VCCVRM AT24 VCCDMI[1] +1.05VS_PCH 10mil AU16 156mA CRB 0.9 is 180 ohm @ 100MHz DG0.8 is 600 ohm FB (Page 290) +1.8VS 15mil +VCCTX_LVDS C300 C316 1 UMOP@ 1 1 0.01U_0402_16V7K 22U_0805_6.3V6M C304 0.01U_0402_16V7K UMOP@ 2 2 UMOP@ 2 40mil AT16 VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9] D 2 R138 1 UMOP@ 2 0_0805_5% Near AP43 0.1U_0402_16V4Z 2 35mA 220 ohm bead,350mA 2 AB35 VCC3_3[4] VCCVRM[2] 1 2 L19 MBK1608221YZF_2P R172 0_0402_5% DIS ONLY@ AP43 AP45 AT46 AT45 3208mA 22U_0805_6.3V6M 1 C476 C291 R186 1 @ VCCVRM[1] BJ18 22U_0805_6.3V6M 1 1 C298 0.1U_0402_16V4Z 2 2 +VCCA_LVDS AH39 VCCAPLLEXP AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27 0.01U_0402_16V7K 1 C296 R136 0_0402_5% @ AH38 VSSA_LVDS VCC3_3[2] BJ24 VCCIO[24] AT22 +VCCVRM 10mil VSSA_DAC[2] HVCMOS @ +VCCAPLL_EXP AF53 59mA AK24 T20 PAD VSSA_DAC[1] +VCCADAC AE52 20mil +1.05VS_PCH 10mil AE50 VCCADAC[2] DMI Short J4 for PCH VCCCORE 2 VCCADAC[1] 69mA 2 C344 VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4]1524mA VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] 1 C718 2 AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31 AJ30 AJ31 60mA 15mil 2 1U_0402_6.3V4Z 1 CRT 10U_0805_10V4Z 1 1 NAND / SPI 1 PCI E* 2 @ JUMP_43X118 FDI 2 D POWER U41G VCC CORE J1 +VCC_DMI R204 1 2 0_0805_5% 1 C368 1U_0402_6.3V4Z 2 AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15 Near AT16 +1.8VS C372 1 B 0.1U_0402_16V4Z 2 85mA VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4] AM8 AM9 AP11 AP9 REV1.0 Near AK13 +3VS C387 IBEXPEAK-M_FCBGA107 1 0.1U_0402_16V4Z 2 Near AM8 A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 19 of 56
  • 20.
    4 3 @ C295 C324 22U_0805_6.3V6M 1U_0402_6.3V4Z 2 2 C294 2 22U_0805_6.3V6M Near AD38 1U_0402_6.3V4Z VCCME[7] VCCME[8] V42 VCCME[9] VCCME[10] VCCME[11] NearV39 All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V rails Y42 C390 10mil 0.1U_0402_16V4Z +VCCRTCEXT 1 2 Near V9 C AU24 +VCCVRM 20mil +VCCADPLLA 20mil C330 1U_0402_6.3V4Z 2 1 2 Near AF32 C351 +PCH_VCCIO 2 0_0603_5% 2 1 C336 1U_0402_6.3V4Z 1 R139 1U_0402_6.3V4Z Near AH35 +3V 72mA VCCADPLLA[1] VCCADPLLA[2] 73mA VCCSUS3_3[30] U20 VCCSUS3_3[31] U22 2 VCCSUS3_3[32] VCC3_3[5] V16 VCC3_3[6] 1 Y16 2 C360 1 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z Near 2 AU18 AT18 A 20mil A12 VCC3_3[7] V_CPU_IO[1] V_CPU_IO[2] 2mA VCCRTC C386 1 C377 +VCC5REF Change to 1U for power sequence issue on ICH9 2 2 0.1U_0402_16V4Z Near A12 1 C692 1U_0402_6.3V4Z 2 2 Near BD51 D4 CH751H-40PT_SOD323-2 R141 100_0402_5% 1 2 2 1 2/12 Follow EDS1.11 Change to 100 ohm C +5VS C299 1U_0402_6.3V6K N36 P36 C337 U35 0.1U_0402_16V4Z 2 AD13 1 Near J38 +3VS Near AD13 AK3 AK1 10mil +VCCSATAPLL @ 2 C376 0.1U_0402_16V4Z PAD T23 DG 1.6 (Page 329) Have Internal VRM B AH22 AT20 VCCIO[10] AH19 VCCIO[11] AD20 VCCIO[12] AF22 1 VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] AD19 AF20 AF19 AH20 C371 1U_0402_6.3V4Z 2 VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] AB19 AB20 AB22 AD22 VCCME[13] VCCME[14] VCCME[15] VCCME[16] AA34 Y34 Y35 AA35 6mA VCCSUSHDA +VCCVRM +1.05VS_PCH +5VALW Near AB19 42 SBPWR_EN# PCH_VCCME13 PCH_VCCME14 PCH_VCCME15 PCH_VCCME16 R179 R164 R165 R173 1 1 1 1 2 2 2 2 L30 R176 0_0402_5% 2 @ 1 C343 @ 0.1U_0402_16V4Z +1.05VS_PCH 15mil S 2 1 Q8 R169 0_0402_5% G @ D AO3413L_SOT23-3 2 0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5% +5V +3V C357 1 A 2 1U_0402_6.3V4Z Near L30 Compal Electronics, Inc. Compal Secret Data Security Classification 0.1U_0402_16V4Z 2 @ Near K49 1 C373 1U_0402_6.3V4Z 1 +3VS VCCVRM[4] IBEXPEAK-M_FCBGA107 2 C349 1U_0402_6.3V6K 1 +RTCVCC 1 1 +5V Near F24 VCC3_3[12] > 1mA 10mil R189 2 100_0402_5% 1 M36 DCPSUS RTC 4.7U_0805_10V4Z 1 10mil VCC3_3[11] VCCSUS3_3[29] AT18 C359 +VCC5REFSUS VCC3_3[10] VCCSATAPLL[1] VCCSATAPLL[2] U19 1 +VCCADPLLB +3VS 2/12 Follow EDS1.11 Change to 100 ohm VCCIO[9] Near V15 1 +1.05VS_PCH +1.05VS_PCH Y22 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 D D5 CH751H-40PT_SOD323-2 L38 32mA DCPSST V15 C364 +3V J38 VCC3_3[9] C689 220U_B2_2.5VM_R35 1 +3VS +1.05VS_PCH K49 2 1U_0402_6.3V4Z 2 + 10mil VCC3_3[8] VCCIO[4] V12 Near P18 0.1U_0402_16V4Z V5REF 357mA R562 0_0402_5% @ L61 1 2 10UH_LB2012T100MR_20% 2 >1mA C691 @ Near U23 VCCIO[3] P18 C370 F24 VCCIO[2] Y22 0.1U_0402_16V4Z V5REF_SUS >1mA C688 220U_B2_2.5VM_R35 10uH inductor, 120mA VCC3_3[14] VCCIO[21] VCCIO[22] VCCIO[23] V12 C369 V23 1 + 0.1U_0402_16V4Z 2 Near A26 VCC3_3[13] VCCADPLLB[1] VCCADPLLB[2] AF32 +VCCSUS 1 2 C353 Near 0.1U_0402_16V4Z 10mil B VCCVRM[3] BD51 BD53 AH34 +VCCSST 1 2 C375 Near 0.1U_0402_16V4Z 10mil DCPRTC AF34 Near AH23 1 BB51 BB53 VCCME[12] AH23 AJ35 AH35 +VCCADPLLB +1.05VS_PCH V9 U23 VCCIO[56] VCCME[6] Y41 2 V39 V41 C341 2 AF42 Y39 C293 163mA VCCME[5] 0.1U_0402_16V4Z 2 1 1 1 C347 1 2 1 1 C350 Near BB51 L60 1 2 10UH_LB2012T100MR_20% 10uH inductor, 120mA 3 AF41 1 VCCSUS3_3[28] VCCME[4] 09/09/14 WW37 remove +VCCADPLLA +VCCADPLLA,+VCCADPLLB external 1U 1 VCCME[3] AF43 +3V Near V24 2 22U_0805_6.3V6M 1 VCCME[2] AD41 Follow Intel suggestion VCCME[1] AD39 Near Y20 +1.05VS_PCH C340 1U_0402_6.3V4Z 2 2 +1.05VS_PCH 1998mA AD38 0.1U_0402_16V4Z 2 V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26 +1.05VS_PCH 1 1 1 DCPSUSBYP USB 2 Near AF23 Y20 HDA C367 +PCH_VCCD6W VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27] 344mA Clock and Miscellaneous 10mil V24 V26 Y24 Y26 PCI/GPIO/LPC C352 1U_0402_6.3V4Z 2 @ DG2.0 Table162 Note2 (C295 unpop) 1 VCCLAN[2] 1 R199 0_0402_5% D VCCLAN[1] AF24 +VCCLAN VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] SATA 2 VCCACLK[2] PCI/GPIO/LPC @ 1 R187 1 0_0603_5% 15mil VCCACLK[1] AF23 +1.05VS_PCH 1 1 REV1.0 52mA AP51 AP53 DG 1.6 (Page 329) Have Internal VRM 2 POWER U41J 10mil +1.1VS_VCCACLK @ T17 PAD CPU 5 2 Wednesday, June 30, 2010 Sheet 1 20 of 56
  • 21.
    5 4 U41I B A U41H VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366] H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14 AB16 VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] PCH XDP Port VSS[0] AA19 AA20 AA22 AM19 AA24 AA26 AA28 AA30 AA31 AA32 AB11 AB15 AB23 AB30 AB31 AB32 AB39 AB43 AB47 AB5 AB8 AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31 AD32 AD34 AU22 AD42 AD46 AD49 AD7 AE2 AE4 AF12 Y13 AH49 AU4 AF35 AP13 AN34 AF45 AF46 AF49 AF5 AF8 AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43 AH47 AH7 AJ19 AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32 AJ34 AT5 AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28 1 REV1.0 VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47 17USB_OC#0_R R314 1 @ 2 33_0402_5% XDP_FN0 17 USB_OC#2_R R311 1 @ 2 33_0402_5% XDP_FN2 17 USB_OC#4_R R306 1 @ 2 33_0402_5% XDP_FN4 R312 R310 R309 R307 R305 R304 R300 R297 2 2 2 2 2 2 2 2 D 13 PCH_JTAG_TCK 13 PCH_JTAG_TMS 13 PCH_JTAG_TDI 13 PCH_JTAG_TDO XDP_FN8 XDP_FN9 XDP_FN10 XDP_FN11 XDP_FN12 XDP_FN13 XDP_FN14 XDP_FN15 2 33_0402_5% XDP_FN17 R287 R284 R286 R293 18 CRT_DET 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% R313 1 @ 14 PCH_GPIO20 14 PCH_GPIO18 13 PCH_GPIO21 13 PCH_GPIO19 14,18,38,42 DGPU_PWR_EN 18 VGA_PRSNT_L# 17,18 DGPU_HOLD_RST# 18,36 PCH_TEMP_ALERT# 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 1 1 1 1 1 1 1 1 @ @ @ @ @ @ @ @ 1 1 1 1 R289 1 @ 13 PCH_JTAG_RST# PCH_JTAG_TCK_R PCH_JTAG_TMS_R PCH_JTAG_TDI_R PCH_JTAG_TDO_R PCH_JTAG_RST#_R JP3 XDP_FN0 (XDP_FN1) 17 USB_OC#1_R XDP_FN2 (XDP_FN3) 17 USB_OC#3_R XDP_FN4 (XDP_FN5) 17 USB_OC#5_R (XDP_FN6) 17 USB_OC#6_R (XDP_FN7) 17 USB_OC#7_R 15 SYS_PWROK 5,15,36 PBTN_OUT# +3VS 1 R296 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 0_0402_5% 5 SMB_DATA_S3 5 SMB_CLK_S3 PCH_JTAG_TCK_R GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 CONN@ GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 (XDP_FN16) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 PCH_GPIO28 18 XDP_FN17 XDP_FN8 XDP_FN9 C XDP_FN10 XDP_FN11 XDP_FN12 XDP_FN13 XDP_FN14 XDP_FN15 +3VS 2 1 R295 1K_0402_5% PCH_JTAG_TDO_R PCH_JTAG_RST#_R PCH_JTAG_TDI_R PCH_JTAG_TMS_R PLT_RST# 5,17,32,36 XDP_DBRESET# 5,15 SAMTE_BSH-030-01-L-D-A B +3VS R294 @ 4.7K_0402_5% 1 2 2 C 2 6 12,14,34 PCH_SMBDATA 1 Q21A 2N7002DWH_SOT363-6 @ +3VS R290 @ 4.7K_0402_5% 1 2 IBEXPEAK-M_FCBGA107 +3VS SMB_DATA_S3 5 D AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47 B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49 BB5 BC10 BC14 BC18 BC2 BC22 BC32 BC36 BC40 BC44 BC52 BH9 BD48 BD49 BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50 BE6 BE8 BF3 BF49 BF51 BG18 BG24 BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47 BH7 C12 C50 D51 E12 E16 E20 E24 E30 E34 E38 E42 E46 E48 E6 E8 F49 F5 G10 G14 G18 G2 G22 G32 G36 G40 G44 G52 AF39 H16 H20 H30 H34 H38 H42 3 3 12,14,34 PCH_SMBCLK 4 +3VS SMB_CLK_S3 Q21B 2N7002DWH_SOT363-6 @ A REV1.0 Compal Electronics, Inc. Compal Secret Data Security Classification IBEXPEAK-M_FCBGA107 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 21 of 56
  • 22.
    A B C D E U51A I2CS_SCL I2CS_SDA R773 R774 R864 R863 1 1 1 1 DIS@ DIS@ DIS@ DIS@ I2CB_SCL I2CB_SDA HDCP_SCL HDCP_SDA 4 I2CS_SCL 2 2 2 2 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 28 VGA_LCD_CLK 28 VGA_LCD_DATA 29VGA_DDC_CLK VGA_DDC_DATA CRT29 EC_SMB_CK2 14,36 +1.05VSDGPU +3VSDGPU 5 I2CC_SCL I2CC_SDA I2CB_SCL I2CB_SDA VGA_DDC_CLK G1 VGA_DDC_DATA G4 I2CA_SCL I2CA_SDA F6 G6 I2CH_SCL I2CH_SDA EC_SMB_DA2 14,36 +3VSDGPU 1 C855 DIS@ 2 2 2 N/A N/A IN N/A N/A OUT N/A N/A OUT N/A N/A B 2 @ 22_0402_5% XTAL_OUTBUFF 1 R759 1 VSS 3 XIN/CLKIN R761 10K_0402_5% DIS@ 6 MODOUT 5 VDD OSC_SPREAD 4 2 1 OSC_OUT XOUT 3 +3VSDGPU 1 @ ASM3P2872AF-06OR_TSOT-23-6 2 OSC_SPREAD R763 1 @ C842 0.1U_0402_16V4Z 2 @ 22_0402_5% XTAL_SSIN XTAL_SSIN 12 27M_SSC 2 R756 R757 R758 DIS@ DIS@ DIS@ W4 AA7 AA6 R765 10K_0402_5% DIS@ If External Spread Spectrum not stuff then stuff resistor DACA_RED DACA_GREEN DACA_BLUE AM15 AM14 AL14 VGA_CRT_R 29 VGA_CRT_G 29 VGA_CRT_B 29 AM13 AL13 VGA_CRT_HSYNC VGA_CRT_VSYNC AJ12 AK12 AK13 DACB_RED DACB_GREEN DACB_BLUE BLM18PG181SN1D_0603 1 2 +3VSDGPU L80 DIS ONLY@ 150 mA DACA_VDD 1 1 2 124_0402_1% R770 DIS@ 2 0.1U_0402_16V4Z C849 DIS@ C850 1 AK4 AL4 AJ4 DACB_HSYNC DACB_VSYNC 29 29 AM1 AM2 1 C850 2 10K_0402_5% 0.1U_0402_16V4Z 2 R775 1 AG7 1 2 AK6 10K_0402_5% DIS@ R776 2 DIS@ C854 1 AH7 124_0402_1% DIS@ 2 1 C853 2 1 C851 2 1 C858 1 C857 2 2 2 C859 1 For CRT flicker issue change C858 C857 form .1u to 1u 20100617 4 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 2 1 C852 2009/5/12 Deciphered Date 2009/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: A 2 1 1 DIS@ 2 R764 10K_0402_5% REFOUT 2 2 AE1 V4 DACB_VDD DACB_VREF DACB_RSET 1 C856 DIS@ OUT U53 1 N11P-GE1-B-A2_BGA969 @ BLM18PG181SN1D_0603 SP_PLLVDD 2 1 DIS@ L81 Q60B 2N7002DWH_SOT363-6 DIS@ I2CS_SDA 4 3 E3 E4 G3 G2 HDCP_SCL HDCP_SDA Q60A 2N7002DWH_SOT363-6 1 6 DIS@ 2 VGA_LCD_CLK VGA_LCD_DATA I2CB_SCL I2CB_SDA N/A 0.1U_0402_16V4Z DIS@ 2 2.2K_0402_5% DIS@ 2 2.2K_0402_5% N/A N/A DIS ONLY@ 1 1 L OUT 1U_0402_6.3V6K R771 R772 LVDS OUT 1U_0402_6.3V6K VGA_LCD_CLK VGA_LCD_DATA N/A DIS ONLY@ DIS@ 2 2.2K_0402_5% DIS@ 2 2.2K_0402_5% L OSC_OUT 4.7U_0603_6.3V6M 1 1 I2CS_SCL I2CS_SDA N/A IN DIS ONLY@ R768 R769 VGA_CRT_B DACA_VDD DACA_VREF DACA_RSET E2 E1 N/A External Spread Spectrum VGA_CRT_G DACA_HSYNC DACA_VSYNC XTAL_OUTBUFF XTAL_SSIN I2CS_SCL I2CS_SDA VGA_DDC_CLK VGA_DDC_DATA NVVDD VID1 OUT GPIO14 DIS ONLY@ DIS@ 2 2.2K_0402_5% DIS@ 2 2.2K_0402_5% NVVDD VID0 N/A VGA_CRT_R Y5 W3 AF1 MIOB_CAL_PD_VDDQ MIOB_CAL_PU_GND N/A OUT 1 When the MIOx interface is unused, the interface must still be powered by 3.3V, a decoupling capacitor of 0.1uF should still be placed on thx MIOx_VDDQ power rail and 10k pull down should be used on MIOx_CLKIN 1U_0402_6.3V6K 1 1 XTAL_IN XTAL_OUT D1 D2 4.7U_0603_6.3V6M R766 R767 VID_PLLVDD B1 B2 XTAL_OUTBUFF XTAL_SSIN +3VSDGPU C836 DIS@ 18P_0402_50V8J 1 DIS ONLY@ XTALIN XTALOUT 1 DIS@ 2 R753 10K_0402_5% 4700P_0402_25V7K AD9 C848 DIS@ OUT GPIO13 XTALIN 1 1M_0402_5% 27MHZ_16PF_X5H027000FG1H DIS@ C838 DIS@ 18P_0402_50V8J DIS ONLY@ 2 VGA_BKL_EN GPIO12 2 R754 @ 2 W1 W2 MIOB_DE MIOB_CTL3 MIOB_VREF MIOB_CLKOUT_N H GPIO11 2 0_0402_5% Y5 470P_0402_50V7K C847 DIS@ XTALOUT DIS ONLY@ 2 SP_PLLVDD 1 @ R860 12 27M_CLK PLLVDD AF9 ENVDD OUT Unused MIO interface Y1 Y2 Y3 AB3 AB2 AB1 AC4 AC1 AC2 AC3 AE3 AE2 U6 W6 Y6 MIOB_CLKIN MIOB_CLKOUT AE9 SP_PLLVDD 1 H GPIO9 2 +3VSDGPU 10K_0402_5% OPT@ 1 1 DIS@ PEX_RST_N PEX_TERMP CLK 0.1U_0402_16V4Z 0.1U_0402_16V4Z C846 DIS@ 2 0.1U_0402_16V4Z 2 1U_0402_6.3V6K 4.7U_0603_6.3V6M 22U_0805_6.3V6M C845 DIS@ GPU_PLLVDD 1 VGA_PNL_PWM OUT GPIO10 R747 150_0402_1% 1 HDMI Hot-plug H +3VSDGPU 150_0402_1% 150_0402_1% 36 mA AM16 AG21 2 DIS@ 1 R762 2.49K_0402_1% H OUT GPIO8 2N7002E-T1-GE3_SOT23-3 1 VGA_idle 36 150_0402_1% 17 PLTRST_VGA# 3 USAGE DIS@ 1 PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N R760@ 2 1 200_0402_1% MIOB_HSYNC MIOB_VSYNC IN GPIO7 +3VSDGPU 1 DIS@ 2 R746 10K_0402_5% 1 AJ17 AJ18 1 14 PEG_CLKREQ# 14 CLK_PEG_VGA 14 CLK_PEG_VGA# GPIO1 GPIO5 1 2.2K_0402_5% 1 DIS@ 2 R745 10K_0402_5% 3 N/A +3VSDGPU +3VSDGPU Q54 N/A GPIO6 @ 2 R742 ACTIVE IN GPIO4 GPU_VID0 50 GPU_VID1 50 1 DIS@ 2 R743 DIS@ 10K_0402_5% 1 2 R744 10K_0402_5% I/O GPIO0 GPIO3 1 2.2K_0402_5% ENVDD 28 VGA_BKL_EN 16 2 PEX_REFCLK PEX_REFCLK_N PEX_CLKREQ_N MIOB_D0 MIOB_D1 MIOB_D2 MIOB_D3 MIOB_D4 MIOB_D5 MIOB_D6 MIOB_D7 MIOB_D8 MIOB_D9 MIOBD_10 MIOB_D11 MIOB_D12 MIOB_D13 MIOB_D14 GPIO GPIO2 @ 2 R741 VGA_HDMI_DET 30 VGA_PNL_PWM 28 2 AR16 AR17 AR13 PEX_TXP15 PEX_TXN15 PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N I2C DACs R755 10K_0402_5% DIS@ BLM18PG181SN1D_0603 2 1 +1.05VSDGPU DIS@ L79 1 1 C843 C844 DIS@ DIS@ 2 2 GPIO AL17 AM17 AM18 AM19 AL19 AK19 AL20 AM20 AM21 AM22 AL22 AK22 AL23 AM23 AM24 AM25 AL25 AK25 AL26 AM26 AM27 AM28 AL28 AK28 AK29 AL29 AM29 AM30 AM31 AM32 AN32 AP32 PEX_TXP9 PEX_TXN9 PEX_TXP10 PEX_TXN10 PEX_TXP11 PEX_TXN11 PEX_TXP12 PEX_TXN12 PEX_TXP13 PEX_TXN13 PEX_TXP14 PEX_TXN14 N1 P4 P1 P2 P3 T3 T2 T1 U4 U1 U2 U3 R6 T6 N6 N2 N3 L3 P5 N5 N4 R4 U5 T5 T4 PCI EXPRESS DVO 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PEX_TXP0 PEX_TXN0 PEX_TXP1 PEX_TXN1 PEX_TXP2 PEX_TXN2 PEX_TXP3 PEX_TXN3 PEX_TXP4 PEX_TXN4 PEX_TXP5 PEX_TXN5 PEX_TXP6 PEX_TXN6 PEX_TXP7 PEX_TXN7 PEX_TXP8 PEX_TXN8 MIOA_D0 MIOA_D1 MIOA_D2 MIOA_D3 MIOA_D4 MIOA_D5 MIOA_D6 MIOA_D7 MIOA_D8 MIOA_D9 MIOA_D10 MIOA_D11 MIOA_D12 MIOA_D13 MIOA_D14 MIOA_DE MIOA_HSYNC MIOA_VSYNC MIOA_CTL3 MIOA_VREF MIOA_CLKIN MIOA_CLKOUT MIOA_CAL_PD_VDDQ MIOA_CAL_PD_VDDGND MIOA_CLKOUT_N 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K K1 K2 K3 H3 H2 H1 H4 H5 H6 J7 K4 K5 H7 J4 J6 L1 L2 L4 M4 L7 L5 K6 L6 M6 G 2 PEG_GTX_C_HRX_P0 PEG_GTX_C_HRX_N0 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_N15 +3VSDGPU C807 C808 C810 C811 C812 C813 C814 C815 C816 C817 C818 C819 C820 C821 C822 C823 C824 C825 C826 C827 C828 C829 C830 C831 C832 C833 C834 C835 C837 C839 C840 C841 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 D 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ Part 1 of 7 PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N 1U_0402_6.3V6K 1 AP17 AN17 AN19 AP19 AR19 AR20 AP20 AN20 AN22 AP22 AR22 AR23 AP23 AN23 AN25 AP25 AR25 AR26 AP26 AN26 AN28 AP28 AR28 AR29 AP29 AN29 AN31 AP31 AR31 AR32 AR34 AP34 PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_N15 S S 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 C D Wednesday, June 30, 2010 Sheet E 22 of 56
  • 23.
    5 4 3 2 1 U51D Part 4 of7 AP13 AN13 AN8 AP8 AP10 AN10 AR11 AR10 AN11 AP11 2 GE1@ 1 R782 10K_0402_1% +3VSDGPU D @ 1 2 R777 5.1K_0402_5% 1 DIS@ 2 R778 45.3K_0402_1% GE@ R779 34.8K_0402_1% NonGE@ 34.8K_0402_1% strap1 R780 1 GE@ 2 R781 10K_0402_1% 1 GV2H@ 2 R782 30K_0402_5% strap2 strap0 1 X76@ 2 R783 20K_0402_5% @ 1 2 R784 5.1K_0402_5% ROM_SI 1 DIS@ 2 R785 10K_0402_1% @ 1 2 R786 5.1K_0402_5% ROM_SO GE@ 2 1 R788 15K_0402_5% ROM_SCLK NonGE@ R787 15K_0402_5% Mode E Command Mapping GB2-128 Package Femi C Mode C Command Mapping GB1-128 Package Data Bit 0..31 FBx_CMD1 A8 FBx_CMD2 FBx_CMD2 FBx_CMD21 FBx_CMD3 A7 FBx_CMD4 A2 AL2 AL3 R792 AJ3 4.7K_0402_5% AJ2 DIS@ AJ1 AH1 AH2 AH3 IFPF_L0 IFPF_L0_N IFPF_L1 IFPF_L1_N IFPF_L2 IFPF_L2_N IFPF_L3 IFPF_L3_N A1 FBx_CMD23 FBx_CMD5 A11 A9 FBx_CMD26 FBx_CMD6 A5 A4 FBx_CMD7 FBx_CMD7 A0 A12 FBx_CMD15 FBx_CMD8 CAS* CAS* FBx_CMD13 FBx_CMD9 BA1 A3 FBx_CMD4 FBx_CMD10 A9 A11 FBx_CMD18 FBx_CMD11 FBx_CMD29 FBx_CMD12 BA0 BA0 FBx_CMD27 FBx_CMD13 BA2 A15 FBx_CMD6 FBx_CMD14 A3 BA1 FBx_CMD17 FBx_CMD15 CS1_H FBx_CMD19 FBx_CMD16 ODT_H FBx_CMD22 FBx_CMD17 A4 A5 FBx_CMD12 FBx_CMD18 A13 A14 FBx_CMD28 FBx_CMD19 WE* A10 FBx_CMD10 FBx_CMD20 A1 A2 FBx_CMD25 FBx_CMD21 A10 WE* FBx_CMD9 FBx_CMD22 A12 A0 FBx_CMD1 FBx_CMD23 CS1_L* FBx_CMD11 FBx_CMD24 RAS* A8 CS0_H 1 1 2 2 +3VSDGPU R791 4.7K_0402_5% DIS@ D35 P7 AD20 GND_SENSE_0 GND_SENSE_1 GND_SENSE_2 IFPE_L0 IFPE_L0_N IFPE_L1 IFPE_L1_N IFPE_L2 IFPE_L2_N IFPE_L3 IFPE_L3_N A6 FBx_CMD24 AD19 E35 R7 AP2 AN3 IFPD_AUX_I2CX_SCL IFPD_AUX_I2CX_SDA_N IFPE_AUX_I2CY_SCL IFPE_AUX_I2CY_SDA_N AF3 AF2 IFPF_AUX_I2CZ_SCL IFPF_AUX_I2CZ_SDA_N TESTMODE JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N A7 B7 C7 D6 D7 +3VSDGPU FBx_CMD25 ODT_L FBx_CMD5 FBx_CMD26 A6 FBx_CMD16 FBx_CMD27 FBx_CMD20 FBx_CMD28 RST FBx_CMD29 A14 A13 FBx_CMD30 FBx_CMD30 A15 strap2 ROM_SI H 45K H 35K H 30K L 20K L 10K L 15K 64MX16 Hynix SA000032490 H 45K H 35K H 30K L 15K L 10K L 15K 20100113 Modify For GE1 strap0 ROM_SO ROM_SCLK strap1 strap2 ROM_SI 64MX16 Samsung SA000035720 H 45K H 35K H 10K L 20K L 10K L 15K 64MX16 Hynix SA000032490 H 45K H 35K H 10K L 15K L 10K L 15K strap1 strap2 ROM_SI 20100601 Modify For GE strap0 64MX16 Samsung SA000035720 ROM_SO ROM_SCLK ROM_SO ROM_SCLK H 45K L 35K L 10K L 20K L 10K H 15K 64MX16 Hynix SA000032490 H 45K L 35K L 10K L 15K L 10K H 15K 128MX16 Samsung SA00003MQ40 H 45K L 35K L 10K L 45K L 10K H 15K 128MX16 Hynix SA00003VS10 R790 1 DIS@ R793 1 DIS@ D H 45K L 35K L 10K L 35K L 10K H 15K C +NVVDD_SENSE 50 2 0_0402_5% 2 0_0402_5% R794 1 DIS@ 2 0_0402_5% R796 1 DIS@ 2 0_0402_5% NC NC NC NC NC A4 BUFRST_N NC AP35 AP14 AN14 AN16 AR14 AP16 PAD PAD PAD PAD PAD T25 T26 T27 T28 T29 @ @ @ @ @ R799 ROM_CS_N ROM_SI ROM_SO ROM_SCLK C3 D3 C4 D4 NC A5 N9 CEC JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST 2 R798 1 10K_0402_5% DIS@ SERIAL MULTI_STRAP_REF0_GND AB5 DIS@ 1 R797 2 10K_0402_5% ROM_CS# ROM_SI ROM_SO ROM_SCLK 10K_0402_5%1 2 @ +3VSDGPU DIS@ R801 2 1 40.2K_0402_1% 2 1 40.2K_0402_1% DIS@ R802 RST FBx_CMD14 strap0 B GENERAL DIS@ 10K_0402_5% 2 R800 1 strap1 64MX16 Samsung SA000035720 TEST AE4 AD4 20091214 Modify For GV2H 20091217 For layout convenient del R789 and R795 IFPC_AUX_I2CW_SCL IFPC_AUX_I2CW_SDA_N AP4 AN4 30 VGA_HDMI_SCLK 30 VGA_HDMI_SDATA RAS* FBx_CMD0 A AH6 AH5 AH4 AG4 AF4 AF5 AE6 AE5 CS0_L* A2 C5 D5 E5 E7 F4 G5 G11 G12 G14 G15 G27 G28 G24 G25 H32 J18 J19 J25 J26 L29 M7 M29 P6 P29 R29 U7 V6 Y4 AA4 AB4 AB7 AC5 AD6 AD29 AE29 AF6 AG6 AG20 AG29 AH29 AJ5 AK15 AL7 VDD_SENSE_0 VDD_SENSE_1 VDD_SENSE_2 IFPD_L0 IFPD_L0_N IFPD_L1 IFPD_L1_N IFPD_L2 IFPD_L2_N IFPD_L3 IFPD_L3_N CKE_L FBx_CMD8 B FBx_CMD0 IFPC_L0 IFPC_L0_N IFPC_L1 IFPC_L1_N IFPC_L2 IFPC_L2_N IFPC_L3 IFPC_L3_N AR8 AR7 AP7 AN7 AN5 AP5 AR5 AR4 32..63 FBx_CMD3 IFPB_TXC IFPB_TXC_N IFPB_TXD4 IFPB_TXD4_N IFPB_TXD5 IFPB_TXD5_N IFPB_TXD6 IFPB_TXD6_N IFPB_TXD7 IFPB_TXD7_N AM7 AM6 AL5 AM5 AM3 AM4 AP1 AR2 30 VGA_HDMI_TXD2+ 30 VGA_HDMI_TXD230 VGA_HDMI_TXD1+ 30 VGA_HDMI_TXD130 VGA_HDMI_TXD0+ 30 VGA_HDMI_TXD030 VGA_HDMI_TXC+ 30 VGA_HDMI_TXC- NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Straps MULTI LEVEL STRAPS IFPA_TXC IFPA_TXC_N IFPA_TXD0 IFPA_TXD0_N IFPA_TXD1 IFPA_TXD1_N IFPA_TXD2 IFPA_TXD2_N IFPA_TXD3 IFPA_TXD3_N LVDS/TMDS STRAP0 STRAP1 STRAP2 ROM_SI ROM_SO ROM_SCLK AM11 AM12 AM8 AL8 AM10 AM9 AK10 AL10 AK11 AL11 28 VGA_TXCLK+ 28 VGA_TXCLK28 VGA_TXOUT0+ 28 VGA_TXOUT028 VGA_TXOUT1+ 28 VGA_TXOUT128 VGA_TXOUT2+ 28 VGA_TXOUT2- BA2 STRAP0 STRAP1 STRAP2 A7 CKE_H MULTI_STRAP_REF1_GND W5 W7 V7 N11P-GE1-B-A2_BGA969 @ HIGH Compal Electronics, Inc. Compal Secret Data 2009/5/12 Issued Date LOW B5 B4 A Security Classification FBx_CMD31 M9 THERMDP THERMDN STRAP0 STRAP1 STRAP2 Deciphered Date 2010/04/15 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 Rev 401869 Date: 3 2 Wednesday, June 30, 2010 Sheet 1 23 of 56
  • 24.
    5 4 3 2 1 U51E C1042 DIS@ 2 1 C1046 DIS@ 2 PEX_SVDD_3V3 MIOA_VDDQ MIOA_VDDQ MIOA_VDDQ MIOA_VDDQ 2 1 C879 DIS@ 2 1 C891 DIS@ 2 2 C900 DIS@ PEX_IOVDDQ 2 C892 DIS@ 1 C1032 DIS@ 2 2 C897 DIS@ 1 2 C898 DIS@ 1 2 C899 DIS@ C 1 C1031 DIS@ 2 C907 DIS@ 2 C904 DIS@ 2 10K_0402_5% C914 DIS@ C908 C915 DIS@ DIS@ C909 C906 DIS@ DIS@ C905 C916 DIS@ DIS@ C910 C917 DIS@ DIS@ C911 C918 DIS@ DIS@ R810 1 @ C936 0.1U_0603_25V7K DIS@ 2N7002DWH_SOT363-6 Q57A 1 2 1 2 DIS@ C1038 DIS@ C935 0.1U_0603_25V7K DIS@ C923 + 2 1 C924 DIS@ 2 C925 DIS@ 1 2 C926 DIS@ 1 2 C927 DIS@ 1 2 C928 DIS@ 1 2 1U_0402_6.3V6K 2 1 R812 470_0603_5% DIS@ 2N7002DWH_SOT363-6 4 31 6 R814 DIS@ 1K_0402_5% 2 1 1 C930 DIS@ 10U_0805_10V4Z 2 1 38,42,50 VGA_ON 2 1 2 R813 DIS@ 3.3K_0402_5% 2 10K_0402_5% DIS@ 4.7U_0603_6.3V6M 1 2 C934 1 OPT@ DIS ONLY@ 0.1U_0402_16V4Z DIS ONLY@ 0.1U_0402_16V4Z DIS ONLY@ 4.7U_0603_6.3V6M DIS ONLY@ 1U_0402_6.3V6K 1 C934 3VSdelay_gate A 1 2 DIS@ G 2 C933 100mil(1.5A) D 2 2 R811 100K_0402_5% C1036 +VGA_CORE AO3413L_SOT23-3 Q56 3 1 DIS@ 385 mA IFPC_IOVDD DIS@ 2 0_0805_5% S BLM18PG181SN1D_0603 2 1 L86 DIS ONLY@ 1 1 C931 C932 C1035 22U_0805_6.3V6M DIS@ 10U_0805_10V4Z 2 DIS@ 22U_0805_6.3V6M C929 1 C1034 0.047U_0402_16V7K DIS@ +3VSDGPU 0.047U_0402_16V7K C1037 2 10K_0402_5% 0.047U_0402_16V7K +3VS C1052 1 0.22U_0603_16V7K C1052 22U_0805_6.3V6M 1 +3VALW +1.05VSDGPU +VGA_CORE DIS@ Q57B 3VSdelay_gate 5 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 VDD_72 VDD_73 VDD_74 VDD_75 VDD_76 VDD_77 VDD_78 VDD_79 VDD_80 VDD_81 VDD_82 VDD_83 VDD_84 VDD_85 VDD_86 VDD_87 VDD_88 VDD_89 VDD_90 VDD_91 VDD_92 VDD_93 VDD_94 VDD_95 VDD_96 VDD_97 VDD_98 VDD_99 VDD_100 VDD_101 VDD_102 VDD_103 VDD_104 VDD_105 VDD_106 VDD_107 VDD_108 VDD_109 VDD_110 Part 7 of 7 POWER IFPF_IOVDD +3VSDGPU 4700P_0402_16V7K 1 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AD12 AD14 AD16 AD18 AD22 AD24 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 M12 M14 M16 M18 M20 M22 M24 P11 P13 P15 P17 P19 0.01U_0402_16V7K IFPE_IOVDD 330U_D2_2V_Y 1 2 120mA 2 1 +3VSDGPU 0_0603_5% DIS@ U51G N11P-GE1-B-A2_BGA969 @ OPT@ C922 DIS ONLY@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 DIS ONLY@ 1 C921 DIS ONLY@ 0.1U_0402_16V4Z 2 2 120mA +VGA_CORE 160 mA C920 2200mA PEX_SVDD_3V3 R803 4700P_0402_16V7K IFPEF_PLLVDD IFPEF_RSET AA9 AB9 W9 Y9 +1.8VS DIS ONLY@ 2 1 +1.05VSDGPU +VGA_CORE MIOB_VDDQ_0 MIOB_VDDQ_1 MIOB_VDDQ_2 MIOB_VDDQ_3 IFPC_PLLVDD 4.7U_0603_6.3V6M C919 DIS ONLY@ 1U_0402_6.3V6K 1 C880 DIS@ 2 PEX_IOVDD 1 4.7U_0603_6.3V6M 1 1U_0603_10V4Z 2 C1026 DIS@ 0.1U_0402_16V4Z 1 0.22U_0603_16V7K BLM18PG181SN1D_0603 D 1 C890 DIS@ +VGA_CORE 1 L85 DIS ONLY@ C1041 DIS@ 2 1 L82 DIS@ BLM18PG181SN1D_0603 0.01U_0402_16V7K AJ6 AL1 follow the DS04644 2 22U_0805_6.3V6M C878 DIS@ 2 10U_0805_6.3V6M 4.7U_0603_6.3V6M 1U_0603_10V4Z 1U_0402_6.3V6K 2 1 1 +3VS_DELAY +3VSDGPU 1 0.1U_0402_16V4Z 1 +3VSDGPU P9 R9 T9 U9 IFPD_IOVDD DIS@ AD7 C1050 1 J10 J11 J12 J13 J9 0.1U_0402_16V4Z VDD33_0 VDD33_1 VDD33_2 VDD33_3 VDD33_4 PWR Sequence B +1.05VSDGPU 22U_0805_6.3V6M 1 10U_0805_6.3V6M 4.7U_0603_6.3V6M 1U_0603_10V4Z 0.1U_0402_16V4Z 1U_0603_10V4Z 0.01U_0402_25V7K 1U_0603_10V4Z 0.1U_0402_16V4Z 4.7U_0603_6.3V6M 2 C889 DIS@ C877 DIS@ 1 0.01U_0402_16V7K 1 C1050 1 2 0.022U_0402_16V7K 1 2 C1043 DIS@ 1 4.7U_0603_6.3V6M AG19 F7 IFPD_PLLVDD IFPD_RSET DIS@ AE7 OPT@ C1049 DIS ONLY@ 2 2 C888 DIS@ C1033 DIS@ 1 0.01U_0402_16V7K R809 1 2 1K_0402_1% R861 1 2 1K_0402_1% 0.1U_0402_16V4Z C913 PEX_SVDD_3V3_0 PEX_SVDD_3V3_1 IFPC_IOVDD AC6 AB6 AK8 1K_0402_5% 1 DIS@ 2 R807 IFPE_RSET 1K_0402_1% 2 DIS@ 1 R808 IFPB_IOVDD 1 2 0.022U_0402_16V7K 2 10K_0402_5% C876 DIS@ 2 0.01U_0402_16V7K 1 DIS ONLY@ 2 0.1U_0402_16V4Z 1U_0402_6.3V6K 2 1 DIS ONLY@ C912 DIS ONLY@ 4.7U_0603_6.3V6M 1 PEX_PLLDVDD IFPC_PLLVDD IFPC_RSET AJ8 IFPC_IOVDD +1.8VSDGPU 2 1 L88 DIS ONLY@ BLM18PG181SN1D_0603 AG14 IFPA_IOVDD IFPB_IOVDD AJ9 AK7 IFPC_PLLVDD DIS@ 1 R806 IFPD_RSET 1K_0402_1% 2 C1048 1 C1048 2 C887 DIS@ 1 0.022U_0402_16V7K 2 C875 DIS@ 2 1 0.01U_0402_16V7K 1 AG9 AG10 IFPC_PLLVDD 2 1 IFPC_RSET DIS@ R805 1K_0402_1% IFPC_IOVDD OPT@ C903 DIS ONLY@ 2 0.1U_0402_16V4Z 2 C902 C1047 DIS@ 1 2 PEX_PLLVDD PEX_PLLVDD IFPA_IOVDD DIS ONLY@ 2 1 0.1U_0402_16V4Z 1U_0402_6.3V6K C901 DIS ONLY@ 1 DIS ONLY@ 1 L84 DIS ONLY@ BLM18PG181SN1D_0603 4.7U_0603_6.3V6M 100 mA #SI Change to +VDDMEM18 2 2 +3VSDGPU IFPA_IOVDD IFPB_IOVDD 2 10K_0402_5% +1.8VSDGPU PEX_IOVDD AK16 AK17 AK21 AK24 AK27 1 PEX_SVDD_3V3 IFPAB_PLLVDD IFPAB_RSET C1045 DIS@ 2 1U_0603_10V4Z 1K_0402_1% 2 R804 @ PEX_PLLDVDD 0.022U_0402_16V7K C895 1 C1053 IFPAB_PLLVDD AK9 IFPAB_RSET AJ11 1 C1044 DIS@ 2 1 +1.05VSDGPU 0.1U_0402_16V4Z 2 OPT@ 1 DIS ONLY@ 2 0.1U_0402_16V4Z 1 C896 0.1U_0402_16V4Z 2 DIS ONLY@ C894 1 1 C895 PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 1 0.1U_0402_16V4Z C884 DIS@ 0.1U_0402_16V4Z C874 DIS@ 0.047U_0402_16V7K C873 DIS@ 0.047U_0402_16V7K C872 DIS@ 2 IFPAB_PLLVDD DIS ONLY@ 1U_0402_6.3V6K 2 follow the DS04644 DIS ONLY@ 0.1U_0402_16V4Z DIS ONLY@ 4.7U_0603_6.3V6M C C893 2 1 100mA BLM18PG181SN1D_0603 2 1 L83 DIS ONLY@ 1 2 DIS@ C870 0.047U_0402_16V7K C869 0.1U_0402_16V4Z 2 1 PEX_IOVDDQ PEX_IOVDD 0.1U_0402_16V4Z +1.05VSDGPU 1 DIS@ 0.1U_0402_16V4Z FBVDDQ PEX_IOVDDQ AG11 AG12 AG13 AG15 AG16 AG17 AG18 AG22 AG23 AG24 AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16 0.1U_0402_16V4Z D PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14 PEX_IOVDDQ_15 PEX_IOVDDQ_16 PEX_IOVDDQ_17 PEX_IOVDDQ_18 PEX_IOVDDQ_19 PEX_IOVDDQ_20 PEX_IOVDDQ_21 PEX_IOVDDQ_22 PEX_IOVDDQ_23 PEX_IOVDDQ_24 0.1U_0402_16V4Z FBVDDQ FBVDDQ_0 FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 POWER J23 J24 J29 AA27 AA29 AA31 AB27 AB29 AC27 AD27 AE27 AJ28 B18 E21 G17 G18 G22 G8 G9 H29 J14 J15 J16 J17 J20 J21 J22 N27 P27 R27 T27 U27 U29 V27 V29 V34 W27 Y27 DIS@ C1051 C868 0.01U_0402_16V7K 0.01U_0402_16V7K DIS@ C867 DIS@ C866 0.01U_0402_16V7K DIS@ C865 2 0.01U_0402_16V7K 1 DIS@ C864 2 0.1U_0402_16V4Z C863 2 1 DIS@ 1 4.7U_0603_6.3V6M 2 4.7U_0603_6.3V6M 2 1 DIS@ 22U_0805_6.3V6M 1 DIS@ C1040 DIS@ C1039 22U_0805_6.3V6M FBVDDQ 0.1U_0402_16V4Z Part 5 of 7 +1.5VSDGPU P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17 V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24 B A 2 N11P-GE1-B-A2_BGA969 @ Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/5/12 Deciphered Date 2009/12/31 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Sheet Wednesday, June 30, 2010 1 24 of 56
  • 25.
    A VRAM Interface MDC[15..0] MDA[15..0] MDA[31..16] 26 MDA[31..16] 27MDC[47..32] MDA[63..48] 26 MDA[63..48] U51C U51B CMDA[30..0] Part 2 of 7 MDA0 L32 MDA1 N33 MDA2 L33 MDA3 N34 MDA4 N35 MDA5 P35 MDA6 P33 MDA7 P34 MDA8 K35 MDA9 K33 MDA10 K34 MDA11 H33 MDA12 G34 MDA13 G33 MDA14 E34 MDA15 E33 MDA16 G31 MDA17 F30 MDA18 G30 MDA19 G32 MDA20 K30 MDA21 K32 MDA22 H30 MDA23 K31 MDA24 L31 MDA25 L30 MDA26 M32 MDA27 N30 MDA28 M30 MDA29 P31 MDA30 R32 MDA31 R30 MDA32 AG30 MDA33 AG32 MDA34AH31 MDA35AF31 MDA36AF30 MDA37AE30 MDA38AC32 MDA39AD30 MDA40AN33 MDA41AL31 MDA42 AM33 MDA43AL33 MDA44AK30 MDA45AK32 MDA46 AJ30 MDA47AH30 MDA48AH33 MDA49AH35 MDA50AH34 MDA51AH32 MDA52 AJ33 MDA53AL35 MDA54 AM34 MDA55 AM35 MDA56AF33 MDA57AE32 MDA58AF34 MDA59AE35 MDA60AE34 MDA61AE33 MDA62AB32 MDA63AC35 FB_PLLAVDD AG27 AF27 FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 MEMORY INTERFACE A 1 FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 P32 H34 J30 P30 AF32 AL32 AL34 AF35 MDC0 MDC1 MDC2 MDC3 MDC4 MDC5 MDC6 MDC7 MDC8 MDC9 MDC10 MDC11 MDC12 MDC13 MDC14 MDC15 MDC16 MDC17 MDC18 MDC19 MDC20 MDC21 MDC22 MDC23 MDC24 MDC25 MDC26 MDC27 MDC28 MDC29 MDC30 MDC31 MDC32 MDC33 MDC34 MDC35 MDC36 MDC37 MDC38 MDC39 MDC40 MDC41 MDC42 MDC43 MDC44 MDC45 MDC46 MDC47 MDC48 MDC49 MDC50 MDC51 MDC52 MDC53 MDC54 MDC55 MDC56 MDC57 MDC58 MDC59 MDC60 MDC61 MDC62 MDC63 DQSA#[3..0] DQSA0 L34 H35 DQSA1 DQSA2 J32 N31 DQSA3 AE31 DQSA4 AJ32 DQSA5 AJ34 DQSA6 AC33 DQSA7 26 DQSA#[7..4] L35 DQSA#0 G35 DQSA#1 H31 DQSA#2 N32 DQSA#3 AD32 DQSA#4 AJ31 DQSA#5 AJ35 DQSA#6 AC34 DQSA#7 FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 DQMA[7..4] 26 26 DQSA[3..0] 26 DQSA[7..4] 26 +1.5VSDGPU B13 D13 A13 A14 C16 B16 A17 D16 C13 B11 C11 A11 C10 C8 B8 A8 E8 F8 F10 F9 F12 D8 D11 E11 D12 E13 F13 F14 F15 E16 F16 F17 D29 F27 F28 E28 D26 F25 D24 E25 E32 F32 D33 E31 C33 F29 D30 E29 B29 C31 C29 B31 C32 B32 B35 B34 A29 B28 A28 C28 C26 D25 B25 A25 40.2_0402_1% 2 DIS@ 1 R815 K27 FBCAL_PD_VDDQ 40.2_0402_1% 2 FBA_CLK0 FBA_CLK0_N T32 T31 FBA_CLK1 FBA_CLK1_N AC31 AC30 DQMC[3..0] 27 DQMC[7..4] 27 DQSC#[3..0] 27 DQSC#[7..4] 27 DQSC[3..0] 27 DQSC[7..4] 27 DIS@ 1 R817 M27 FBCAL_TERM_GND CMDC0 CMDC1 CMDC2 CMDC3 CMDC4 CMDC5 CMDC6 CMDC7 CMDC8 CMDC9 CMDC10 CMDC11 CMDC12 CMDC13 CMDC14 CMDC15 CMDC16 CMDC17 CMDC18 CMDC19 CMDC20 CMDC21 CMDC22 CMDC23 CMDC24 CMDC25 CMDC26 CMDC27 CMDC28 CMDC29 CMDC30 FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3 FBC_DQM4 FBC_DQM5 FBC_DQM6 FBC_DQM7 A16 D10 F11 D15 D27 D34 A34 D28 DQMC0 DQMC1 DQMC2 DQMC3 DQMC4 DQMC5 DQMC6 DQMC7 FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7 B14 B10 D9 E14 F26 D31 A31 A26 DQSC#0 DQSC#1 DQSC#2 DQSC#3 DQSC#4 DQSC#5 DQSC#6 DQSC#7 C14 A10 E10 D14 E26 D32 A32 B26 DQSC0 DQSC1 DQSC2 DQSC3 DQSC4 DQSC5 DQSC6 DQSC7 FBC_CLK0 FBC_CLK0_N E17 D17 CLKC0 27 CLKC0# 27 FBC_CLK1 FBC_CLK1_N D23 E23 CLKC1 27 CLKC1# 27 2 G19 1 @ 10K_0402_5% R818 FBCAL_PU_GND 40.2_0402_1% 2 CLKA0 26 CLKA0# 26 DIS@ 1 R816 L27 CLKA1 26 CLKA1# 26 FB_VREF J27 FB_VREF +1.5VSDGPU 2 1 T30 R819 10K_0402_5% @ FBA_DEBUG 27 C17 B19 D18 F21 A23 D21 B23 E20 G21 F20 F19 F23 A22 C22 B17 F24 C25 E22 C20 B22 A19 D22 D20 E19 D19 F18 C19 F22 C23 B20 A20 FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7 FBC_D00 FBC_D01 FBC_D02 FBC_D03 FBC_D04 FBC_D05 FBC_D06 FBC_D07 FBC_D08 FBC_D09 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63 FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8 FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30 FBC_DEBUG DQMA[3..0] 26 DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7 CMDC[30..0] Part 3 of 7 26 V32 CMDA0 W31 CMDA1 U31 CMDA2 Y32 CMDA3 AB35 CMDA4 AB34 CMDA5 W35 CMDA6 W33 CMDA7 W30 CMDA8 T34 CMDA9 T35 CMDA10 AB31 CMDA11 Y30 CMDA12 Y34 CMDA13 W32 CMDA14 AA30 CMDA15 AA32 CMDA16 Y33 CMDA17 U32 CMDA18 Y31 CMDA19 U34 CMDA20 Y35 CMDA21 W34 CMDA22 V30 CMDA23 U35 CMDA24 U30 CMDA25 U33 CMDA26 AB30 CMDA27 AB33 CMDA28 T33 CMDA29 W29 CMDA30 FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7 FB_DLLAVDD FB_PLLAVDD MDC[63..48] 27 MDC[63..48] MDA[47..32] 26 MDA[47..32] MDC[47..32] MEMORY INTERFACE C 26 MDA[15..0] U51F MDC[31..16] 27 MDC[31..16] +1.5VSDGPU N11P-GE1-B-A2_BGA969 @ +1.5VSDGPU 1 N11P-GE1-B-A2_BGA969 @ Rt 2 R820 @ 1K_0402_1% FB_VREF GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 Part 6 of 7 GND_97 GND_98 GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 V18 V20 V22 V24 V31 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25 AA2 AA5 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA34 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC9 AD2 AD5 AD11 AD13 AD15 AD17 AD21 AD23 AD25 AD31 AD34 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AG2 AG5 AG31 AG34 AK2 AK5 AK14 AK31 AK34 AL6 AL9 AL12 AL15 AL18 AL21 AL24 AL27 AL30 AN2 AN34 AP3 AP6 AP9 AP12 AP15 AP18 AP21 AP24 AP27 AP30 AP33 1 1 1 +1.05VSDGPU L87 DIS@ BLM18PG181SN1D_0603 R821 @ 1K_0402_1% Rb 0.1U_0402_16V4Z 2 C940 C939 1 DIS@ 2 DIS@ 2 1 4.7U_0603_6.3V6M 2 C937 DIS@ 1 DIS@ C938 0.01U_0402_25V7K 1 1U_0402_6.3V6K 0.1U_0402_16V4Z 2 2 FB_PLLAVDD B3 B6 B9 B12 B15 B21 B24 B27 B30 B33 C2 C34 E6 E9 E12 E15 E18 E24 E27 E30 F2 F31 F34 F5 J2 J5 J31 J34 K9 L9 M2 M5 M11 M13 M15 M17 M19 M21 M23 M25 M31 M34 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 P12 P14 P16 P18 P20 P22 P24 R2 R5 R31 R34 T11 T13 T15 T17 T19 T21 T23 T25 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 V2 V5 V9 V12 V14 V16 GND 27 MDC[15..0] 1 2 C941 @ N11P-GE1-B-A2_BGA969 @ Compal Electronics, Inc. Compal Secret Data Security Classification 2009/5/12 Issued Date Deciphered Date 2009/12/31 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: A Wednesday, June 30, 2010 Sheet 25 of 56
  • 26.
    5 4 3 2 CMDA0 CMDA25 CMDA28 CMDA16 CMDA27 DQSA#[7..0] DQMA[7..0] MDA[63..0] 25 MDA[63..0] U54 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% X76@ U55 DQMA[7..0] 25 DQMA[7..0] CMDA[30..0] 25CMDA[30..0] DQSA#[7..0] 25 DQSA#[7..0] MODE C PULL DOWN SIGNAL:RST，CKE，ODT CMDA[30..0] 25 CMDA[30..0] 1 1 1 1 1 DQSA[7..0] 25 DQSA[7..0] MDA[63..0] 25 MDA[63..0] X76@ U56 VDD VDD VDD VDD VDD VDD VDD VDD VDD B2 D9 G7 K2 K8 N1 N9 R1 R9 E7 D3 G3 B7 CMDA28 DQSL DQSU T2 RESET L8 ZQ/ZQ0 E7 D3 DML DMU DQSA#0 DQSA#3 G3 B7 DQSL DQSU A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 CMDA28 T2 RESET ZQA1 L8 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ZQ/ZQ0 1 DIS@ R833 C944 1K_0402_1% DIS@ 1 2 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 B2 D9 G7 K2 K8 N1 N9 R1 R9 2 MEM_VREFA2 1 DIS@ R834 C945 1K_0402_1% DIS@ DIS@ CLKA0# 2 CMDA16 CMDA11 CMDA24 CMDA8 CMDA21 E3 F7 F2 F8 H3 H8 G2 H7 MDA43 MDA45 MDA40 MDA44 MDA41 MDA47 MDA42 MDA46 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDA51 MDA52 MDA48 MDA54 MDA49 MDA55 MDA50 MDA53 VDD VDD VDD VDD VDD VDD VDD VDD VDD B2 D9 G7 K2 K8 N1 N9 R1 R9 CLKA1 J7 CLKA1# K7 CMDA27 K9 CK CK CKE/CKE0 C F3 C7 +1.5VSDGPU VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ VDDQ DQSL VDDQ DQSU VDDQ A1 A8 C1 C9 D2 E9 F1 H2 H9 CMDA16 CMDA11 CMDA24 CMDA8 CMDA21 K1 L2 J3 K3 L3 DQSA5 DQSA6 F3 C7 DML DMU DQSL DQSU CMDA28 T2 CLKA1# 25 CLKA1# D +1.5VSDGPU BA0 BA1 BA2 DQSA#7 G3 DQSA#4 B7 R836 240_0402_1% K1 L2 J3 K3 L3 DQSA7 DQSA4 CLKA1 25 CLKA1 R835 240_0402_1% DIS@ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 CMDA12 M2 CMDA14 N8 CMDA30 M3 RESET VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 L8 ZQ/ZQ0 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B1 B9 D1 D8 E2 E8 F9 G1 G9 J1 L1 J9 L9 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 ZQA2 B1 B9 D1 D8 E2 E8 F9 G1 G9 DIS@ L8 J1 L1 J9 L9 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 ODT/ODT0 CS/CS0 RAS CAS WE ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ VDDQ DQSL VDDQ DQSU VDDQ A1 A8 C1 C9 D2 E9 F1 H2 H9 DQMA5 E7 DQMA6 D3 DML DMU DQSA#5 G3 DQSA#6 B7 DQSL DQSU CMDA28 T2 RESET VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B1 B9 D1 D8 E2 E8 F9 G1 G9 ZQA3 R840 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 CMDA22 N3 CMDA4 P7 CMDA20 P3 CMDA9 N2 CMDA6 P8 CMDA17 P2 CMDA3 R8 CMDA26 R2 CMDA1 T8 CMDA5 R3 CMDA19 L7 CMDA10 R7 CMDA7 N7 CMDA29 T3 CMDA18 T7 CMDA13 M7 DIS@ 243_0402_1% DIS@ J1 L1 J9 L9 CK CK CKE/CKE0 243_0402_1% B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ MDA33 MDA38 MDA32 MDA37 MDA34 MDA39 MDA35 MDA36 VDD VDD VDD VDD VDD VDD VDD VDD VDD VREFCA VREFDQ +1.5VSDGPU R839 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 MEM_VREFA3 1 CLKA0 25 CLKA0 25 CLKA0# J1 L1 J9 L9 D7 C3 C8 C2 A7 A2 B8 A3 X76@ MEM_VREFA3 M8 H1 DQMA7 E7 DQMA4 D3 1 DQMA0 DQMA3 R838 DIS@ 2 F3 C7 A1 A8 C1 C9 D2 E9 F1 H2 H9 243_0402_1% R837 B 243_0402_1% 243_0402_1% 1 ZQA0 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSA0 DQSA3 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ DQSL VDDQ DQSU VDDQ ODT/ODT0 CS/CS0 RAS CAS WE 1 DQSA#2 DQSA#1 DML DMU K1 L2 J3 K3 L3 2 DQMA2 DQMA1 CMDA25 CMDA2 CMDA24 CMDA8 CMDA19 2 F3 C7 VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ VDDQ DQSL VDDQ DQSU VDDQ MDA57 MDA63 MDA62 MDA61 MDA59 MDA56 MDA60 MDA58 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 BA0 BA1 BA2 CLKA1 J7 CLKA1# K7 CMDA27 K9 R832 1K_0402_1% DIS@ 0.1U_0402_10V6K~D DQSA2 DQSA1 +1.5VSDGPU A1 A8 C1 C9 D2 E9 F1 H2 H9 ODT/ODT0 CS/CS0 RAS CAS WE 2 R831 1K_0402_1% DIS@ E3 F7 F2 F8 H3 H8 G2 H7 +1.5VSDGPU CMDA12 M2 CMDA14 N8 CMDA30 M3 +1.5VSDGPU 0.1U_0402_10V6K~D K1 L2 J3 K3 L3 1 +1.5VSDGPU +1.5VSDGPU CMDA25 CMDA2 CMDA24 CMDA8 CMDA19 2 2 +1.5VSDGPU MEM_VREFA1 1 DIS@ R830 C943 1K_0402_1% DIS@ 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 1 CK CK CKE/CKE0 DIS@ R829 C942 1K_0402_1% DIS@ MEM_VREFA0 1 U57 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VREFCA VREFDQ 2 J7 K7 K9 CLKA0 CLKA0# CMDA0 DIS@ 1 C BA0 BA1 BA2 R827 1K_0402_1% CMDA22 N3 CMDA4 P7 CMDA20 P3 CMDA9 N2 CMDA6 P8 CMDA17 P2 CMDA3 R8 CMDA26 R2 CMDA1 T8 CMDA5 R3 CMDA19 L7 CMDA10 R7 CMDA7 N7 CMDA29 T3 CMDA18 T7 CMDA13 M7 R828 1K_0402_1% DIS@ 2 CK CK CKE/CKE0 M2 N8 M3 MDA27 MDA26 MDA31 MDA28 MDA29 MDA25 MDA30 MDA24 MEM_VREFA2 M8 H1 +1.5VSDGPU 1 J7 K7 K9 CLKA0 CLKA0# CMDA0 CMDA12 CMDA9 CMDA13 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD D7 C3 C8 C2 A7 A2 B8 A3 +1.5VSDGPU 2 BA0 BA1 BA2 +1.5VSDGPU A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 MDA0 MDA7 MDA1 MDA4 MDA3 MDA6 MDA2 MDA5 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 E3 F7 F2 F8 H3 H8 G2 H7 1 M2 N8 M3 MDA13 MDA11 MDA14 MDA10 MDA12 MDA8 MDA15 MDA9 CMDA7 CMDA20 CMDA4 CMDA14 CMDA17 CMDA6 CMDA26 CMDA3 CMDA1 CMDA10 CMDA21 CMDA5 CMDA22 CMDA18 CMDA29 CMDA30 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 2 CMDA12 CMDA9 CMDA13 D7 C3 C8 C2 A7 A2 B8 A3 VREFCA VREFDQ 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 MEM_VREFA1 M8 H1 0.1U_0402_10V6K~D N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 MDA21 MDA18 MDA23 MDA16 MDA22 MDA19 MDA20 MDA17 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 CMDA7 CMDA20 CMDA4 CMDA14 CMDA17 CMDA6 CMDA26 CMDA3 CMDA1 CMDA10 CMDA21 CMDA5 CMDA22 CMDA18 CMDA29 CMDA30 E3 F7 F2 F8 H3 H8 G2 H7 0.1U_0402_10V6K~D DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VREFCA VREFDQ 2 MEM_VREFA0 M8 H1 X76@ 1 25 DQMA[7..0] R822 R823 R824 R825 R826 2 25 DQSA[7..0] 25 DQSA#[7..0] D 1 DQSA[7..0] 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 ODT/ODT0 CS/CS0 RAS CAS WE B 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 +1.5VSDGPU +1.5VSDGPU 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 2 2 2 2 2 2 2 1 2 4.7U_0603_6.3V6M 2 1 4.7U_0603_6.3V6M C964 2 1 4.7U_0603_6.3V6M C963 2 1 4.7U_0603_6.3V6M C962 2 1 4.7U_0603_6.3V6M C961 2 1 4.7U_0603_6.3V6M C960 2 1 4.7U_0603_6.3V6M C959 2 1 4.7U_0603_6.3V6M C958 2 1 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ A DIS@ Compal Electronics, Inc. Compal Secret Data Security Classification DIS@ DIS@ 2 C956 4.7U_0603_6.3V6M 2 4.7U_0603_6.3V6M C983 2 4.7U_0603_6.3V6M C982 2 4.7U_0603_6.3V6M C981 2 4.7U_0603_6.3V6M C980 2 4.7U_0603_6.3V6M C979 2 4.7U_0603_6.3V6M C978 2 4.7U_0603_6.3V6M C977 2 4.7U_0603_6.3V6M C976 C975 0.1U_0402_16V4Z 0.1U_0402_16V4Z C974 0.1U_0402_16V4Z C973 C972 0.1U_0402_16V4Z 0.1U_0402_16V4Z C971 0.1U_0402_16V4Z C970 0.1U_0402_16V4Z C969 0.1U_0402_16V4Z C968 0.1U_0402_16V4Z C967 C965 1000P_0402_50V7K C966 2 1 2 1 0.1U_0402_16V7K 0.1U_0402_16V7K 2 1 2 1 C955 0.1U_0402_16V7K 2 1 1 1 C954 0.1U_0402_16V7K 2 1 1 1 C953 C953 0.1U_0402_16V7K 2 1 1 1 C952 0.1U_0402_16V7K 0.1U_0402_16V7K 2 1 1 1 C951 0.1U_0402_16V7K 2 1 1 1 C950 1U_0402_6.3V6K 2 1 1 1 C949 C949 1U_0402_6.3V6K 2 1 1 1 C948 1U_0402_6.3V6K 1 1 1 C947 1U_0402_6.3V6K 1U_0402_6.3V6K A 1 C946 +1.5VSDGPU 4.7U_0603_6.3V6M C957 +1.5VSDGPU 2009/5/12 Issued Date Deciphered Date 2010/04/15 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 26 of 56
  • 27.
    3 2 DQSC[7..0] 25 DQSC[7..0] CMDC0 CMDC25 CMDC28 CMDC27 CMDC16 DQSC#[7..0] 25 DQSC#[7..0] DQMC[7..0] 25DQMC[7..0] R841 R842 R843 R844 R847 1 1 1 1 1 MDC[63..0] 25 MDC[63..0] U58 2 2 2 2 2 DQMC[7..0] 25 DQMC[7..0] 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% DQSC#[7..0] 25 DQSC#[7..0] DQSC[7..0] 25 DQSC[7..0] MDC[63..0] 25 MDC[63..0] X76@ U59 U60 RAM BIT SWAP 20091211 60->60 62->58 58->63 63->57 59->56 56->62 57->61 61->59 CMDC[30..0] 25 CMDC[30..0] MODE C PULL DOWN SIGNAL:RST，CKE，ODT CMDC[30..0] 25 CMDC[30..0] DIS@ DIS@ DIS@ DIS@ DIS@ 1 X76@ U60 B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.5VSDGPU A1 A8 C1 C9 D2 E9 F1 H2 H9 CMDC25 CMDC2 CMDC24 CMDC8 CMDC19 K1 L2 J3 K3 L3 F3 C7 VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ VDDQ DQSL VDDQ DQSU VDDQ DQSC0 DQSC3 DQMC2 DQMC1 E7 D3 DML DMU DQSC#2 DQSC#1 G3 B7 DQSL DQSU A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 F3 C7 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ DQSL VDDQ DQSU VDDQ DQMC0 DQMC3 E7 D3 DML DMU DQSC#0 DQSC#3 G3 B7 DQSL DQSU A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 T2 RESET L8 ZQ/ZQ0 RESET L8 ZQ/ZQ0 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 1 2 1 M2 N8 M3 CLKC1 CLKC1# CMDC27 J7 K7 K9 CK CK CKE/CKE0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 E3 F7 F2 F8 H3 H8 G2 H7 MDC44 MDC43 MDC42 MDC47 MDC41 MDC45 MDC40 MDC46 D7 C3 C8 C2 A7 A2 B8 A3 B2 D9 G7 K2 K8 N1 N9 R1 R9 D MDC48 MDC53 MDC51 MDC54 MDC49 MDC55 MDC50 MDC52 VDD VDD VDD VDD VDD VDD VDD VDD VDD BA0 BA1 BA2 +1.5VSDGPU K1 L2 J3 K3 L3 DQSC5 DQSC6 DML DMU DQSC#7 G3 DQSC#4 B7 DQSL DQSU CMDC28 T2 CLKC1# CMDC16 CMDC11 CMDC24 CMDC8 CMDC21 DQMC7 E7 DQMC4 D3 R855 240_0402_1% A1 A8 C1 C9 D2 E9 F1 H2 H9 RESET VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B1 B9 D1 D8 E2 E8 F9 G1 G9 ZQC2 B1 B9 D1 D8 E2 E8 F9 G1 G9 DIS@ ODT/ODT0 CS/CS0 RAS CAS WE L8 ZQ/ZQ0 J1 L1 J9 L9 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 C +1.5VSDGPU DQSC7 F3 DQSC4 C7 1 1 2 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 CMDC12 CMDC14 CMDC30 F3 C7 VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ VDDQ DQSL VDDQ DQSU VDDQ A1 A8 C1 C9 D2 E9 F1 H2 H9 DQMC5 DQMC6 E7 D3 DML DMU DQSC#5 DQSC#6 G3 B7 DQSL DQSU CMDC28 T2 RESET L8 ZQ/ZQ0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 J1 L1 J9 L9 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B1 B9 D1 D8 E2 E8 F9 G1 G9 ZQC3 R859 R859 DIS@ J1 L1 J9 L9 25 CLKC1# DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DIS@ 243_0402_1% B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ DIS@ CLKC0# 2 CLKC1 R854 240_0402_1% DIS@ B2 D9 G7 K2 K8 N1 N9 R1 R9 X76@ VREFCA VREFDQ CMDC22 CMDC4 CMDC20 CMDC9 CMDC6 CMDC17 CMDC3 CMDC26 CMDC1 CMDC5 CMDC19 CMDC10 CMDC7 CMDC29 CMDC18 CMDC13 VDDQ VDDQ VDDQ VDDQ VDDQ 310mA VDDQ VDDQ DQSL VDDQ DQSU VDDQ K1 L2 J3 K3 L3 243_0402_1% 243_0402_1% NC/ODT1 NC/CS1 NC/CE1 NCZQ1 DIS@ R853 C987 1K_0402_1% DIS@ 25 CLKC1 MDC35 MDC39 MDC32 MDC36 MDC33 MDC38 MDC34 MDC37 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 CMDC16 CMDC11 CMDC24 CMDC8 CMDC21 MEM_VREFC3 1 R858 J1 L1 J9 L9 2 CLKC0 25 CLKC0 25 CLKC0# R857 DIS@ 2 T2 ZQC1 243_0402_1% 243_0402_1% R856 B 243_0402_1% 1 ZQC0 CMDC28 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS D7 C3 C8 C2 A7 A2 B8 A3 MEM_VREFC3 M8 H1 +1.5VSDGPU 2 CMDC28 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS MDC60 MDC58 MDC63 MDC57 MDC56 MDC62 MDC61 MDC59 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 BA0 BA1 BA2 CLKC1 J7 CLKC1# K7 CMDC27 K9 R851 1K_0402_1% DIS@ MEM_VREFC2 1 DIS@ R852 C986 1K_0402_1% DIS@ 2 E3 F7 F2 F8 H3 H8 G2 H7 +1.5VSDGPU CMDC12 M2 CMDC14 N8 CMDC30 M3 1 R850 1K_0402_1% DIS@ A1 A8 C1 C9 D2 E9 F1 H2 H9 ODT/ODT0 CS/CS0 RAS CAS WE DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 +1.5VSDGPU 2 DQSC2 DQSC1 ODT/ODT0 CS/CS0 RAS CAS WE MEM_VREFC1 1 DIS@ R849 C985 1K_0402_1% DIS@ 2 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D K1 L2 J3 K3 L3 2 0.1U_0402_10V6K~D CMDC25 CMDC2 CMDC24 CMDC8 CMDC19 MEM_VREFC0 1 +1.5VSDGPU +1.5VSDGPU A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 2 CK CK CKE/CKE0 DIS@ R846 C984 1K_0402_1% DIS@ +1.5VSDGPU VDD VDD VDD VDD VDD VDD VDD VDD VDD DIS@ 1 J7 K7 K9 R848 1K_0402_1% CMDC22 N3 CMDC4 P7 CMDC20 P3 CMDC9 N2 CMDC6 P8 CMDC17 P2 CMDC3 R8 CMDC26 R2 CMDC1 T8 CMDC5 R3 CMDC19 L7 CMDC10 R7 CMDC7 N7 CMDC29 T3 CMDC18 T7 CMDC13 M7 U61 VREFCA VREFDQ R845 1K_0402_1% DIS@ 2 CLKC0 CLKC0# CMDC0 MDC29 MDC26 MDC31 MDC25 MDC30 MDC27 MDC28 MDC24 X76@ MEM_VREFC2 M8 H1 +1.5VSDGPU 1 CK CK CKE/CKE0 BA0 BA1 BA2 D7 C3 C8 C2 A7 A2 B8 A3 +1.5VSDGPU 2 J7 K7 K9 M2 N8 M3 MDC3 MDC7 MDC0 MDC5 MDC2 MDC6 MDC1 MDC4 1 CLKC0 CLKC0# CMDC0 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 CMDC12 CMDC9 CMDC13 +1.5VSDGPU N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 E3 F7 F2 F8 H3 H8 G2 H7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 CMDC7 CMDC20 CMDC4 CMDC14 CMDC17 CMDC6 CMDC26 CMDC3 CMDC1 CMDC10 CMDC21 CMDC5 CMDC22 CMDC18 CMDC29 CMDC30 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 2 BA0 BA1 BA2 MDC15 MDC11 MDC13 MDC9 MDC12 MDC8 MDC14 MDC10 VREFCA VREFDQ 1 M2 N8 M3 D7 C3 C8 C2 A7 A2 B8 A3 MEM_VREFC1 M8 H1 0.1U_0402_10V6K~D A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 CMDC12 CMDC9 CMDC13 C N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 MDC22 MDC16 MDC23 MDC19 MDC18 MDC17 MDC20 MDC21 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 CMDC7 CMDC20 CMDC4 CMDC14 CMDC17 CMDC6 CMDC26 CMDC3 CMDC1 CMDC10 CMDC21 CMDC5 CMDC22 CMDC18 CMDC29 CMDC30 E3 F7 F2 F8 H3 H8 G2 H7 0.1U_0402_10V6K~D DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VREFCA VREFDQ 2 MEM_VREFC0 M8 H1 1 D 1 4 2 5 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 ODT/ODT0 CS/CS0 RAS CAS WE B 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 +1.5VSDGPU DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 2 2 DIS@ DIS@ 2 2 2 2 1 2 1 2 1 2 2009/5/12 Issued Date 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ Deciphered Date Compal Electronics, Inc. 2010/04/15 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 A DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ Compal Secret Data Security Classification 1 4.7U_0603_6.3V6M C1024 1 4.7U_0603_6.3V6M C1023 1 4.7U_0603_6.3V6M C1022 1 4.7U_0603_6.3V6M C1021 1 C1017 1 4.7U_0603_6.3V6M 2 1 4.7U_0603_6.3V6M C1025 2 1 4.7U_0603_6.3V6M C1018 2 1 4.7U_0603_6.3V6M 2 1 4.7U_0603_6.3V6M C1006 2 1 4.7U_0603_6.3V6M C1005 2 1 4.7U_0603_6.3V6M C1004 2 1 4.7U_0603_6.3V6M C1003 2 1 4.7U_0603_6.3V6M C1002 1 4.7U_0603_6.3V6M C1001 2 4.7U_0603_6.3V6M C1000 C998 4.7U_0603_6.3V6M C999 0.1U_0402_16V4Z 0.1U_0402_16V4Z C997 0.1U_0402_16V4Z C996 C995 0.1U_0402_16V4Z 0.1U_0402_16V4Z C994 0.1U_0402_16V4Z C993 0.1U_0402_16V4Z C992 0.1U_0402_16V4Z C991 C988 0.1U_0402_16V4Z C990 2 1 0.1U_0402_16V7K 2 1 C1016 0.1U_0402_16V7K 2 1 C1015 0.1U_0402_16V7K 2 1 C1014 C1014 0.1U_0402_16V7K 2 1 C1013 0.1U_0402_16V7K 0.1U_0402_16V7K 2 1 C1012 0.1U_0402_16V7K 2 1 C1011 1U_0402_6.3V6K DIS@ 2 1 C1010 C1010 1U_0402_6.3V6K DIS@ 2 1 C1009 1U_0402_6.3V6K 1U_0402_6.3V6K A 2 1 C1008 1U_0402_6.3V6K 2 1 C1007 1 1000P_0402_50V7K C989 +1.5VSDGPU 4.7U_0603_6.3V6M C1020 +1.5VSDGPU 4.7U_0603_6.3V6M C1019 +1.5VSDGPU 2 Wednesday, June 30, 2010 Sheet 1 27 of 56
  • 28.
    5 4 3 2 +3VS C475 SG@ 0.1U_0402_16V4Z 1 2 LCD POWERCIRCUIT 1 1 UMOP@ R351 100K_0402_5% P 2 2 SG@ 2 DGPU_EDIDSEL_R# 1 R366 0_0402_5% 18 DGPU_EDIDSEL# 2 C459 29 DGPU_EDIDSEL_R# 0.1U_0402_16V4Z 1 0_0402_5% P PWMSEL_1# SG@ 2 1 R361 0_0402_5% 17 DGPU_PWMSEL# 2 A G R371 100K_0402_5% 1 2 UMOP@ 2 G 3 OE# A IGPU_SELECT# 16 SG@ 2 1 R365 100K_0402_5% 74AHC1G14GW_SOT3535 D Y IGPU_EDIDSEL# 4 U26 @ @ 1 R364 74AHC1G14GW_SOT3535 2 100K_0402_5% Y IGPU_PWM_SELECT# 4 U22 SG@ 74AHC1G14GW_SOT3535 1 5 P 2 16 DPST_PWM C 091211 ADD R371 Fix CPT 4sec shut down flash issue R417 3 S IGPU_SELECT# 4 +3VS C469 SG@ 0.1U_0402_16V4Z 1 2 2 3 DIS ONLY@ R367 100K_0402_5% Q31 2N7002E-T1-GE3_SOT23-3 DIS ONLY@ A 5 D 2 G UMOP@ 1 1 ENVDD 1 G P 1 2 4.7U_0805_10V4Z 1 Y U27 SG@ 3 AO3413L_SOT23-3 +LCDVDD +5VS 22 ENVDD A +3VS C474 @ 0.1U_0402_16V4Z 1 2 SN74CBTD3306CPWR_TSSOP8 SG@ W=60mils C462 S 2N7002E-T1-GE3_SOT23-3 2 INVTPWM 1 D 1 Q30 0.047U_0402_16V7K 2 Q29 2 G 3 PCH_ENVDD 16 PCH_ENVDD 3 C466 UMOP@ D G 8 3 6 4 5 S 3 2N7002E-T1-GE3_SOT23-3 S 2 1 2 G VCC 1B 2B GND G 2 1 Q28 4.7U_0805_10V4Z 1A 2A 1OE# 2OE# 3 2 2 R353 1K_0402_5% 2 1 D 2 5 1 7 DGPU_SELECT# 16,17,29 DGPU_SELECT# U23 INVT_PWM DPST_PWM_1 PWMSEL_1# IGPU_PWM_SELECT# C463 NC 1 +5VS 1 R357 100K_0402_5% 1 1 W=60mils R349 300_0603_5% NC 5 +3VS +3V NC +LCDVDD D 1 Y 4 DPST_PWM_1 U24 UMOP@ 74AHCT1G125GW_SOT353-5 INVT_PWM 36 INVT_PWM UMOP@ 1 R358 C DIS ONLY@ 1 2 R356 22_0402_5% VGA_PNL_PWM 1 @ R360 2 22_0402_5% 1 22 VGA_PNL_PWM INVTPWM 2 22_0402_5% Reserved for UMA Only and OPTIMUS R355 10K_0402_5% SM010014520 3000ma 220ohm@100mhz DCR 0.04 +INVPWR_B+ 1 2 5 +3VS 2 3 Vp Vn USB20_CMOS_N8 2 SWITCHABLE 2009/8/27 ADD SWITCHABLE C470 68P_0402_50V8J USB20_CMOS_P8 4 CH4 CH1 L CM1293-04SO_SOT23-6 @ B W=60mils JLVDS1 41 42 43 44 45 46 A G1 G2 G3 G4 G5 G6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 +3VS @ 2 1 +LCDVDD R679 0_0603_5% 1 +LCDVDD +3VS INVTPWM DISPOFF# I2CC_SCL I2CC_SDA Place closed to JLVDS1 +LCDVDD +INVPWR_B+ +LVDD_R UMA W=60mils 2 1 C464 0.1U_0402_16V4Z 2 1 C461 10U_0805_10V4Z 2 C458 0.1U_0402_16V4Z DAC_BRIG 36 TXOUT0TXOUT0+ INVTPWM DISPOFF# DISPOFF# 2 2 2 @ 0_0402_5% 2 @ PCH_TXCLK+ PCH_TXCLKPCH_TXOUT2PCH_TXOUT2+ PCH_TXOUT1+ PCH_TXOUT1PCH_TXOUT0PCH_TXOUT0+ PCH_LCD_CLK PCH_LCD_DATA 220P_0402_50V7K 220P_0402_50V7K 220P_0402_50V7K 0_0402_5% 2 1 R363 10K_0402_5% 2 0_0402_5% 2 0B1 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 46 45 41 40 35 34 30 29 25 26 0B2 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 DGPU_EDIDSEL_R# 54 SEL2 NC NC NC 57 1 C467 1 C468 1 C473 TXOUT2TXOUT2+ TXCLKTXCLK+ 48 47 43 42 37 36 32 31 22 23 52 5 51 DAC_BRIG TXOUT1TXOUT1+ VGA_TXCLK+ VGA_TXCLKVGA_TXOUT2VGA_TXOUT2+ VGA_TXOUT1+ VGA_TXOUT1VGA_TXOUT0VGA_TXOUT0+ VGA_LCD_CLK VGA_LCD_DATA Thermal_GND 1 R362 1 R368 LOCAL_DIM 36 1 R369 BKOFF# 36 COLOR_ENG_EN 36 TXOUT0+ TXOUT0- +3VS_SWITCH 1 1 1 VCC VCC VCC VCC VCC VCC VCC 4 10 18 27 38 50 56 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 2 3 7 8 11 12 14 15 19 20 SEL 17 1 6 9 13 16 21 24 28 33 39 44 49 53 55 SG@ SG@ SG@ 2 2 2 1109 RF request +3VS R1 R2 1 IPEX_20143-040E-20F CONN@ 2 1 0_0402_5% 1 0_0402_5% 1 C805 22P_0402_50V8J @ 2 2 2 C806 22P_0402_50V8J @ 0_0402_5% 2 UMOP@1 0_0402_5% 2 UMOP@1 R405 R410 PCH_TXOUT1+ PCH_TXOUT1- TXOUT2+ TXOUT2- 0_0402_5% 2 UMOP@1 0_0402_5% 2 UMOP@1 R401 R399 PCH_TXOUT2+ PCH_TXOUT2- TXCLK+ TXCLK- 0_0402_5% 2 UMOP@1 0_0402_5% 2 UMOP@1 R393 R396 PCH_TXCLK+ PCH_TXCLK- 0_0402_5% 2 UMOP@1 0_0402_5% 2 UMOP@1 R418 R420 PCH_LCD_CLK PCH_LCD_DATA +3VS PCH_TXOUT1+ 16 PCH_TXOUT1- 16 PCH_TXOUT2+ 16 PCH_TXOUT2- 16 PCH_LCD_CLK 16 PCH_LCD_DATA 16 1 UMOP@ 2 4.7K_0402_5% PCH_LCD_DATA Discrete ONLY TXOUT0+ TXOUT0- 0_0402_5% 2 DIS ONLY@ R26 1 0_0402_5% 2 DIS ONLY@ R24 1 VGA_TXOUT0+ VGA_TXOUT0- TXOUT1+ TXOUT1- 0_0402_5% 2 DIS ONLY@ R22 1 0_0402_5% 2 DIS ONLY@ R23 1 VGA_TXOUT1+ VGA_TXOUT1- TXOUT2+ TXOUT2- 0_0402_5% 2 DIS ONLY@ R21 1 0_0402_5% 2 DIS ONLY@ R20 1 VGA_TXOUT2+ VGA_TXOUT2- TXCLK+ TXCLK- 0_0402_5% 2 DIS ONLY@ R18 1 0_0402_5% 2 DIS ONLY@ R19 1 VGA_TXCLK+ VGA_TXCLK- I2CC_SCL I2CC_SDA 0_0402_5% 2 DIS ONLY@ R419 VGA_LCD_CLK 1 0_0402_5% 2 DIS ONLY@ R421 VGA_LCD_DATA 1 VGA_TXOUT0+ 23 VGA_TXOUT0- 23 VGA_TXOUT1+ 23 VGA_TXOUT1- 23 VGA_TXOUT2+ 23 VGA_TXOUT2- 23 VGA_TXCLK+ 23 VGA_TXCLK- 23 A VGA_LCD_CLK 22 VGA_LCD_DATA 22 PI3LVD400ZFE with 2 SEL pin USB20_N8 17 USB20_P8 17 2009/08/01 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 4 B PCH_TXCLK+ 16 PCH_TXCLK- 16 1 UMOP@ 2 4.7K_0402_5% PCH_LCD_CLK R32 Date: 5 PCH_TXOUT0+ 16 PCH_TXOUT0- 16 5/4 PCH_LCD_CLK& PCH_LCD_DATA Pull high 2.2K change to 4.7K R29 PI3LVD400ZFEX_TQFN56_11X5 SG@ USB20_CMOS_N8 USB20_CMOS_P8 PCH_TXOUT0+ PCH_TXOUT0- DGPU_SELECT# GND GND GND GND GND GND GND GND GND GND GND GND GND GND R416 R412 I2CC_SCL I2CC_SDA C63 C54 C66 TXCLK+ TXCLKTXOUT2TXOUT2+ TXOUT1+ TXOUT1TXOUT0TXOUT0+ I2CC_SCL I2CC_SDA 0_0402_5% 2 UMOP@1 0_0402_5% 2 UMOP@1 TXOUT1+ TXOUT1- R15 0_0603_5% SG@ U3 TS3DV520ERHUR with 1 SEL pin LCD/LED PANEL Conn. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 B2 UMA ONLY / Optimus +3VS DIS H SEL1 SEL2 1 B1 0.1U_0402_16V4Z 1 CH2 4.7U_0603_6.3V6K L30 2 1 FBMA-L11-201209-221LMA30T_0805 C471 680P_0402_50V7K CH3 1 6 B+ 2 L31 2 1 FBMA-L11-201209-221LMA30T_0805 0.1U_0402_16V4Z W=60mils 2 D1 3 2 Sheet Wednesday, June 30, 2010 1 28 of 56
  • 29.
    A B C D UMA ONLY &OPTIMUS D17 R372 UMOP@ 1 2 D16 +5VS +R_CRT_VCC +CRT_VCC 1 1 1 2 1 1 2 1.1A_6V_SMD1812P110TF 1 C171 0.1U_0402_16V4Z 3 2 3 2 2 W=40mils +3VS 2 1 Change to 0 ohm for CRT EA rising falling time L41 1 1 2 C598 UMOP@ 1 C590 1 UMOP@ 2 2 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J For CRT flicker issue Change C603 C593 C569 Form 12p to 15p 20100617 A OE# P 2 1 L2 2 MBC1608121YZF_0603 2 MBC1608121YZF_0603 C110 3 16 17 C-H_13-12201513CP CONN@ CRT_DET# 18 100P_0402_50V8J CRT_VSYNC_2 1 1 G G CRT_HSYNC_2 C178 10P_0402_50V8J CRT_HSYNC_1 4 1 2 U7 Y 2 1 L1 1 10K_0402_5% 2 2 DSUB_12 2 2 R41 100K_0402_5% @ 1 C164 10P_0402_50V8J DSUB_15 C208 2 68P_0402_50V8J 1 G CRT_HSYNC 1 R67 5 2 0.1U_0402_16V4Z 2 2 C569 1 2 2 C618 UMOP@ CRT_B_2 C593 1 74AHCT1G125GW_SOT353-5 2 1 2 1 C567 +CRT_VCC C194 1 2 FCM2012CF-800T06_2P C603 1 JCRT1 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 CRT_G_2 2 FCM2012CF-800T06_2P L39 1 CRT_B_1 15P_0402_50V8J 1 DIS ONLY@ For CRT flicker issue Change C607 C592 C567 Form 8p to 6p 20100617 2 C592 6P_0402_50V8J DIS ONLY@ 2 2 150_0402_1% 1 DIS ONLY@ C607 150_0402_1% 6P_0402_50V8J R446 6P_0402_50V8J R464 150_0402_1% CRT_G_1 DIS ONLY@ 2 0_0805_5% DIS ONLY@ 1 1 1 1 R377 CRT_R_2 DIS ONLY@ CRT_B 2 FCM2012CF-800T06_2P 15P_0402_50V8J CRT_G L48 1 DIS ONLY@ CRT_R_1 2 0_0805_5% DIS ONLY@ 1 2 R376 0_0805_5% 15P_0402_50V8J 1 R372 DIS ONLY@ CRT_R 2 F1 CH491DPT_SOT23-3 FCM2012CF-800T06_2P R466 D2 C569 1 3 C593 1 2 2 2 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J FCM2012CF-800T06_2P R377 UMOP@ 1 2 1 C603 1 UMOP@ 2 2 2 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J UMOP@ FCM2012CF-800T06_2P R376 UMOP@ 1 2 C567 1 W=40mils D14 BAV99_SOT-23 BAV99_SOT-23 BAV99_SOT-23 UMOP@ C592 1 UMOP@ UMOP@ UMOP@ C607 1 E 2 C126 +CRT_VCC 68P_0402_50V8J +CRT_VCC U5 Y CRT_VSYNC_1 4 D25 BAV99_SOT-23 BAV99_SOT-23 +CRT_VCC +3VS 1 1 3 D33 74AHCT1G125GW_SOT353-5 1 A G 2 1 5 P CRT_VSYNC 1 2 0.1U_0402_16V4Z OE# C111 1 R78 4.7K_0402_5% 2 2 2 3 2 3 G G 2 R48 4.7K_0402_5% +3VS C280 SG@ 0.1U_0402_16V4Z CRT_DDC_CLK 3 DSUB_12 1 Q3 2N7002E-T1-GE3_SOT23-3 DSUB_15 1 3 D 2 2 0.1U_0402_16V4Z 3 S 2 2 0.1U_0402_16V4Z 3 CRT_DDC_DATA +CRT_VCC 1 D 0.1U_0402_16V4Z 1 1 C273 C290 C271 SG@ SG@ SG@ S 1 G 2009/08/27 2 SWITCHABLE Q2 2N7002E-T1-GE3_SOT23-3 20091214 For NV Recommand +3VS U10 4 16 23 29 32 VDD VDD VDD VDD VDD VGA_CRT_R VGA_CRT_G VGA_CRT_B VGA_CRT_HSYNC VGA_CRT_VSYNC VGA_DDC_CLK VGA_DDC_DATA 27 25 22 20 18 12 14 0B1 1B1 2B1 3B1 4B1 5B1 6B1 PCH_CRT_R PCH_CRT_G PCH_CRT_B PCH_CRT_HSYNC PCH_CRT_VSYNC PCH_CRT_CLK PCH_CRT_DATA 26 24 21 19 17 13 15 0B2 1B2 2B2 3B2 4B2 5B2 6B2 4 A0 A1 A2 A3 A4 1 2 5 6 7 SEL1 8 A5 A6 9 10 SEL2 30 CRT_R CRT_G CRT_B CRT_HSYNC CRT_VSYNC DGPU_SELECT# 16,17,28 22 VGA_CRT_R 22 VGA_CRT_G CRT_DDC_CLK CRT_DDC_DATA 22 VGA_CRT_B DGPU_EDIDSEL_R# 28 22 VGA_CRT_HSYNC 22 VGA_CRT_VSYNC GND GND GND GND GPAD 22 VGA_DDC_CLK 3 11 28 31 33 22 VGA_DDC_DATA B1 B2 R537 2 DIS ONLY@ 1 0_0402_5% CRT_R VGA_CRT_G R535 2 DIS ONLY@ 1 0_0402_5% CRT_G VGA_CRT_B R533 2 DIS ONLY@ 1 0_0402_5% CRT_B VGA_CRT_HSYNC R531 2 DIS ONLY@ 1 0_0402_5% CRT_HSYNC VGA_CRT_VSYNC R529 2 DIS ONLY@ 1 0_0402_5% CRT_VSYNC VGA_DDC_CLK R527 2 DIS ONLY@ 1 0_0402_5% CRT_DDC_CLK VGA_DDC_DATA R526 2 DIS ONLY@ 1 0_0402_5% CRT_DDC_DATA 16 PCH_CRT_R 16 PCH_CRT_G 16 PCH_CRT_B 16 PCH_CRT_HSYNC 16 PCH_CRT_VSYNC 16 PCH_CRT_CLK 16 PCH_CRT_DATA PCH_CRT_R R536 2 UMOP@ 1 0_0402_5% CRT_R PCH_CRT_G R534 2 UMOP@ 1 0_0402_5% CRT_G PCH_CRT_B R532 2 UMOP@ 1 0_0402_5% PCH_CRT_HSYNC R530 2 UMOP@ 1 0_0402_5% CRT_HSYNC PCH_CRT_VSYNC R528 2 UMOP@ 1 0_0402_5% CRT_VSYNC PCH_CRT_CLK R544 2 UMOP@ 1 0_0402_5% PCH_CRT_DATA R543 2 UMOP@ 1 0_0402_5% UMA CRT_DDC_CLK CRT_DDC_DATA 4 2009/08/01 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A CRT_B PCH DDC PU 2.2K on Page 17 DIS H VGA_CRT_R VGA_DDC_DATA and VGA_DDC_CLK Pull high at Page22 PI3V712-AZLEX_TQFN32_6X3~D SG@ L UMA only & Optimus Discrete only B C D SCHEMATICS,MB A5893 Document Number Rev C 401869 Sheet Wednesday, June 30, 2010 E 29 of 56
  • 30.
    5 4 3 2 1 +3VS +3VS C725 C730 C731 1 C720 1 C721 C409 2 0_0603_5% UMOP@ UMOP@ 2 UMOP@ 2 0.1U_0402_16V4Z 2 UMOP@ 2 0.1U_0402_16V4Z UMOP@ R616 10K_0402_5% UMOP@ W=40mils 1 +HDMI_5V_OUT D21 UMOP@ UMOP@ 2 2 0.1U_0402_16V4Z HDMI connector 1 0.1U_0402_16V4Z 1 +5VS 2 2 F2 1+HDMI_5V 1 @ CH491DPT_SOT23-3 OE# 2 1.1A_6V_SMD1812P110TF C707 0.1U_0402_16V4Z D 1 Q43 UMOP@ HDMI_HPD 2 G 3 S 100K_0402_5% 2 HDMI_R_D0+ HDMI_R_D1- SCL_SINK 28 HDMI_SCLK R625 1 D23 2 2.2K_0402_5% 1 SDA_SINK VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V CG_0 CG_1 3 4 29 HDMI_SDATA R627 1 2 2.2K_0402_5% 1 REXT 6 2 0_0402_5% D24 HPD_SINK 32 EQ_0 EQ_1 HDMI_R_D1+ HDMI_R_D2- CH751H-40PT_SOD323-2 2 +HDMI_5V_OUT HDMI_R_D2+ 2 34 35 R629 1 UMOP@ 2 2.2K_0402_5% +3VS R637 2.2K_0402_5% 1 UMOP@ 2 R638 2.2K_0402_5% 1 UMOP@ 2 EQ_S0 R635 @ 1 2 2.2K_0402_5% EQ_S1 R666 @ 1 2 2.2K_0402_5% 2 3.3K_0402_5% 1 2 2.2K_0402_5% R219 UMOP@ 1 +3VS R223 UMOP@ 16 SDVO_SDATA 2 2.2K_0402_5% REXT 16 SDVO_SCLK R211 1 @ R209 UMOP@ 1 +3VS CG0 CG1 CG2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 +3VS R228 1 0 0 0 0 0 2db 2db 0 @ 0 -3db -3db (default) -4db 0 0 0 0 R234 @ 1 SDA SDVO_SCLK 9 SCL CG_2 SM070001310 400ma 90ohm@100mhz DCR 0.3 EQ0 EQ1 0 0 1 1 0 1 0 1 Equalization 12dB 9dB 6dB 3dB (default) OUT_D4+ OUT_D4- IN_D4+ IN_D4- 48 47 PCH_TMDS_D2 16 PCH_TMDS_D2# 16 HDMI_TX1+ HDMI_TX1- 16 17 OUT_D3+ OUT_D3- IN_D3+ IN_D3- 45 44 PCH_TMDS_D1 16 PCH_TMDS_D1# 16 HDMI_CLK+ HDMI_CLK- 19 20 OUT_D2+ OUT_D2- IN_D2+ IN_D2- 42 41 PCH_TMDS_CK 16 PCH_TMDS_CK# 16 HDMI_TX0+ HDMI_TX0- 22 23 OUT_D1+ OUT_D1- IN_D1+ IN_D1- 39 38 PCH_TMDS_D0 16 PCH_TMDS_D0# 16 1 5 12 18 24 27 31 36 37 43 GND GND GND GND GND GND GND GND GND GND GND 49 2 10K_0402_5% 2 4 3 @ ASM1442T_QFN48_7X7 R174 1 2 1 L23 WCM-2012-900T_0805 @ 4 23 VGA_HDMI_TXD023 VGA_HDMI_TXD0+ 23 VGA_HDMI_TXC23 VGA_HDMI_TXC+ 3 R183 1 2 1 1 L25 WCM-2012-900T_0805 @ 4 HDMI_TX2+ R190 HDMI_R_D1+ 2 3 HDMI_R_D1- 0_0402_5% 2 HDMI_R_D2+ 2 4 2 3 1 R188 1 HDMI_R_D0- 0_0402_5% 2 1 1 L26 WCM-2012-900T_0805 @ 4 3 0_0402_5% 3 1 HDMI_R_D0+ 2 0_0402_5% 2 4 R182 HDMI_R_CK- 0_0402_5% 2 HDMI_TX1+ C 3 3 2 B 0_0402_5% HDMI_R_D2- C379 C378 DIS ONLY@ 2 DIS ONLY@ 2 1 0.1U_0402_16V7K HDMI_TX2- R613 1 DIS ONLY@590_0402_1% 2 1 0.1U_0402_16V7K HDMI_TX2+ R614 1 DIS ONLY@590_0402_1% 2 C381 C380 DIS ONLY@ 2 DIS ONLY@ 2 1 0.1U_0402_16V7K HDMI_TX1- R611 1 DIS ONLY@590_0402_1% 2 1 0.1U_0402_16V7K HDMI_TX1+ R612 1 DIS ONLY@590_0402_1% 2 C385 C384 DIS ONLY@ 2 DIS ONLY@ 2 1 0.1U_0402_16V7K HDMI_TX0- R607 1 DIS ONLY@590_0402_1% 2 1 0.1U_0402_16V7K HDMI_TX0+ R608 1 DIS ONLY@590_0402_1% 2 C383 C382 DIS ONLY@ 2 DIS ONLY@ 2 1 0.1U_0402_16V7K HDMI_CLK- R609 1 DIS ONLY@590_0402_1% 2 1 0.1U_0402_16V7K HDMI_CLK+ R610 1 DIS ONLY@590_0402_1% 2 1 S S D HDMI_SDATA Q13 DIS ONLY@ 2N7002E-T1-GE3_SOT23-3 Place closed to JHDMI1 1 C803 12P_0402_50V8J 2 @ 1 1 Q42 DIS ONLY@ S 100K_0402_5% 2N7002E-T1-GE3_SOT23-3 2009/08/01 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 A Compal Electronics, Inc. Compal Secret Data Security Classification DDC to HDMI CONN R370 S D C804 12P_0402_50V8J 2 @ D 2 G 3 1 2 2 Q12 3 23 VGA_HDMI_SDATA D G A @ 1 22 VGA_HDMI_DET 1 S 23 VGA_HDMI_SCLK +3VSDGPU 2 G 2 1109 RF request HDMI_SCLK DIS ONLY@ 2N7002E-T1-GE3_SOT23-3 3 C Q52 HDMI_HPD 2 1 DIS ONLY@ 2 B R634 150K_0402_5% MMBT3904_G_SOT23-3 DIS ONLY@ E 1 2 R714 1 3 18 DGPU_HPD_INT# 0_0402_5% DIS ONLY@ R715 Q44 10K_0402_5% 2N7002E-T1-GE3_SOT23-3 DIS ONLY@ SG@ 2 G Pull high at VGA side 3 1 +3VSDGPU 4 HDMI_R_CK+ 2 0_0402_5% 2 R168 1 HDMI_TX2- 23 VGA_HDMI_TXD123 VGA_HDMI_TXD1+ 1 HDMI_TX0- UMOP@ 23 VGA_HDMI_TXD223 VGA_HDMI_TXD2+ +3VSDGPU 2 HDMI_TX1- 20091216 For ASMEDIA AOC Panel Bug ASM1442 PN: SA00003GT00 R177 1 HDMI_TX0+ CG_2 13 14 0_0402_5% 2 1 HDMI_CLK- HDMI_TX2+ HDMI_TX2- HPD_SOURCE R180 1 1 L24 WCM-2012-900T_0805 @ 4 10 2 10K_0402_5% 1 UMOP@ 2 R230 0_0402_5% 16 PCH_DPB_HPD HPD# 8 2 2.2K_0402_5% 2 2.2K_0402_5% Swing Pre-amp Slew-rate 450 420 450 460 340 400 400 420 7 SDVO_SDATA D 20 21 22 23 +3VS 2.2K_0402_5% 1 2 R718 UMOP@ 1 2.2K_0402_5% 1 2 R719 R235 UMOP@ HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ SUYIN_100042MR019S153ZL CONN@ CH751H-40PT_SOD323-2 HDMI_HPD 30 CG_0 CG_1 HPD_SOURCE B @ 1 R618 OE# HDMI_CLK+ Connection to 3.4K external resistor. C HDMI_R_CK+ HDMI_R_D0- 25 DDC_EN 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% HDMI_R_CK- 0.1U_0402_16V4Z OE# 2 11 15 21 26 33 40 46 @ 1 2 1 @ 2 1 UMOP@ 2 1 UMOP@ 2 C410 2 U45 R269 R253 R273 R252 1 R256 2N7002E-T1-GE3_SOT23-3 +3VS 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HDMI_SDATA HDMI_SCLK D 0.1U_0402_16V4Z 2 +3VS JHDMI1 HDMI_HPD +HDMI_5V_OUT 1 C727 1 2 0.1U_0402_16V4Z R590 1 1 1 0.1U_0402_16V4Z 1 3 2 Wednesday, June 30, 2010 Sheet 1 30 of 56
  • 31.
    5 4 3 2 1 D D SATA HDD1 Conn. CL4.0 mm JHDD1 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 C753 1 C751 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K 13 SATA_DTX_C_PRX_N0 13 SATA_DTX_C_PRX_P0 SATA_DTX_C_PRX_N0 SATA_DTX_C_PRX_P0 C749 1 C747 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K 1 2 3 4 5 6 7 SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0 SATA_DTX_PRX_N0 SATA_DTX_PRX_P0 13 SATA_PTX_DRX_P0 13 SATA_PTX_DRX_N0 +3VS 1 2 +5VS R669 1 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 +3VS C745 0.1U_0402_16V4Z 2 0_0805_5% +5VS_HDD1 100mils 10U_0805_10V4Z C735 1 0.1U_0402_16V4Z 1 C734 1 C733 1 C732 C 2 2 2 GND A+ AGND BB+ GND V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12 24 23 GND GND C 2 1U_0402_6.3V4Z SANTA_192301-1 CONN@ 1000P_0402_50V7K SATA ODD Conn. JODD1 B SATA_PTX_C_DRX_P1 SATA_PTX_C_DRX_N1 C680 1 C678 1 13 SATA_DTX_C_PRX_N1 13 SATA_DTX_C_PRX_P1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_DTX_PRX_N1 SATA_DTX_PRX_P1 R516 1 +5VS R105 1 @ 2 1K_0402_1% +5VS_ODD 2 0_0805_5% 80mils 10U_0805_10V4Z C642 Place caps. near ODD CONN. 1 2 1 2 3 4 5 6 7 GND A+ AGND BB+ GND 8 9 10 11 12 13 C687 1 C685 1 13 SATA_PTX_DRX_P1 13 SATA_PTX_DRX_N1 DP +5V +5V MD GND GND B GND GND GND GND 17 16 15 14 0.1U_0402_16V4Z C654 1 C653 2 1 C643 2 1U_0402_6.3V4Z OCTEK_SLS-13SB1G_RV CONN@ 1 2 1000P_0402_50V7K A A 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Sheet Wednesday, June 30, 2010 1 31 of 56
  • 32.
    5 4 3 2 1 +3V_LAN +3VALW R599 1 2 60mil 0_1206_5% 1 D BIASVDDH VDDC VDDC VDDC XTALVDDH 14 2 6 15 41 AVDDH 30 AVDDH D +LAN_BIASVDDH 36 1 AVDDL AVDDL AVDDL +LAN_AVDDH SPROM_CLK (EECLK) 38 LAN_MIDI3+ TRD2_N 35 LAN_MIDI2- TRD2_P 34 LAN_MIDI2+ TRD1_N 31 LAN_MIDI1- TRD1_P 32 LAN_MIDI1+ TRD0_N 29 LAN_MIDI0- TRD0_P 24 37 TRD3_P +LAN_GPHYPLLVDDL TRD3_N LAN_MIDI3- 28 LAN_MIDI0+ LAN_MIDI3+ 33 LAN_MIDI2- 33 1 0 AT24C02 LAN_MIDI3-33 SPROM_DOUT (EEDATA) On chip 1 1 +3V_LAN LAN_MIDI2+ 33 C322 1 GPHY_PLLVDDL +LAN_PCIEPLLVDD 18 PCIE_PLLVDDL 21 PCIE_PLLVDDL LAN_MIDI1- 33 R195 1K_0402_1% @ LAN_MIDI1+ 33 LAN_MIDI0- 33 LAN_MIDI0+ 33 2 0.1U_0402_16V7K 14 PCIE_PTX_C_DRX_P1 14 PCIE_PTX_C_DRX_N1 R592 1 R589 1 R587 1 15,34 PCH_PCIE_WAKE# 36 EC_PME# +3V_LAN @ R597 1 5,17,21,36 PLT_RST# 17 16 22 23 LAN_PME# 4 LAN_RESET# 2 20 19 2 0_0402_5% 2 0_0402_5% 2 4.7K_0402_5% 48 SPD100LED# 47 SPD1000LED# 46 TRAFFICLED# PCIE_TXD_P PCIE_TXD_N PCIE_RXD_P PCIE_RXD_N WAKE# REST# PCIE_REFCLK_P PCIE_REFCLK_N 45 2 R595 0_0402_5% 1 2 R594 0_0402_5% 1 LAN_LINK# 33 VCC WP SCL SDA A0 A1 NC GND 1 2 3 4 C AT24C02_SO8 R196 1K_0402_1% R194 1K_0402_1% @ 1 PCIE_DTX_PRX_P1 PCIE_DTX_PRX_N1 U12 @ 8 7 6 5 1 LINKLED# 0.1U_0402_16V7K 1 2 C699 1 2 C700 14 PCIE_DTX_C_PRX_P1 14 PCIE_DTX_C_PRX_N1 R193 1K_0402_1% SPROM_CLK SPROM_DOUT C 2 0.1U_0402_16V4Z @ 2 +LAN_AVDDL 27 33 39 +LAN_XTALVDDH 1 C493 2 1 VDDC 25 2 2 C492 42 1 2 2 +3V_LAN 1000P_0402_50V7K 2 1 C705 1000P_0402_50V7K 1 C701 C333 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 1 C697 0.1U_0402_16V4Z 4.7U_0603_6.3V6K 091211 EMI add 1000P C715 4.7U_0603_6.3V6K 2 2 0.1U_0402_16V4Z U39 +1.2V_LAN 1 C716 LAN_ACTIVITY# 33 SM010005500 500ma 600ohm@100mhz DCR 0.38 20mil L22 +LAN_XTALVDDH C301 1 2 BLM18AG601SN1D_2P 1 +3V_LAN 0.1U_0402_16V4Z 2 0_0402_5% MODE 20mil 5 2 L64 +LAN_BIASVDDH 14 CLK_PCIE_LAN 14 CLK_PCIE_LAN# C703 1 2 BLM18AG601SN1D_2P 1 0.1U_0402_16V4Z EEDATA R175 1 2 1K_0402_5% 40 R596 1 +3VS 2 10K_0402_5% 1 43 44 20mil SPROM_DOUT EECLK SPROM_CLK L66 VMAIN_PRSINT C712 LOW_PWR 40mil B SR_LX LAN_XTALO_R 13 XTALO LAN_XTALI 12 11 SR_VFB 0.1U_0402_16V4Z L65 +1.2V_LAN_OUT 1 2 4.7UH_PG031B-4R7MS_1.1A_20% XTALI 8 1 LAN_RDAC 26 SR_VDDP 2 C710 10U_0805_10V4Z SR_VDD 14 LAN_CLKREQ# 3 10 9 C318 1 2 2 +1.2V_LAN C695 4.7U_0603_6.3V6K L62 1 2 BLM18AG601SN1D_2P +LAN_GPHYPLLVDDL 7 C698 0.1U_0402_16V4Z 1 1 2 2 1 1 2 2 +1.2V_LAN C696 4.7U_0603_6.3V6K 49 BCM57780A0KMLG_QFN48_7X7 1 20mil PAD NC 1 C311 2 2 4.7U_0603_6.3V6K 0.1U_0402_16V4Z CLKREQ# 0.1U_0402_16V4Z L63 1 2 BLM18AG601SN1D_2P +LAN_PCIEPLLVDD +3V_LAN 1 2 B 0.1U_0402_16V4Z RDAC 2 1 2 BLM18AG601SN1D_2P SM010005500 500ma 600ohm@100mhz DCR 0.38 C302 2 C706 1 20mil 1 2 C708 0.1U_0402_16V4Z 1.24K_0402_1% 1 +1.2V_LAN R575 1 2 +LAN_AVDDH 20mil L21 1 2 BLM18AG601SN1D_2P +LAN_AVDDL LAN_XTALI C709 LAN_XTALO_R 0.1U_0402_16V4Z 4.7U_0603_6.3V6K A 1 A +1.2V_LAN C312 2 R571 200_0402_1% Y3 1 1 2 2 LAN_XTALO 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 1 25MHZ_20PF_7A25000012 C704 C702 27P_0402_50V8J 27P_0402_50V8J 2 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 Rev C 401869 4 3 2 Sheet Wednesday, June 30, 2010 1 32 of 56
  • 33.
    5 4 3 2 1 LAN Connector D D T16 TCT1 TD1+ TD1- MCT1 MX1+ MX1- 24 23 22 RJ45_MIDI0+ RJ45_MIDI0- 32 LAN_MIDI1+ 32LAN_MIDI1- LAN_MIDI1+ LAN_MIDI1- 4 5 6 TCT2 TD2+ TD2- MCT2 MX2+ MX2- 21 20 19 RJ45_MIDI1+ RJ45_MIDI1- 32 LAN_MIDI2+ 32 LAN_MIDI2- LAN_MIDI2+ LAN_MIDI2- 7 8 9 TCT3 TD3+ TD3- MCT3 MX3+ MX3- 18 17 16 RJ45_MIDI2+ RJ45_MIDI2- 32 LAN_MIDI3+ 32 LAN_MIDI3- LAN_MIDI3+ LAN_MIDI3- 10 11 12 TCT4 TD4+ TD4- MCT4 MX4+ MX4- 15 14 13 RJ45_MIDI3+ RJ45_MIDI3- 2 R518 +3V_LAN 1 1K_0402_5% 220P_0402_50V7K C663 LAN_ACTIVITY# LAN_LINK# 1 2 C656 68P_0402_50V8J @ 2 1 JRJ45 Green LED+ Green LED- 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z +3V_LAN 2 R140 40mil 1 1K_0402_5% PR3+ 5 PR3- 6 PR2- 7 PR4+ 8 PR4- C Yellow LED+ 12 LAN_ACTIVITY# 32 LAN_ACTIVITY# Yellow LED- 68P_0402_50V8J 2 2 @ 14 13 SHLD1 SHLD2 11 1 220P_0402_50V7K C297 BOTHHAND: S X'FORM_ GST5009-D LF LAN, SP050006B00 TIMAG:S X'FORM_ IH-160 LAN , SP050006F00 PR2+ 4 RJ45_MIDI3RJ45_GND Place close to TCT pin 3 RJ45_MIDI3+ R522 75_0402_1% PR1- RJ45_MIDI1- 1 1 R525 75_0402_1% 2 RJ45_MIDI2- 1 C690 R541 75_0402_1% 2 0.1U_0402_16V4Z R549 75_0402_1% 1 0.1U_0402_16V4Z 2 2 C686 1 1 C681 1 PR1+ RJ45_MIDI0- 2 2 C671 1 1 RJ45_MIDI1+ 2 1 2 C RJ45_MIDI0+ RJ45_MIDI2+ 350UH_IH-037-2 D22 PJDLC05C_SOT23-3 @ 9 10 LAN_LINK# 32 LAN_LINK# 2 LAN_MIDI0+ LAN_MIDI0- 3 32 LAN_MIDI0+ 32 LAN_MIDI0- 1 2 3 SANTA_130451-K CONN@ 1 C292 RJ45_GND 1 LANGND 1 2 C661 1000P_1206_2KV7K 1 C660 2 2 40mil C659 4.7U_0603_6.3V6K 0.1U_0402_16V4Z B B A A Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 33 of 56
  • 34.
    A 2 R302 +3VS B 1 0_1206_5% C D E For Wireless LAN +3VS_WLAN 60mil +3VS_WLAN 1 2 1 +1.5VS 1 C440 4.7U_0805_10V4Z 2 1 C423 0.1U_0402_16V4Z 2 +3VS_WLAN 1 C452 4.7U_0805_10V4Z 2 1 C441 0.1U_0402_16V4Z 2 1 C434 0.1U_0402_16V4Z 2 C442 MiniCard Power Rating 0.1U_0402_16V4Z Power Primary Power (mA) Auxiliary Power (mA) Peak +3VS @ 2 0_0402_5% (WLAN_BT_DATA) (WLAN_BT_CLK) 14 CLK_PCIE_MINI1# 14 CLK_PCIE_MINI1 14 PCIE_DTX_C_PRX_N2 14 PCIE_DTX_C_PRX_P2 14 PCIE_PTX_C_DRX_N2 14 PCIE_PTX_C_DRX_P2 +3VS_WLAN 2 R280 1 E51TXD_P80DATA1_R E51RXD_P80CLK 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 18 20 22 24 26 28 30 32 34 36 38 40 42 (WWAN_LED#) 44 (WLAN_LED#) 46 48 50 52 +1.5VS WL_OFF# PLT_RST_BUF# R303 1 R299 1 @ 750 330 250 250 (wake enable) +1.5VS +3VS_WLAN 500 375 1 5 (Not wake enable) Normal WL_OFF# 36 PLT_RST_BUF# 17 +3VS +3V 2 0_0603_5% 2 0_0603_5% 0_0402_5% MINI1_SMBCLK R292 1 @ 2 @ MINI1_SMBDATA 1 2 R288 0_0402_5% PCH_SMBCLK 12,14,21 PCH_SMBDATA 12,14,21 USB20_N12 17 USB20_P12 17 R291 1 2 0_0402_5% MINI1_LED# 36 2 (9~16mA) R285 100K_0402_5% 53 54 55 56 2 G1 G2 G3 G3 36 E51TXD_P80DATA 36 E51RXD_P80CLK 0_0402_5% 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 14 MINI1_CLKREQ# 1 3 5 7 9 11 13 15 1 R323 1 1000 +3V JMINI1 PCH_PCIE_WAKE# 15,32 PCH_PCIE_WAKE# Normal ACES_88910-5204 CONN@ 4 mm High +3VS_WLAN +3VS_WWAN 1 2 C460 3G@ 0.1U_0402_16V4Z For 3G / GPS +3VS_WWAN To 3G Module Connect (Port 9) +3VS_WWAN Peak: 2.75A Normal: 1.1A 1 3G@ R352 1 2 3 4 5 6 7 8 9 10 GND GND 2 0_1206_5% 1 C465 @ 150U_B2_6.3VM_R35M 1 + 2 1 C801 3G@ 2 2 C173 3G@ 10U_0603_6.3V6M 47P_0402_50V8J Close to WWAN CONN +3VS_WWAN R350 100K_0402_5% JP4 1 2 3 4 5 6 7 8 9 10 11 12 1 +3VS 3 LS-5895 2 3 WWAN_OFF# WWAN_OFF# 36 WWAN_LED# 36 USB20_N13 17 USB20_P13 17 USB20_N10 17 USB20_P10 17 ACES_87036-1001-CP CONN@ 1109 RF request 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: A B C D Wednesday, June 30, 2010 Sheet E 34 of 56
  • 35.
    A B C D E +3V +5VALW +USB_VCCB U46 U17 C424 1 R250 100K_0402_5% 8 7 6 5 GND VOUT VIN VOUT VINVOUT EN FLG 2 1 2 3 4 1 2 R251 10K_0402_5% RT9715BGS_SO8 4.7U_0805_10V4Z 2 1 1 2 3 4 C736 USB_OC#2 17 1 2 1 GND VOUT VIN VOUT VIN VOUT EN FLG 8 7 6 5 R681 100K_0402_5% 2 +USB_VCCA 1 +5VALW 1 +3V 1 2 R680 10K_0402_5% RT9715BGS_SO8 USB_OC#0 17 1 4.7U_0805_10V4Z 2 C408 2 0.1U_0402_16V4Z C744 1 0.1U_0402_16V4Z SYSON# SYSON# 42 SYSON# 2009/08/14 CHANGE cap D26 6 CH3 CH2 3 USB20_N1_1 +USB_VCCA W=100mils USB/B Conn. LS-5891 +USB_VCCA (Port 0,2) 1 5 +USB_VCCA Vp Vn 2 1 + C726 2 220U_6.3V_M_R17 USB20_P1_1 4 CH4 CH1 1 C728 2009/08/25 Update Footprint(follow NAL00) 2 470P_0402_50V7K CM1293-04SO_SOT23-6 R667 1 2 0_0402_5% 1 2 3 4 5 6 7 8 9 10 11 12 USB Conn. (Port 1) JUSB1 USB20_N1 17 USB20_N1 L68 1 1 2 2 USB20_N1_1 USB20_P1_1 2 USB20_P1 17 USB20_P1 4 4 3 3 @ WCM-2012-900T_0805 1 2 R668 0_0402_5% 1 2 3 4 5 6 7 8 +USB_VCCB JUSB2 VBUS DD+ GND GND GND GND GND 13 14 GND GND W=100mils 1 2 3 4 5 6 7 8 9 10 11 12 USB20_N0 USB20_P0 USB20_N2 USB20_P2 USB20_N0 17 USB20_P0 17 USB20_N2 17 USB20_P2 17 2 ACES_85201-1205N CONN@ SUYIN_020133GB004M51PZR CONN@ 3 3 36 BT_ON# +3VS GND GND 8 7 6 5 4 3 2 1 C445 4.7U_0805_10V4Z 1 2 10 9 8 7 6 5 4 3 2 1 BT_ON# 5IN1_LED# 37 USB20_N9 USB20_P9 1 1 BT@ 2 R706 10K_0402_5% C788 BT@ 0.1U_0402_16V4Z 1 S 2 G D 2 (Port 11) 10 2 Q51 BT@ AO3413L_SOT23-3 W=40mils +BT_VCC 1 C796 BT@ 4.7U_0805_10V4Z USB20_N9 17 USB20_P9 17 BT Conn. C790 BT@ 1U_0603_10V4Z 1 LS-5896 2 3 C789 BT@ 0.1U_0402_16V4Z +3VS 1 Card Reader Conn. +3VALW 1 C795 BT@ R713 300_0603_5% BT@ 2 0.1U_0402_16V4Z 1 S 2 G 4 2008/08/10 Issued Date Deciphered Date 8 7 6 5 4 3 2 1 USB20_P11 17 USB20_N11 17 (WLAN_BT_DATA) (WLAN_BT_CLK) ACES_87213-0800G CONN@ BT Wire Cable Note: Pin 3, Pin 4 NC Q50 2N7002E-T1-GE3_SOT23-3 BT@ 4 Compal Electronics, Inc. Compal Secret Data Security Classification GND 8 7 6 5 4 3 2 GND 1 D 3 JCR1 ACES_85201-08051 CONN@ 9 +BT_VCC JBT1 2 2009/08/24 CHANGE Conn to FFC Type 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: A B C D Wednesday, June 30, 2010 Sheet E 35 of 56
  • 36.
    4 3 2 1 SM010015410 300ma 80ohm@100mhzDCR 0.3 PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D 18 EC_SCI# 15 PM_CLKRUN# +3VALW C 1 R392 1 R395 1 R422 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 77 78 79 80 SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 PM_SLP_S3# PM_SLP_S5# EC_SMI# EC_ACIN MINI1_LED# LOCAL_DIM COLOR_ENG_EN INVT_PWM FAN_SPEED1 BT_ON# E51TXD_P80DATA E51RXD_P80CLK ON/OFF PWR_SUSP_LED WLAN_LED# 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 2 LID_SW# 100K_0402_5% 1 R374 1 R373 2 KSO1 47K_0402_5% 2 KSO2 47K_0402_5% 1 R426 @ 2 EC_PME# 10K_0402_5% 44 44 14,22 14,22 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 R400 2 R402 1 2 100K_0402_5% EC_SMB_CK2 1 2.2K_0402_5% EC_SMB_DA2 1 2.2K_0402_5% 38 ON/OFF 37 PWR_SUSP_LED 37 WLAN_LED# 2 GFX_CORE_PWRGD 10K_0402_5% 1 E51TXD_P80DATA R508 15 SUSCLK @ 1 R740 2 0_0402_5% EC_CRY1 EC_CRY2 1 R509 2 100K_0402_5% 1 COLOR_ENG_EN R511 PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F 83 84 85 86 87 88 EC_MUTE# GFX_CORE_PWRGD WWAN_LED# VGA_idle TP_CLK TP_DATA 122 123 DAC_BRIG 28 EN_DFAN1 41 IREF 46 CALIBRATE# 46 EC_MUTE# 40 GFX_CORE_PWRGD 52 WWAN_LED# 34 VGA_idle 22 TP_CLK 37 TP_DATA 37 3S/4S# 65W/90W# SBPWR_EN LID_SW# SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS# 119 120 126 128 EC_SI_SPI_SO EC_SO_SPI_SI EC_SPICLK EC_SPICS#/FSEL# CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 73 74 89 90 91 92 93 95 121 127 WWAN_OFF# PCH_TEMP_ALERT# FSTCHG BATT_GRN_LED# 3G_LED# BATT_AMB_LED# PWR_LED SYSON VR_ON ACIN EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 100 101 102 103 104 105 106 107 108 EC_RSMRST# EC_LID_OUT# EC_ON EC_SWI# EC_PWROK BKOFF# WL_OFF# PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 110 112 114 115 116 117 118 V18R 124 SPI Flash ROM 2 R404 TP_DATA 2 R408 65W/90W# C496 VGA_idle GPIO SM Bus GPI 2 R423 2 R424 2 R428 DIS@ EC_SI_SPI_SO 37 EC_SO_SPI_SI 37 EC_SPICLK 37 EC_SPICS#/FSEL# 37 C +3VALW 1 100K_0402_5% 1 100K_0402_5% 1 100K_0402_5% +3VALW WWAN_OFF# 34 PCH_TEMP_ALERT# 18,21 FSTCHG 46 (CAPS_LED#) BATT_GRN_LED# 37 3G_LED# 37 BATT_AMB_LED# 37 PWR_LED 37 SYSON 42,49 VR_ON 38,53 ACIN 37,42,43 EC_RSMRST# 15 EC_LID_OUT# 14 EC_ON 38 EC_SWI# 15 EC_PWROK 15,38 BKOFF# 28 WL_OFF# 34 R394 100K_0402_5% Ra EC_PROJECTID 2 C511 0.1U_0402_16V4Z @ B Project ID definition, Please see page 3. EC_CRY1 PM_SLP_S4# 15 ENBKL 16 EAPD 39 SUS_PWR_DN_ACK SUSP# 38,42,46,48 PBTN_OUT# 5,15,21 EC_PME# 32 ENBKL EAPD SUS_PWR_DN_ACK SUSP# PBTN_OUT# EC_PME# 1 R397 0_0402_5% Rb C536 KB926QFD3_LQFP128_14X14 1 4.7K_0402_5% 1 4.7K_0402_5% PCH_TEMP_ALERT# Pull high at Page 18 (PCH side) @ For Low PWR Pannel use 15P_0402_50V8J EC_CRY2 1 1 2 X1 15 2 C537 15P_0402_50V8J 32.768KHZ_12.5PF_Q13MC14610002 1 2 C539 C490 BATT_TEMP 2 C489 BATT_OVP 2 C534 ACIN 2 4.7U_0805_10V4Z 20mil L33 ECAGND 2 1 FBMA-L11-160808-800LMT_0603 ENBKL 1 R425 2 100K_0402_5% 100P_0402_50V8J 1 100P_0402_50V8J 1 100P_0402_50V8J 1 A SM010015410 300ma 80ohm@100mhz DCR 0.3 Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Issued Date Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 1 2 0.1U_0402_16V4Z TP_CLK 3S/4S# 46 65W/90W# 46 SBPWR_EN 42 LID_SW# 37 SPI Device Interface XCLK1 XCLK0 <BOM Structure> AD_BID0 R382 33K_0402_1% Rb 97 98 99 109 SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0 PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A LOCAL_DIM 2 100K_0402_5% A (NUM_LED#) DAC_BRIG EN_DFAN1 IREF CALIBRATE# R389 100K_0402_5% Ra BATT_TEMP 44 BATT_OVP 46 ADP_I 46 3S/4S# GND GND GND GND GND R398 2 DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F 68 70 71 72 PS2 Interface 11 24 35 94 113 +3VS BATT_TEMP BATT_OVP ADP_I AD_BID0 EC_PROJECTID +5VS B 15 PM_SLP_S3# 15 PM_SLP_S5# 18 EC_SMI# 15 EC_ACIN 34 MINI1_LED# 28 LOCAL_DIM 28 COLOR_ENG_EN 28 INVT_PWM 41 FAN_SPEED1 35 BT_ON# 63 64 65 66 75 76 DA Output KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 2 EC_SMB_CK1 2.2K_0402_5% 2 EC_SMB_DA1 2.2K_0402_5% BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 Board ID definition, Please see page 3. 4 0.1U_0402_16V4Z ACOFF 1 1 AD +3VALW BEEP# 39 ME_OVERRIDE 13 ACOFF 46,47 ECAGND 2 1 C491 0.01U_0402_16V7K OSC 12 13 37 20 38 PWM Output ACES_85205-0400 @ BEEP# OSC 2 5,17,21,32 PLT_RST# 21 23 26 27 NC C487 1 47K_0402_5% INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 4 D E51RXD_P80CLK E51TXD_P80DATA NC R375 2 1 2 3 4 3 EC_RST# EC_SCI# 17 CLK_PCI_LPC +3VALW Place on MiniCard +3VALW 1 2 3 4 2 1 47_0402_5% GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC E51RXD_P80CLK 34 E51TXD_P80DATA 34 JP5 AGND R403 2 1 2 3 4 5 7 8 10 69 C516 22P_0402_50V8J 2 1 EC_GA20 EC_KBRST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 Place on RAM door E51RXD_P80CLK E51TXD_P80DATA ACES_85205-0400 @ AVCC VCC VCC VCC VCC VCC VCC 1109 RF request 18 EC_GA20 18 EC_KBRST# 13 SERIRQ 13 LPC_FRAME# 13 LPC_AD3 13 LPC_AD2 13 LPC_AD1 13 LPC_AD0 0.1U_0402_16V4Z 67 9 22 33 96 111 125 D 2 1 2 3 4 1 2 3 4 C505 1000P_0402_50V7K U32 +3VALW JP6 KSO[0..17] 37 2 1 1 1000P_0402_50V7K KSO[0..17] 1 1 2 2 0.1U_0402_16V4Z C488 2 2 2 0.1U_0402_16V4Z +3VALW_EC 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 2 C519 C533 C538 C524 C512 KSI[0..7] 37 1 1 For EC Tools KSI[0..7] 20mil 2 2 L32 FBMA-L11-160808-800LMT_0603 1 2 +EC_VCCA ECAGND 1 R385 0_0805_5% 40mil 2 +3VALW 1 5 3 2 SCHEMATICS,MB A5893 Document Number Rev C 401869 Wednesday, June 30, 2010 Sheet 1 36 of 56
  • 37.
    1 R391 +3VALW 2 0_0603_5% 1 C506 2 0.1U_0402_16V4Z To TP/BConn. 20mil +5VS 150mils 36 EC_SPICS#/FSEL# JTP1 U31 R406 4.7K_0402_5% 1 2 SPI_WP# 1 2 SPI_HOLD# R390 4.7K_0402_5% +3VALW 1 3 7 4 CE# WP# HOLD# VSS VDD SCK SI SO +SPI_VCC 8 6 5 2 EC_SPICLK 36 EC_SO_SPI_SI 36 EC_SI_SPI_SO 36 (Right) C682 @ 2 2 100P_0402_50V8J 100P_0402_50V8J INT_KBD Conn. 28 27 @ C497 TP_CLK LEFT_BTN# TP_DATA RIGHT_BTN# KSI[0..7] 36 KSO[0..17] +5VS KSO[0..17] 36 1 D19 PJDLC05C_SOT23-3 3 2 KSI[0..7] 3 2 33P_0402_50V8K D18 PJDLC05C_SOT23-3 C684 0.1U_0402_16V4Z LS-5893+LS-5894(Lid Board) LED/B RIGHT (90) LED/B LEFT (70) 1 2 3 4 5 6 7 8 9 10 GND GND ACES_88747-2601 CONN@ 2 100P_0402_50V8J 1 2 100P_0402_50V8J KSO15 C34 1 2 100P_0402_50V8J KSO7 C26 1 2 100P_0402_50V8J KSO14 C33 1 2 100P_0402_50V8J KSO6 C25 1 2 C32 1 2 100P_0402_50V8J KSO5 C24 1 2 C31 1 2 100P_0402_50V8J KSO4 C23 1 2 C37 1 2 100P_0402_50V8J KSO3 C22 1 2 C30 1 2 100P_0402_50V8J KSI4 C41 1 2 C29 1 2 100P_0402_50V8J KSO2 C21 1 2 C38 1 2 100P_0402_50V8J KSO1 C20 1 2 C39 1 2 100P_0402_50V8J KSO0 C19 1 2 100P_0402_50V8J KSO9 C28 1 2 100P_0402_50V8J KSI5 C42 1 2 100P_0402_50V8J KSI3 C40 1 2 100P_0402_50V8J KSI6 C43 1 2 100P_0402_50V8J KSO8 C27 1 2 100P_0402_50V8J KSI7 C44 1 2 +3VS 100P_0402_50V8J KSI2 2 100P_0402_50V8J KSI1 PWR_LED# ON/OFFBTN# 4 100P_0402_50V8J KSO10 ON/OFFBTN# 38 2 +3VALW 100P_0402_50V8J KSO11 +3VS LID_SW# ACIN_LED# 3G_LED# WLAN_LED# MEDIA_LED# 100P_0402_50V8J KSI0 3G_LED# 36 WLAN_LED# 36 1 2 3 4 5 6 7 8 9 10 11 12 100P_0402_50V8J KSO12 1 2 3 4 5 6 7 8 9 10 GND GND 100P_0402_50V8J KSO13 PWR_LED# ON/OFFBTN# +3VALW LID_SW# 36 SW3 SMT1-05-A_4P 1 100P_0402_50V8J ACES_85201-1005N CONN@ ACES_85201-1005N CONN@ +3VS +3VS 2 1 C36 LID_SW# ACIN_LED# 3G_LED# WLAN_LED# MEDIA_LED# 3 RIGHT_BTN# Q4A R272 @ 100K_0402_5% 1 C35 KSO17 4 JLED2 1 2 3 4 5 6 7 8 9 10 11 12 SW2 SMT1-05-A_4P 1 2 KSO16 3 LEFT_BTN# 5 6 JLED1 1 2 1 KSO0 G2 KSO1 G1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 1 C683 @ 5 6 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 1 (Left) TP_CLK 36 TP_DATA 36 LEFT_BTN# RIGHT_BTN# ACES_85201-0605N CONN@ @ R386 0_0402_5% JKB1 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 7 8 2 MX25L1005AMC-12G_SOP8 Reserved for BIOS simulator. Footprint SO8 1 2 3 4 5 6 1 2 3 4 5 6 GND GND 6 1 MEDIA_LED# 3 4 LED Status Power/SUS ON SUS Battery BlueTooth 3G/WLAN Full Charge 3G Blue Amber ACIN WLAN Blue Amber +3VS NEW70/80/90 Blue Amber ACIN_LED# B 1 1 2 2 2.2K_0402_5% PWR_LED# 2 91@ 1 R343 680_0402_5% D 3 LED3 1 71@ R343 PCH_SATALED# 13 2N7002DWH_SOT363-6 5 Q4B +3VS 5IN1_LED# 35 2N7002DWH_SOT363-6 S Q53 @ 2 G 36,42,43 ACIN HT-191NB5_BLUE 2N7002E-T1-GE3_SOT23-3 LED1 +3VALW 1 71@ R344 2 2 3.9K_0402_5% A 1 PWR_SUSP_LED# 2 91@ 1 R344 680_0402_5% HT-191UD5_AMBER 3 PWR_SUSP_LED# 6 PWR_LED# LED4 Q26A BATT_GRN_LED# BATT_GRN_LED# 36 2 91@ 1 R341 680_0402_5% 2 36 PWR_LED 2N7002DWH_SOT363-6 HT-191NB5_BLUE R340 100K_0402_5% Q26B 2N7002DWH_SOT363-6 5 36 PWR_SUSP_LED R335 100K_0402_5% 4 1 2 B 1 2 2 2.2K_0402_5% 2 1 71@ R341 1 71@ R342 2 2 3.9K_0402_5% A 1 BATT_AMB_LED# BATT_AMB_LED# 36 1 LED2 1 +3VALW 2 91@ 1 R342 680_0402_5% HT-191UD5_AMBER Bom option For 71 and 91 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: SCHEMATICS,MB A5893 Document Number Rev C 401869 Wednesday, June 30, 2010 Sheet 37 of 56
  • 38.
    A B C D E Power Button ON/OFF switch 2 +3VALW 1 1 R409 37ON/OFFBTN# 100K_0402_5% 1 TOP Side SW1 SMT1-05-A_4P 1 3 4 51ON# 3 @ EC_ON R413 Bottom Side S Q32 2N7002E-T1-GE3_SOT23-3 10K_0402_5% 1 SW4 SMT1-05-A_4P 1 3 4 6 5 @ D 2 G 2 36 EC_ON 2 51ON# 43 D12 CHN202UPT_SC70-3 1 6 5 ON/OFF 36 1 3 2 2 ON/OFFBTN# 2 2 Test Only Power ON Circuit +3VS +3VALW 1 +3VALW 14 For South Bridge P O 3 I O 4 7 G I 2 U21B SN74LVC14APWLE_TSSOP14 SYS_PWROK_1 1 R332 @ 2 0_0402_5% EC_PWROK 15,36 7 CH751H-40PT_SOD323-2 @ C455 1U_0603_10V6K @ 2 G 1 2 U21A SN74LVC14APWLE_TSSOP14 P 2 1 36,53 VR_ON 14 R331 180K_0402_5% D7 1 3 3 +3VS +3VALW 1 +3VALW Q25 C456 0.1U_0402_16V7K 2N7002E-T1-GE3_SOT23-3 S 14 P P U21D SN74LVC14APWLE_TSSOP14 6 9 I O 8 G O G I 1 R320 2 0_0402_5% VS_ON 51 For VTT 7 42,48 SUSP 5 2 D 2 G 3 SUSP U21C SN74LVC14APWLE_TSSOP14 7 1 36,42,46,48 SUSP# 2 R334 249K_0402_1% SUSP# 1 2 14 R333 10K_0402_1% @ 1 SUSP# 1 R321 @ 2 0_0402_5% +3VS +3VALW 1 3 2N7002E-T1-GE3_SOT23-3 S C447 DIS@ 1U_0603_10V6K 1 14 P 10 13 I O G O G I U21F SN74LVC14APWLE_TSSOP14 12 1 R317 DIS@ 2 0_0402_5% VGA_ON 24,42,50 4 7 Q23 DIS@ 2 G 42 DGPU_PWR_EN# 2 U21E SN74LVC14APWLE_TSSOP14 P 2 11 D 2 0.1U_0402_16V4Z 7 1 14,18,21,42 DGPU_PWR_EN 4 14 R319 31.6K_0402_1% @ R318 10K_0402_1% 1 DIS@ 2 +3VALW C448 1 DGPU_PWR_EN 1 R316 @ 2 0_0402_5% 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D SCHEMATICS,MB A5893 Document Number Rev C 401869 Sheet Wednesday, June 30, 2010 E 38 of 56
  • 39.
    5 4 3 2 1 +5VAMP 1 R339 1 R704 SHDN 4 BYP 1 2 C439 0.01U_0402_16V7K @ (output = 300mA) C780 1 36 BEEP# 2 1U_0402_6.3V4Z C785 1 13 PCH_SPKR 2 1U_0402_6.3V4Z 1 R699 C 2 2 B E 560_0402_5% 1 R701 1 C773 1 1U_0402_6.3V4Z Q49 D MONO_IN 2 GND 1 R694 1 R670 560_0402_5% AVDD1 Place near Codec 2 1 U48 C760 2 1K_0402_1% 1 C775 1 2 C776 1 INT_MIC 2 0.1U_0402_16V4Z LINE2_L LOUT1_L 35 AMP_LEFT LINE2_R LOUT_R 36 AMP_RIGHT MIC2_C_L 16 4.7U_0603_6.3V6K MIC2_C_R 17 4.7U_0603_6.3V6K 23 MIC2_L LOUT2_L LOUT2_R 40 MIC1_R MIC1_L C777 1 MIC1_R C778 1 LINE1_L SPDIFO2 45 LINE1_R DMIC_CLK1/2 46 LINE1_VREFO NC 43 20 40 MIC1_L LINE2_VREFO DMIC_CLK3/4 44 19 MIC2_VREFO MIC1_C_L 21 4.7U_0603_6.3V6K MIC1_C_R 22 2 4.7U_0603_6.3V6K MONO_IN 12 2 BITCLK 8 11 10 13 HDA_SYNC_AUDIO 5 13 HDA_SDOUT_AUDIO 40 MIC_PLUG# 40 HP_PLUG# R695 2 R685 2 36 EAPD 1 20K_0402_1% 1 5.11K_0402_1% MIC1_R MONO_OUT 1 R672 2 0_0402_5% 29 CPVEE MIC1_VREFO 28 HPOUT_R 32 CBN SDATA_OUT 47 EAPD 4 7 1 R687 2 33_0402_5% 13 HDA_SDIN0 13 30 SYNC SPDIFO1 HDA_SDIN0_AUDIO 31 RESET# GPIO0/DMIC_DATA1/2 GPIO1/DMIC_DATA3/4 SENSE A SENSE B 48 For EMI HDA_BITCLK_AUDIO 37 CBP PCBEEP_IN 2 3 13 34 SENSE_A SENSE_B 2 C752 22P_0402_50V8J 2 1 0_0402_5% 6 SDATA_IN 1 R686 MIC1_L B 13 HDA_RST_AUDIO# 272@amp AMP_RIGHT 40 41 18 MIC2_VREFO AMP_LEFT 40 39 MIC2_R 24 Internal MIC REF 272@ C B C754 2.2U_0402_6.3V6M 10mil MIC1_VREFO HP_RIGHT VREF 27 40 HPOUT_L AVSS1 AVSS2 1 C758 2 10mil R673 1 33 HP_RIGHT 40 CODEC_VREF JDREF External MIC REF 272@ 26 42 DVSS1 DVSS2 HP_LEFT 2 20K_0402_1% C764 1 C765 1 MIC2_VREFO 2.2U_0402_6.3V6M 2 0.1U_0402_16V4Z 2 10U_0805_10V4Z Int. MIC Place next pin27 HP_LEFT 40 For EMI 15mil JP1 1 2 1 2 G1 G2 1 R702 2 +3VS C746 10U_0805_10V4Z 2 15 INT_MIC_R L71 1 2 MBK1608121YZF_0603 1 C748 14 External MIC SM010032020 600ma 120ohm@100mhz DCR 0.25 +3VS_DVDD 1 GNDA 9 2 0.1U_0402_16V4Z DVDD 2 DVDD_IO 2 1 38 C 0.1U_0402_16V4Z C772 25 C738 10U_0805_10V4Z 1 AVDD2 +VDDA 2 0_0805_5% GND Place near Codec 10mil 2 0_0805_5% 1 R707 2 +AVDD_HDA 40mil 0.1U_0402_16V4Z 1 1 C739 2 0_0805_5% 1 R308 2SC2411K_SOT23-3 2 HD Audio Codec L70 1 2 FBMA-L11-160808-800LMT_0603 GNDA 2 2.4K_0402_1% D31 CH751H-40PT_SOD323-2 SM010015410 300ma 80ohm@100mhz DCR 0.3 2 0_0805_5% 2 1U_0402_6.3V4Z R696 10K_0402_5% 10K_0402_5% G9191-475T1U_SOT23-5 @ 2 0_0805_5% 1 R283 2 D32 CH751H-40PT_SOD323-2 1 4.75V +VDDA C783 R703 2.2K_0402_5% 15mil INT_MIC_L INT_MIC_R 2 FBMA-L11-160808-700LMT_2P 3 4 L29 1 1 ALC272X-GR_LQFP48_7X7 ACES_88266-02001 CONN@ C786 220P_0402_50V7K 3 AGND 2 2 DGND 2 3 0.1U_0402_16V4Z 5 OUT 2 2 GND 1 2 D IN 2 C438 40mil 3 1 C444 1 2 1 U19 60mil 0.1U_0402_16V4Z 2 L28 1 2 FBMA-L11-201209-221LMA30T_0805 @ L27 1 2 FBMA-L11-201209-221LMA30T_0805 1 +5VAMP +5VS R698 10K_0402_5% +3VS SM010014520 3000ma 220ohm@100mhz DCR 0.04 2 0_0805_5% 1 R329 1 2 0_0805_5% 1 1 R298 D10 PJDLC05C_SOT23-3 SM010004010 300ma 70ohm@100mhz DCR 0.3 A 1 A 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: 5 4 3 2 Sheet Wednesday, June 30, 2010 1 39 of 56
  • 40.
    A B Ri 90k 70k 45k 25k 0.1U_0402_16V4Z 1 10 dB C457 2 VDD PVDD1 PVDD2 R710 100K_0402_5% 39 AMP_LEFT C791 1 2 1 0.47U_0603_10V7KR712 9 AMP_C_LEFT 2 0_0603_5% 5 EC_MUTE# 19 2 18 SPKR+ ROUT- 14 SPKR- 4 SPKL+ 8 SPKL- RIN- @ R711 100K_0402_5% R708 100K_0402_5% LIN+ LIN- NC 12 BYPASS 10 SHUTDOWN Keep 10 mil width 2 GND5 GND1 GND2 GND3 GND4 36 EC_MUTE# 1 GAIN1 ROUT+ 2 1 GAIN0 3 LOUT- 2 0.47U_0603_10V7K 2 2 C793 1 AMP_C_RIGHT 17 2 0_0603_5% RIN+ 2 1 R697 7 GAIN0 LOUT+ C779 2 0.47U_0603_10V7K 2 0.47U_0603_10V7K @ R709 100K_0402_5% 1 GAIN1 1 +5VAMP 2 1 C453 10U_0805_10V4Z 1 39 AMP_RIGHT E 1 1 U50 C792 1 D +5VAMP 16 15 6 GAIN0 GAIN1 AV(inv) 0 0 6dB 0 1 10dB 1 0 15.6dB 1 1 21.6dB C C794 0.47U_0603_10V7K 21 20 13 11 1 1 2 2 TPA6017A2PWPR_TSSOP20 C787 330P_0402_50V7K 39 HP_LEFT R705 1 2 56.2_0603_1% HPOUT_L_1 39 HP_RIGHT R700 1 2 56.2_0603_1% HPOUT_R_1 1 L78 1 L77 2 1 2 (Use NAL00 PCB Footprint) C784 330P_0402_50V7K 1 Headphone Out JHP1 1 2 2 HPOUT_L_2 FBMA-L11-160808-700LMT_2P 2 HPOUT_R_2 FBMA-L11-160808-700LMT_2P 3 4 SM010004010 300ma 70ohm@100mhz DCR 0.3 39 HP_PLUG# HP_PLUG# 5 3 3 6 MIC1_VREFO SINGA_2SJ-0960-C01 CONN@ 1 2 3 Headphone Out D30 PJDLC05C_SOT23-3 1 1 D29 CH751H-40PT_SOD323-2 1 D27 CH751H-40PT_SOD323-2 Int. Speaker Conn. HP_PLUG# 2 2 MIC_PLUG# Left Side 1 2 R676 4.7K_0402_5% R688 D11 PJDLC05C_SOT23-3 @ G1 G2 39 MIC1_L ACES_88266-02001 CONN@ 39 MIC1_R MIC1_L_1 2 1K_0603_1% MIC1_R_1 2 1K_0603_1% R689 1 R674 1 1 Right Side 1 2 MIC1_R_R 1 C743 220P_0402_50V7K JMIC1 MIC1_L_R L73 1 2 FBMA-L11-160808-700LMT_2P L72 1 2 FBMA-L11-160808-700LMT_2P SM010004010 300ma 70ohm@100mhz DCR 0.3 MIC JACK 4.7K_0402_5% 3 2 3 4 3 2 2 20mil 1 2 1 SPK_L+ SPK_L- 2 0_0603_5% 2 0_0603_5% 2 R354 1 R359 1 2 1 2 3 JSPK2 SPKL+ SPKL- 4 D28 C759 PJDLC05C_SOT23-3 220P_0402_50V7K 39 MIC_PLUG# MIC_PLUG# JSPK1 SPK_R+ SPK_R- 1 2 6 1 2 4 SINGA_2SJ-A960-C01 CONN@ 3 2 0_0603_5% 2 0_0603_5% 2 SPKR+ R348 1 SPKR- R347 1 1 4 5 D9 PJDLC05C_SOT23-3 @ 3 4 G1 G2 ACES_88266-02001 CONN@ 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title SCHEMATICS,MB A5893 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: A B C D Sheet Wednesday, June 30, 2010 E 40 of 56
  • 41.
    @ H16 H_3P0 @ H22 H_3P0 @ 1 @ H3 H_3P0 1 @ H5 H_3P0 1 @ H1 H_3P0 1 @ H2 H_3P0 1 @ H20 H_3P0 1 @ H21 H_3P0 1 @ H17 H_3P0 1 1 1 @ H6 H_3P0 1 H15 H_3P0 1 H10 H_3P0 GNDA H11 H_3P0 H14 H_4P2 H13 H_4P2 H8 H_4P2 @ 1 1 +5VS 10U_0805_10V4Z 2 @ @ @ 1 C542 1 @ 1 +5VS 1 1 FAN1 Conn H9 H_4P2 @ @ C562 1000P_0402_50V7K H7 H_3P0N @ @ JFAN1 1 2 3 FD4 ACES_85205-03001 CONN@ FD2 @ FIDUCIAL_C40M80 2 @ FIDUCIAL_C40M80 FD3 @ FIDUCIAL_C40M80 @ FIDUCIAL_C40M80 Compal Electronics,Inc. Compal Secret Data Security Classification Issued Date FD1 1 36 FAN_SPEED1 H19 H_3P0X3P5N 1 40mil +VCC_FAN1 @ 1 H18 H_3P4 C563 1000P_0402_50V7K 1 2 R445 10K_0402_5% 1 @ 1 +3VS H4 H_4P0 1 2 @ BAS16_SOT23-3 C568 10U_0805_10V4Z 1 2 1 1 APL5607KI-TRG_SO8 C570 0.1U_0402_16V4Z 1 2 H12 H_4P0 D15 1 1 2 +VCC_FAN1 1 300_0402_5% D13 1SS355_SOD323-2 @ 8 7 6 5 1 2 R461 GND GND GND GND 2 36 EN_DFAN1 EN VIN VOUT VSET 1 U35 1 2 3 4 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: SCHEMATICS,MB A5893 Document Number Rev C 401869 Wednesday, June 30, 2010 Sheet 41 of 56
  • 42.
    C D E +3VALW TO +3V(PCHAUX Power) C1029 1 2 Q47B 20mil @ 1 0.1U_0603_25V7K Q16A SBPWR_EN# 2 SBPWR_EN# DIS@ @ VGA_ON# 5 2N7002DWH_SOT363-6 2 C421 @ 0.1U_0603_25V7K 2 2 5 1 S 2 G R345 100K_0402_5% 2 2 510K_0402_5% 2009/08/17 add VGA_ON# Q38 @ S 2N7002E-T1-GE3_SOT23-3 1 1 24,38,50 VGA_ON R231 DIS@ 22K_0402_5% 1 3 3 2N7002E-T1-GE3_SOT23-3 2N7002E-T1-GE3_SOT23-3 Q36 2 G SUSP S 2N7002E-T1-GE3_SOT23-3 Q37 @ 2 G SYSON# D S Q15 DIS@ 2 G 2N7002E-T1-GE3_SOT23-3 S 2N7002E-T1-GE3_SOT23-3 2009/08/14 CP_S3PowerReduction WhitePaper_Rev0.9 0.75VS speed up discharge 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A 2N7002E-T1-GE3_SOT23-3 4 2 SUSP Q24 DIS@ 3 2 G S VGA_ON# VGA_ON# 1 1 1 Q33 3 SUSP S R232 100K_0402_5% DIS@ 3 1 3 2 D 2 G D 1 D 1 D 2 G 2 R325 100K_0402_5% DIS@ +5VALW R569 470_0603_5% @ 1 R524 470_0603_5% 2 R427 470_0603_5% ACIN D 2 G 14,18,21,38 DGPU_PWR_EN C711 DIS@ 0.1U_0603_25V7K 1 +1.5V 2 2 1 +1.8VS 1 Q1 @ S 2N7002E-T1-GE3_SOT23-3 1 VGA_ON# R30 100K_0402_5% @ 2 1 R584 @ 2 5 D 3 2 G DGPU_PWR_EN# 38 DGPU_PWR_EN# 1 Q40A DIS@ 2 SBPWR_EN# 36 SBPWR_EN 3 1 1 20 SBPWR_EN# 4 1.5VSDGPU_GATE 1 2 1 R586 510K_0402_5% DIS@ VGA_ON# 2 Q40B 2N7002DWH_SOT363-6 DIS@ 6 1 3 Q10 @ S 2N7002E-T1-GE3_SOT23-3 R593 470_0603_5% DIS@ R326 100K_0402_5% DIS@ 2 20mil D 2 G 2 2 1U_0603_10V4Z 10U_0805_10V4Z +5VALW R31 100K_0402_5% @ 3 0.1U_0603_25V7K SI4856ADY_SO8 DIS@ C713 DIS@ 1 1 2 10U_0805_10V4Z +VSB +1.05VS_VTT S 1 2 DIS@ C717 DIS@ 1 1 SUSP 1 2 3 4 2 5 1 S S S G 1 C714 D D D D 3 1 2 C346 +5VALW U40 1 2 1 D Q11 3 R338 10K_0402_5% +1.5VSDGPU 8 7 6 5 2N7002DWH_SOT363-6 4 5 36,38,46,48 SUSP# Q34 @ 2N7002E-T1-GE3_SOT23-3 +1.5V 3 6 @ ACIN R200 22_0603_5% 1 6 VGA_ON# +1.5V to +1.5VSDGPU for GPU R181 470_0603_5% 4 1.5VS_GATE 2 Q9A 2N7002DWH_SOT363-6 +0.75VS 2 Q27B 2N7002DWH_SOT363-6 2N7002DWH_SOT363-6 D 3 1 Q9B 2N7002DWH_SOT363-6 510K_0402_5% 10mil R185 36,37,43 ACIN 2 510K_0402_5% 1 C338 2 1 10U_0805_10V4Z 2 2 1U_0603_10V4Z 4 C389 C328 2 SUSP C650 DIS@ 0.1U_0603_25V7K SUSP 38,48 SUSP Q27A SYSON +1.5VS U13 SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5 2 1 R184 105K_0402_1% +VSB 20mil 2 1 Q35A @ DIS@ 2N7002DWH_SOT363-6 1 2 1 Q35B 2N7002DWH_SOT363-6 DIS@ 1.8VSDGPU_GATE R472 1 2 C374 10U_0805_10V4Z C587 10U_0805_10V4Z C588 0.1U_0402_16V4Z 0.1U_0402_16V4Z 3 2 1 SYSON# 35 SYSON# 36,49 SYSON 10mil 2 1 R505 510K_0402_5% DIS@ +1.5V to +1.5VS 1 2 2 2 1U_0603_10V4Z 10U_0805_10V4Z R346 100K_0402_5% 1 +VSB ACIN 1 R337 100K_0402_5% R502 470_0603_5% DIS@ 1 20mil SUSP 2N7002DWH_SOT363-6 +1.5V 1 1 5 Q22B VGA_ON# 1211 EMI ADD 0.1U close PJ5 C664 DIS@ 3 DIS@ 2 10U_0805_10V4Z 1 2 0.1U_0603_25V7K C648 DIS@ 2 2 2 C450 C670 1 +5VALW 4 1 +5VALW 1 R315 470_0603_5% 4 2 1 3VS_GATE Q22A SUSP C446 1 10mil Q59 @ S 2N7002E-T1-GE3_SOT23-3 2 2 1 R322 200K_0402_5% +VSB 1 10U_0805_10V4Z 2 2 1U_0603_10V4Z 6 20mil U37 DIS@ SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5 6 C451 10U_0805_10V4Z 2 2 10U_0805_10V4Z 2 +1.8VS to +1.8VSDGPU for GPU +1.8VSDGPU 2N7002DWH_SOT363-6 4 3 1 C454 1 4 1 C449 C1030 DIS@ 0.1U_0603_25V7K +1.8VS +3VS U20 SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5 VGA_ON# D 2 G 1 +3VALW TO +3VS 2 2 510K_0402_5% ACIN 2N7002DWH_SOT363-6 +3VALW R867 @ Q16B 2N7002DWH_SOT363-6 1 2N7002DWH_SOT363-6 Q58B DIS@ 1 2 2 +1.05VSDGPU_GATE 2 1 Q58A 2N7002DWH_SOT363-6 DIS@ 3 Q47A 2 5 @ 3V_GATE 1 200K_0402_5% SUSP 1 10K_0402_5% 10mil R255 2 +VSB 2N7002DWH_SOT363-6 C756 10mil R866 4 6 SUSP 4 5 1 20mil +VSB 5VS_GATE 6 10mil 2 1 R684 200K_0402_5% +VSB 4 20mil R865 470_0603_5% DIS@ 2 10U_0805_10V4Z R226 @ 470_0603_5% 10U_0805_10V4Z 2 2 1U_0603_10V4Z 1 + @ C1027 2 330U_D2_2V_Y 1U_0603_10V4Z 2 1 C392 DIS@ C1028 DIS@ 6 1 C393 4A 1 4 40mil +1.05VSDGPU 1 10U_0805_10V4Z +3V 4 1 C407 2 2 +1.05VS_VTT U63 DIS@ SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5 1 1 R692 470_0603_5% 10U_0805_10V4Z 2 2 1U_0603_10V4Z 1 4 C767 1 @ JUMP_43X79 U14 @ SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5 2 C761 1 1 10U_0805_10V4Z 2 2 10U_0805_10V4Z 1 1 3 1 C766 +5VS U49 SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5 4 1 C763 J5 2 +5VALW +1.05VS_VTT to +1.05VSDGPU for GPU Short J5 for PCH VCCSUS3.3 +3VALW 3 1 +5VALW TO +5VS 1 2 B 3 A B C D SCHEMATICS,MB A5893 Document Number Rev C 401869 Sheet Wednesday, June 30, 2010 E 42 of 56
  • 43.
    A B C D VIN 1 VIN VIN VS PR296 10K_0402_5% PR297 84.5K_0402_1% 2 1 2 PC210 0.1U_0603_25V7K 2 1 2 PR303 10K_0402_1% 1 2 1 2 2 8 P 3 - O PU18A LM393DG_SO8 PD1 GLZ4.3B_LL34-2 2 PR302 10K_0402_1% + G 1 1 36,37,42 ACIN PR298 22K_0402_5% 1 2 4 1 PC209 1000P_0402_50V7K PR299 10K_0402_5% 1 2 1 PC207 100P_0402_50V8J 46,47 PACIN 2 1 1 PC206 1000P_0402_50V7K PC208 100P_0402_50V8J 2 2 ACES_50305-00441-001 2 1 2 2DC_IN_S2 1 DC_IN_S1 1 2 3 4 GND GND 1 PL24 SMB3025500YA_2P 1 PJP1 PR295 1M_0402_1% 1 2 PR301 20K_0402_1% 1 PC211 1000P_0402_50V7K RTCVREF VinDectector 2 Min. H-->L 16.976V L-->H 17.430V Typ 17.525V 17.901V 2 Max. 17.728V 18.384V VIN 2 PJ6 +3VALWP PD2 LL4148_LL34-2 1 1 +3VALW PJ2 +VGFX_COREP PR304 68_1206_5% 2 2 1 38 51ON# 1 +1.5VP VS 1 1 2 PJ11 +VSBP PC213 0.1U_0603_25V7K 2 2 1 1 +VSB JUMP_43X39 2 +1.8VSP 2 2 +1.5V 1 GND PC214 10U_0805_10V4Z +1.8VS 1 +1.05VS_VTT PJ15 PC215 1U_0805_25V4Z - PBJ1 2 ML1220T13RE <BOM Structure> 2 1 1 2 1 1 +VGA_CORE JUMP_43X118 PJ16 2 2 1 1 +0.75VS JUMP_43X39 + 1 2 2 +VGA_COREP 2 +0.75VSP 1 1 JUMP_43X118 PJ17 N2 2 4 1 2 JUMP_43X118 PJ10 2 2 1 1 JUMP_43X118 1 IN 2 1 OUT 1 3 2 1 PR309 200_0603_5% PU14 G920AT24U_SOT89-3 3.3V 2 1 PJ9 RTCVREF +CHGRTC 2 JUMP_43X118 +1.05VS_VTTP PR311 560_0603_5% 1 2 3 JUMP_43X118 PJ7 2 2 1 1 PJ14 PR310 560_0603_5% 1 2 +VGFX_CORE 2 2 PR308 22K_0402_1% 1 2 1 PJ5 1 PC212 0.22U_0603_25V7K 2 PR307 100K_0402_1% 1 JUMP_43X118 +5VALW 1 3 +5VALWP 2 JUMP_43X118 2 N1 PJ8 PR305 68_1206_5% 2 JUMP_43X118 PJ4 2 2 1 1 1 PQ42 TP0610K-T1-E3_SOT23-3 PR306 200_0603_5% CHGRTCP 1 2 1 1 BATT+ 2 JUMP_43X118 2 3 PD3 LL4148_LL34-2 2 1 2 4 JUMP_43X118 +RTCBATT +RTCBATT Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: A B C Wednesday, June 30, 2010 D Sheet 43 of 56
  • 44.
    A EC_SMCA TH PI D PH1 under CPUbotten side : CPU thermal protection at 92 degree C 2 EC_SMDA C 1 PR542 100_0402_1% 1 2 1 10 9 8 7 6 5 4 3 2 1 GND GND 8 7 6 5 4 3 2 1 B PJP2 SUYIN_200275GR008G13GZR PR543 100_0402_1% VL EC_SMB_DA1 36 1 <40,41> VMB VL GND RHYST1 8 7 3 OT1 TMSNS2 6 OT2 RHYST2 5 G718TM1U_SOT23-8 1 @ PR551 @PR551 47K_0402_1% 1 2 4 2 PR549 9.53K_0402_1% 2 VCC TMSNS1 2 PR550 1K_0402_1% @ PR547 @PR547 100K_0402_1% 2 1 1 PR546 21K_0402_1% 1 PU30 +3VALWP 1 PR545 10K_0402_1% PH1 100K_0402_1%_NCP15WF104F03RC 1 PC380 0.01U_0402_25V7K 2 PC381 0.1U_0603_25V7K PR548 6.49K_0402_1% 2 1 2 1 PR544 1K_0402_5% 1 PC379 1000P_0402_50V7K 2 2 1 2 BATT_S1 EC_SMB_CK1 36 1 <40,41> BATT+ PL44 SMB3025500YA_2P 1 2 2 1 CONN@ 2 BATT_TEMP 36 1 MAINPWON 18,45,47 2 2 2 @ PH2 @PH2 100K_0402_1%_NCP15WF104F03RC +VSBP 2 2 1 1 PC222 0.1U_0603_25V7K 3 3 2 2 PR327 22K_0402_1% 1 2 VL 2 PR325 100K_0402_1% 3 1 1 B+ PC221 0.22U_0603_25V7K PQ44 TP0610K-T1-E3_SOT23-3 PC224 1U_0402_6.3V6K PQ45 2 G D S 2N7002W-T/R7_SOT323-3 2 1 45 SPOK PR330 1K_0402_5% 2 1 1 3 1 PR329 100K_0402_1% 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: A B C Wednesday, June 30, 2010 D Sheet 44 of 56
  • 45.
    5 4 3 1 ISL6237_B+ ISL6237_B+ B+ HG5 VBST2 VBST1 17 BST5A 1 0_0603_5% VOUT2 DRVL1 LG5 PGND 22 VOUT1 10 FB1 32 16 18 11 1 2 PC236 0.1U_0603_25V7K REFIN2 1 FB5 20 VSW 9 5V_SKIP EN_LDO PGOOD1 13 TRIP1 12 ILM1 TRIP2 31 ILIM2 GND EN2 TONSE EN1 VREF3 14 21 2 5 PC241 1U_0603_10V6K 2 13/5V_NC VL SPOK 44 RT8206BGQW QFN32P PR344 402K_0402_1% 2 1 2 1 PR345 267K_0402_1% For +5VALWP Power Budget=8.8A, Ipeak=7A, I max=4.9A Fsw=375KHz by RT8206 setting. ∆I=2.09A, 1/2∆I=1.05A 5uA*PR344=10*Iocpmin*18mΩ*1.2 =>PR344=397KΩ~402KΩ B 13/5V_TON 5uA*402K=10*ILIMTmin*18mΩ*1.2 ILIMTmin=9.305A 5uA*402K=10*ILIMTmax*15mΩ*1.1 ILMIT=12.181A Iocp=10.355A~13.231A For +3VALWP Power Budget=5.98A, Ipeak=5.98A, Imax=4.2A Iocpmin=5.98*1.2=7.2A Fsw=300KHz, ∆I=1.933A, 1/2∆I=0.966A 5uA*PR345=10*Iocpmin*Rdsonmax 5uA*PR345=10*5.7A*18mΩ PR345=266.76K~267K PR350 0_0402_5% 2VREF_ISL6237 2VREF_ISL6237 1 PR347 0_0402_5% 1 TP0610K-T1-E3_SOT23-3 2 2 PC243 @ 0.047U_0402_16V7K 2 1 1 2 PQ50 3 080414:PQ23 ,Del @ 28 2 2 @ 2 2 PR349 PR349 47K_0402_5% 1 1 @ PR346 @PR346 0_0402_5% PC242 0.047U_0402_16V7K 18,44,47 MAINPWON PR348 0_0402_5% 2 1 PGOOD2 27 PD8 1SS355_SOD323-2 PR561 806K_0603_1% NC 2 1 @ PR340 @PR340 0_0402_5% 1 2 PR341 0_0402_5% 2 2 3/5V_EN1 PC240 0.22U_0603_25V7K 1 1 B 4 29 1 VS PR343 200K_0402_5% 1 2 VL EN_LDO C LDOREFIN SKIPSEL PR342 100K_0402_1% 2 PC237 220U_6.3VM_R15 VREF2 8 1 PC238 680P_0603_50V7K + 2 PR339 0_0402_5% 1 2 30 VL EN_LDO-1 1 1 DRVL2 FB3 LL1 LL2 2 23 3 2 1 25 LG3 SW5 PC239 0.22U_0603_25V7K PD7 RLZ5.1B_LL34 1 2 PR336 4.7_1206_5% 2BST5A-1 PR334 1 SW3 2VREF_ISL6237 VS PQ49 AO4712_SO8 @ PR337 61.9K_0402_1% 1 2 15 2 DRVH1 +5VALWP PL27 4.7UH_SIL104R-4R7PF_5.7A_30% 2 1 1 3 2 1 DRVH2 5 6 7 8 7 3 6 19 D PQ47 AO4466_SO8 4 2 2 1 PC232 1U_0603_10V6K 1 2 V5DRV PC234 0.1U_0603_25V7K PR338 @ 10K_0402_1% C 4 2 2 1 4 LDO 24 V5FILT 2 BST3A PR333 1 2 3 PC235 680P_0603_50V7K 26 8 7 6 5 1 UG3 BST3A-1 1 PQ48 0_0603_5% AO4712_SO8 13V_SNB 2 2 2 TP VIN PU16 PR332 4.7_1206_5% PR335 0_0402_5% 1 + PC231 4.7U_0603_6.3V6K 2 1 3/5V_VIN 2 1 PC229 0.1U_0603_25V7K 33 1 PC230 1U_0603_10V6K 3/5V_VCC 1 2 8 7 6 5 PQ46 AO4466_SO8 4 PL28 4.7UH_SIL104R-4R7PF_5.7A_30% 1 2 +3VALWP 5 6 7 8 VL 1 2 3 JUMP_43X118 D PC228 2200P_0402_50V7K 2 1 1 PC226 2200P_0402_50V7K 2 1 1 PC225 10U_1206_25V6M 2 1 2 PC227 10U_1206_25V6M 2 1 PR331 0_0805_5% 1 2 PJ19 2 PC233 220U_6.3VM_R15 2 5uA*267KΩ=10*ILIMTmin*18mΩ ILIMTmin=7.42A 5uA*267KΩ=10*ILIMTmax*15mΩ ILIMTmax=8.9A Iocp=8.39A~9.86A A A 2008/08/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 45 of 56
  • 46.
    A B Iada=0~4.74A(90W/19V=4.736A) Iada=0~3.42A(90W/19V=3.421A) P2 P3 PQ52 AO4407A_SO8 B+ CHG_B+ B+ PR351 0.02_2512_1% PQ53AO4407A_SO8 PJ18 3 EN CSON 22 CELLS CSOP 21 ICOMP CSIN 20 VCOMP CSIP 19 ICM PHASE 18 8 VREF UGATE 17 CHLIM BOOT 16 ACLIM VDDP 15 D GND PGND 13 PC247 2200P_0402_25V7K 2 1 4 2 PC246 0.1U_0603_25V7K 2 1 1 3 2 1 PR376 4.7_0603_5% PC265 4.7U_0603_6.3V6K 12600mV 2 2 1 4 0.02_1206_1% 3 ISL6251AHAZ-T_QSOP24 3 <40,41> 2 1 PR379 15.4K_0402_1% 1 2 8 2 5 - 6 PR384 105K_0402_1% 2 CV mode 1 1 + PC267 0.01U_0402_25V7K PU13B LM358DT_SO8 7 0 P PR383 10K_0402_1% 1 2 G 36 BATT_OVP PR382 499K_0402_1% 2 2 1 Per cell=4.5V PR380 340K_0402_1% 1 BATT-OVP=0.1112*VMB 4 Kv Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K R=514K//31.6K//(15.4K+3k)=11.372K r=514K//514K//31.6K=28.14K Vcell=0.175*Vadj+3.99v 4.2V=0.175*Vadj+3.99V =>Vadj=1.2V Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K)) 1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899 1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv A=Vref*(R/(R+514K))=0.052 Kv=9.451 VS LI-3S :13.5V----BATT-OVP=1.5012V PC266 0.01U_0402_25V7K 1 PR381 31.6K_0402_1% 4 Normal 3S LI-ON Cells 1 2 1 1 12 RB751V-40_SOD323-2 1 26251VDD 2 LGATE 6251VDDP DL_CHG 3 2 1 VADJ 14 BATT+ PR369 PQ64 AO4466_SO8 4 2 11 PC260 0.1U_0603_25V7K 2 BST_CHGA 2 1 PD13 <40,41> TCR=50ppm / C S Ki Vchlim=Iref*(PR374/(PR372+PR374)) =Iref*(100K/(80.6K+100K)) =Iref*0.5537 Ichanrge=(165mV/PR369)*(Vchlim/3.3V) =(165m/20m)*(1/3.3V)*Iref*0.5537 =1.3842*Iref Iref=0.7224*Ichanrge =>Ki=0.7224 Charging Voltage (0x15) 10 20K_0402_1% PR378 PR373 0_0603_5% BST_CHG 1 2 BATT Type PL29 10UH_MMD-10DZ-100M-X1_6A_20% CHG 1 2 VMB 36 CALIBRATE# CC=0.6~4.48A Iref=0.7224*Ichanrge kI=0.7224 IREF=0.43V~3.24V 2 4 2N7002W-T/R7_SOT323-3 3 CP mode Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) where Vaclm=1.502V, Iinput=4.07A PQ62 AO4466_SO8 5 6 7 8 2 1 3 PQ66 2 G CSOP 2 6251ACLIM 12.1K_0402_1% 36 65W/90W# CSON 1 6251VREF 1 PR375 2 1 PR374 100K_0402_1% 2 .1U_0402_16V7K 2 1 3 IREF 6251VREF PC259 1 2 PR377 PR377 2.55K_0402_1% 36,47 ACOFF 36 PC245 10U_1206_25V6M 2 1 DH_CHG 6 PR368 100_0402_1% 1 2 2 PC258 @ 100P_0402_50V8J PR372 80.6K_0402_1% 2 1 5 2 10K_0402_1% 1 36 ADP_I PR371 22K_0402_5% PACIN 1 2 ACOFF 1 PR366 2 PC256 0.01U_0402_25V7K ACON PQ65 PDTC115EU_SOT323 1 1 43,47 PACIN S 2 1 PC261 0.01U_0402_25V7K 2 1 ACON 1 47 D 2N7002W-T/R7_SOT323-3 3 PQ63 2 G 6800P_0402_25V7K 2 1 PC255 1 3 PR363 20_0402_5% 1 2 PC254 0.047U_0402_16V7K 1 2 PR364 20_0402_5% 2 1 PR365 PC257 20_0402_5% 0.1U_0603_25V7K 1 2 PR367 2_0402_5% LX_CHG 2 7 6251_EN 2 PACIN 2N7002W-T/R7_SOT323-3 G S PC264 10U_1206_25V6M 2 1 23 D PQ61 3 ACSET ACPRN 2 1SS355_SOD323-2 PC263 10U_1206_25V6M 2 1 2 DCIN 24 1 PC253 0.1U_0603_25V7K 2 1 DCIN PD12 2 PR370 4.7_1206_5% VDD wrong Value PC252 0.1U_0603_25V7K 2 1 ACOFF 2 1SS355_SOD323-2 PR357 200K_0402_1% 1 2 VIN PC262 680P_0402_50V7K 1 PD9 5 6 7 8 1 2 S PQ57 PDTC115EU_SOT323 VIN 1 1 1 1 3 PU17 2 2 SUSP# 36,38,42,48 BAS40CW_SOT323-3 9 PQ60 PDTC115EU_SOT323 36 3S/4S# SUSP# 3 100K_0402_1% 1 1 1 1 1 1 2 PC251 .1U_0402_16V7K 2 1 PR352 47K_0402_1% 1 2 PR356 10K_0402_1% FSTCHG 2 1 3 1 D PR360 47K_0402_5% 2 1 PQ55 PDTC115EU_SOT323 PR358 2 4 PR361 150K_0402_1% 2N7002W-T/R7_SOT323-3 3 PQ59 2 G PR359 10K_0402_5% 2 1 FSTCHG DCIN 8 7 6 5 1 PD10 PD11 1SS355_SOD323-2 6251VDD 1 2 6251VDD 2 1 1 2 3 CSIN JUMP_43X118 3 P3 36 FSTCHG PQ58 PDTC115EU_SOT323 1 CSIP 47K 2 2 1 PQ54 TP0610K-T1-E3_SOT23-3 PQ56 PDTA144EU_SOT323-3 47K 3 2 2 PR354 200K_0402_1% 4 2 PC248 5600P_0402_25V7K 1 2 4 3 2 2 1 PR353 47K_0402_1% PC249 0.1U_0603_25V7K 2 1 1 4 1 1 PC244 10U_1206_25V6M 2 1 8 7 6 5 PC250 2.2U_0603_6.3V6K 2 1 1 2 3 PR362 2 1 2 3 100K_0402_1% 8 7 6 5 PR355 100K_0402_1% 2 1 VIN 3 D CP = 85%*Iada ; CP = 4.07A CP = 85%*Iada ; CP = 2.91A ADP_I = 19.9*Iadapter*Rsense PQ51 AO4407A_SO8 C 4 12.60V Issued Date - Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: A B C Wednesday, June 30, 2010 D Sheet 46 of 56
  • 47.
    5 4 3 2 1 D D B+ PR385 2.2M_0402_5% 1 PR386 1K_1206_5% 1 2 2 1 PR393 1 2 1 1 2 PC270 0.01U_0402_25V7K 2 PR398 47K_0402_5% 2 2 1 2N7002W-T/R7_SOT323-3 G 3 S PR396 100K_0402_5% 36,46 ACOFF 1 2 1 D PQ69 C PQ68 PDTC115EU_SOT323 2 PQ70 PDTC115EU_SOT323 PACIN43,46 1 PQ71 PDTC115EU_SOT323 @ PR399 @PR399 66.5K_0402_1% 3 PR397 34K_0402_1% 2 1 2 2 1 PR395 499K_0402_1% B+ 1 1 RTCVREF PR394 191K_0402_1% PRG++ 2 PC268 0.1U_0603_25V7K 1 6 2 2 1 BAS40CW_SOT323-3 - O PR391 1K_1206_5% 1 2 32.4 7 3 3 PR390 1K_1206_5% 1 2 PU18B LM393DG_SO8 5 1 P 1 46 ACON + G 2 PC269 1000P_0402_50V7K 8 2 PD15 1 LL4148_LL34-2 4 18,44,45 MAINPWON TP0610K-T1-E3_SOT23-3 PQ67 PR388 1K_1206_5% 1 2 PD14 2 100K_0402_5% 1 VS PR389 100K_0402_1% C VIN PR387 499K_0402_1% 100K_0402_5% 1 2 PR392 1 VL 2 +5VALW 3 2 3 2 ACIN B Precharge detector Min. typ. Max. H-->L 14.589V 14.84V 15.243V L-->H 15.562V 15.97V 16.388V B BATT ONLY Precharge detector Min. typ. Max. H-->L 6.138V 6.214V 6.359V L-->H 7.196V 7.349V 7.505V A A Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Issued Date Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 47 of 56
  • 48.
    5 4 3 2 1 D D C C PL30 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20% 1 2 +1.8VSP 2 LX_1.8V FB 2 GND 3 SW 4 IN 5 BS EN/SYNC 2 1 1 1.8V_EN 10 PC279 22U_0805_6.3V6M 1 1 PC278 22U_0805_6.3V6M 2 PR563 4.7_1206_5% PU20 MP2121DQ-LF-Z_QFN10_3X3 1 PR407 402K_0402_1% 1 2 2 PR405 309K_0402_1% 1 VFB=0.8V 8 IN 6 PC382 680P_0402_50V7K 7 POK 2 SW B @ PD16 @PD16 +1.5V B340A_SMA2 +1.5VS OP1 Short OP1PR409 PC287 PQ78 OP2 PR409 PJ20 JUMP_43X79 2 PJ25 JUMP_43X79 PU21 2 2 2 1 1 OP2 Short 7 3 6 VOUT NC 5 TP 9 1 VREF VCNTL 4 +3VALW 8 NC 2 PR408 1K_0402_1% 2 1.8V_EN NC GND 2 36,38,42,46 SUSP# OP2@ PR409 0_0402_5% 1 PC284 4.7U_0603_6.3V6K PR401 22K_0402_5% 1 2 VIN 2 2 1 1 11 2 TP 1 1 1 PC283 10U_0805_10V4Z 2 2 PC282 10U_0805_10V4Z PR566 0_0402_5% 1 2 9 1 0.01U_0402_16V7K +5VALW B 2 GND 1 PC281 1 PC285 1U_0402_6.3V6K 1 PR410 1K_0402_1% 2008/08/10 Deciphered Date PC288 10U_0805_6.3V6M A Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date +0.75VSP 1 2N7002W-T/R7_SOT323-3 2 S 2 S G PC286 .1U_0402_16V7K 2 1 D susp 2 1 PQ78 1 PC287 .1U_0402_16V7K A D 2N7002W-T/R7_SOT323-3 3 1 PQ72 2 G 1 PR409 28K_0402_1% 1 2 3 38,42 SUSP PC274 0.47U_0603_16V7K 2 2 1 APL5336KAI-TRL_SOP8P8 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 48 of 56
  • 49.
    A B C D B+ PJ21 1 PC290 4.7U_0805_25V6-K 1 1 1 3 2 1 14 +1.5VP 10 1 5 6 7 8 1 2 PR415 4.7_1206_5% 2 1 PC295 4.7U_0805_10V6K 1 + PC293 330U_6.3V_M 2 PC294 680P_0603_50V7K 3 2 1 RT8209BGQW_WQFN14_3P5X3P5 2 4 2 9 PQ74 AO4456_SO8 LG_1.5V 1 LGATE +5VALW PR417 11K_0402_1% NC BOOT PGND 2 LX_1.5V 11 2 Rds=4.5mΩ(Typ) 5.6mΩ(Max) 2 VFB=0.75V VFB=0.75V Vo=VFB*(1+PR418/PR419)=1.52V Freq=282KHz(min) , 300KHz(typ) 1 PR418 5.9K_0402_1% 1 2 2 JUMP_43X118 PL32 1UH_FDUE1040D-1R0M-P3_21.3A_20% 1 2 PC292 1 0.1U_0603_25V7K 2 7 1 @PC297 47P_0402_50V8J 1 2 PC296 4.7U_0603_6.3V6K 15 1 6 open-drain PGOOD 12 VDDP FB UG_1.5V CS GND PR416 100_0603_1% 1 2 13 PHASE VDD 5 PR414 0_0603_5% 1 2BST_1.5V-1 UGATE VOUT 4 +5VALW TON 3 EN/DEM 2 2 8 1 BST_1.5V PU22 2 4 1.5V_EN @ PC291 @PC291 .1U_0402_16V7K 2 @ PR413 @PR413 47K_0402_5% 2 1 PR411 280K_0402_1% 1 2 1 PR412 0_0402_5% 1 2 36,42 SYSON PQ73 AO4466_SO8 2 5 6 7 8 Because +1.5VSP has 17.74A power budget, it includes DDR3, VGA chip, VRAM, so must use molding choke. 1 PC289 4.7U_0805_25V6-K 51117_1.5V_B+ EN_PSV 1. GND=>Disable SMPS 2. FLOAT=>PWM_only mode 3. HIGH=>Auto_skip mode PR419 5.76K_0402_1% 2 Cesr=15m ohm Ipeak=13.61A Imax=9.527A Vtrip=Rtrip*10uA=0.11V Iocp-min=Vtrip/(Rds(on)(max)*1.2)+Delta I / 2= 18.67A Iocp-max=Vtrip/(Rds(on)(typ)*1.2)+Delta I / 2=22.67A Iocpmin=18.67A ∆I=((19-1.5)*(1.5/19))/(L*Freq)=4.605A 1/2∆I=2.3A Iocp=18.67A~22.67A 3 3 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: A B C Wednesday, June 30, 2010 D Sheet 49 of 56
  • 50.
    4 3 2 VGA_CORE Ipeak=27.82A,Imax=19.47A Delta I /2 = 3.97A , Freq=1/ 75E-12*PR134=300K Hz Iocp(min)=1.2*Ipeak+Delta I / 2 = 37.354A Rsen=Iocp(min)*1.2*Rds(on)(max)/ISEN(min)=6.49K ohm ISEN(min)=19uA , Rds(on)=5.6m ohm(max) ,4.5m ohm(typ) Iocp(max)=ISEN(min)*Rsen/(1.2*Rds(on)(typ))=45.67A Iocp=36.7~45.67A PJ22 1 B+_CORE LX_VCORE VGA@ PR161 0_0603_5% DH_VCORE-1 1 2 VGA@ PR124 0_0603_5% VGA@ PC101 1 2 1 2 BST_VCORE 0.1U_0603_25V7K DH_VCORE 18 VGA_PWROK VGA@ PR126 4.7_0603_5% 1 2 7138_VCORE UG BOOT 2 VIN PVCC 5 1 VGA@ PR125 0_0603_5% 15 1 PHASE PGOOD 14 DCR=1.1mΩ(typ) 2.2U_0603_6.3V6K 7138_VCORE LG PGND 11 VGA@ PL9 0.36UH_ETQP4LR36WFC_24A_20% 1 4 12 ISEN DL_VCORE 13 VCC 0.95V 0.95V @ PR146 10K_0402_5% 1 22 GPU_VID0 VGA@ PR148 10K_0402_5% 1 2 2 G VGA@ PR150 10K_0402_5% 1 1 2 2 1 1 1 @ PR144 10K_0402_1% @ PR145 10K_0402_5% D GE1@ PQ76 2N7002W-T/R7_SOT323-3 D GE1@ PR147 10K_0402_5% 2 2 1 G S VGA@ PQ77 2N7002W-T/R7_SOT323-3 GPU_VID1 22 GE1@ PR149 10K_0402_5% S A 2 A 1 2 VGA@ PC111 4700P_0402_25V7K +3VSDGPU GE1@ PC110 @ PR143 4700P_0402_25V7K 10K_0402_1% 2 0.9V S 1 0 2 G S 3 0 GE1@ PQ38 2N7002W-T/R7_SOT323-3 2 0.9V VGA@ PQ75 2N7002W-T/R7_SOT323-3 2 0.85V D 2 G 2 0.85V VGA@ PR142 10K_0402_5% 2 1 2 0 1 1 3 2 1 1 2 0.85V 3 0.8V 1 reserve +3VSDGPU 2 1 GE1@ PR141 10K_0402_5% 1 2 D Core Voltage Level 0 +3VSDGPU GE1@ PR139 10K_0402_5% VGA@ PR140 10K_0402_5% reserve +NVVDD_SENSE 23 2 +3VSDGPU 1 reserve +NVVDD_SENSE B GE1-1@ PR137 20K_0402_1% 1 reserve C VGA@ PR132 10_0402_5% 2 1 1 GE@ PR137 30.9K_0402_1% 1 1 N11P-GE 1 1 Core Voltage Level 2 VGA@ PR135 4.99K_0402_1% GV2H@ PR136 49.9K_0402_1% 3 Core Voltage Level 5 6 7 8 5 6 7 8 3 2 1 Rds=4.5mΩ(typ) 5.6mΩ(max) 2 1 GE1@ PR136 30.9K_0402_1% 1 GPU_VID1 + ESR=10 mΩ VGA@ PR127 0_0402_5% VGA@ PC106 470P_0603_50V8J @PC998 for IC APW7138 2 GPU_VID0 4 VGA@ PR129 4.7_1206_5% GE@ PR136 60.4K_0402_1% GV2H@ PR138 11.8K_0402_1% N11P-GE1 1 VFB=0.6V GE1@ PR138 28K_0402_1% N11P-GV2H +VGA_COREP 3 VGA@ PC104 390U_2.5V_M VO 10 2 @ PC998 0.01U_0402_25V7K GE@ PR138 14.7K_0402_1% B 2 VGA@ PQ36 AO4456_SO8 4 Layout Note: Close IC 單獨拉回不搭Pin15 1 VGA@ PR134 44.2K_0402_1% 2 1 2 1 2 VGA@ PC109 2200P_0402_25V7K VGA@ PC107 22P_0402_50V8J 2 1 Layout Note: Close IC VGA@ PR133 33K_0402_1% VGA@ PQ35 AO4456_SO8 VGA@ PR131 1 2 6.49K_0402_1% 9 FB NC 6 VGA@ PC105 .1U_0402_16V7K 1 2 C FSET EN 3 2 1 5 1 VGA@ PR130 30K_0402_1% 1 2 APW7138NITRL_SSOP16 VGA@ PC103 2.2U_0603_6.3V6K 7 VGA_ON 24,38,42 VGA_ON 1 2 4 VGA@ PQ34 TPCA8030-H_SOP-ADV8-5 4 Layout Note: Close IC VGA@ PC102 1 2 1 3 +3VSDGPU 16 2 8 GND VGA@ PU998 @ PR128 10K_0402_5% D +5VS 3 2 1 1 2 VGA@ PC100 10U_1206_25V6M VGA@ PC99 10U_1206_25V6M VGA@ PC98 10U_1206_25V6M 2 1 2 D VGA@ PC171 0.1U_0805_50V7K 2 1 1 JUMP_43X118 2 1 1 2 2 2 1 B+ 1 2 5 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: 5 4 3 2 Sheet Wednesday, June 30, 2010 1 50 of 56
  • 51.
    5 4 3 2 1 PJ23 6268_B+ LX_1.05VS_VTT 12 5 PC330 2.2U_0603_6.3V6K ISEN 2 4 10 @ PC999 0.01U_0402_25V7K @PC999 forIC APW7138 PR472 5.11K_0402_1% 1 2 @ 4 3 2 1 VO PR467 5.23K_0402_1% 1 2 1 PR470 57.6K_0402_1% 1 PR469 90.9K_0402_1% 1 1 2 11 2 PC336 6800P_0402_25V7K 1 2 22P_0402_50V8J PC334 +1.05VS_VTT Ipeak=20.14A Imax=14.10A Delta I / 2 = 2.176A , Freq=230K Hz Iocp(min)=1.2*Ipeak + Delta I / 2 = 26.34A Rsen=Iocp(min)*1.2*Rds(on)(max)/ISEN(min)=5.23K ohm ISEN(min)=19uA , Rds(on)=3.2m ohm(max) ,2.3m ohm(typ) Iocp(max)=ISEN(min)*Rsen/(1.2*Rds(on)(typ))=36A Iocp=26.34~36A Vref=(Rb/(Rtop+Rbot))*Vo =>0.6=(6.65/(5.11+6.65))*Vo Vo=1.061V 2 7 6 FB NC 1 2 2 PC331 .1U_0402_16V7K FSET EN 9 5 +1.05VS_VTTP 1 1 2 DCR=2.7mΩ(Typ) 3.0mΩ(Max) PL38 1UH_FDUE1040D-1R0M-P3_21.3A_20% 1 2 APW7138NITRL_SSOP16 1 PR465 4.7_1206_5% 1 + PC332 680P_0603_50V7K Rdson=2.3mΩ/3.2mΩ Layout Note: Close IC 單獨拉回不搭Pin15 @ PR471 0_0402_5% 1 2 PC333 390U_2.5V_M 2 C Material Note: 330uF/9 mΩ, number are 3, Power 1, HW 2 +1.05VS_VTTP @ PR473 10_0402_5% 1 2 VTT_SENSE 7 VFB=0.6V PR564 0_0402_5% 1 2 +1.05VS_VTT 1 B PR476 6.49K_0402_1% 2 B Layout Note: Close IC Change PU999 to APW7138 in PVT. @ PR468 10K_0402_5% C 13 PGND 2 PQ95 TPCA8028-H_SOP-ADVANCE8-5 TPCA8028-H_SOP-ADVANCE8-5 LG 1 PC329 2.2U_0603_6.3V6K DL_1.05VS_VTT PQ83 PQ83 TPCA8028-H_SOP-ADVANCE8-5 38 VS_ON 14 PQ82 TPCA8030-H_SOP-ADV8-5 4 1 2 2 6268_VCORE_1.05VS_VTT 4 VCC PR466 57.6K_0402_1% 1 2 PR464 4.7_0603_5% 1 2 6268_VCORE_1.05VS_VTT BOOT PVCC D 2 1 16 UG PHASE PGOOD VIN 2 PR463 0_0603_5% 15 1 2 8 GND PU999 3 1 PC328 0.1U_0603_25V7K +5VS 5 @ PR462 1K_0402_1% 1 2 DH_1.05VS_VTT PR461 BST_1.05VS_VTT 1 2 0_0603_5% 3 2 1 H_VTTPWRGD 5 PGOOD=1V 5 1 2 PC327 10U_1206_25V6M PC326 10U_1206_25V6M 1 2 D +3VS PR458 0_0402_5% 1 2 3 2 1 1 1 1 2 2 JUMP_43X118 PR459 2K_0402_1% 2 B+ A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: 5 4 3 2 Sheet Wednesday, June 30, 2010 1 51 of 56
  • 52.
    5 4 3 2 1 Intel Auburndale CPU(IntegrateGraphics) Ipeak=22A Imax=15A OCP calculation : Assume DCR=1.1m ohm G1=Rn/(Rn+Rsum)=0.617 where Rn=PR277 // (PR274+PH3)=5.875k ohm Rsum=PR269=3.65k ohm LL=2*Rdroop*G1*DCR/Ri= 6.96m V/A where Rdroop=PR271=8.66k ohm, Ri=PR283=1.69k ohm Iocp=OCP Threshold*Rdroop/LL=24.89A B+ D PJ24 1 2 2 UMA@ PC191 0.22U_0402_6.3V6K GFXVR_IMON 8 ISUMBST_GFX 1 1 14 3 2 1 1 2 2 1 1 VID2 VID3 UMA@ PR274 2.61K_0402_1% UMA@ PH3 1 2 1 2 +5VALW UMA@ PC198 2.2U_0603_6.3V6K Rds=4.5mOHM(typ) Rds=5.6mOHM(max) UMA@ PC199 680P_0603_50V7K Layout Note: Place near Choke 1 UMA@ PR270 0_0402_5% + UMA@ PC130 330U_X_2VM_R6M 2 10K_0402_5%_TSM0A103J4302RE 1 2 UMA@ PR277 11K_0402_1% UMA@ PC202 .1U_0402_16V7K 1 2 Material Note: 330uF/6 mΩ, number are 3, PW 1, HW 1, 1 of HW is backup 2 @ PR279 10K_0402_1% UMA@ PR269 3.65K_0805_1% 2 4 2 1 1 4 UMA@ PR273 1 2 0_0603_5% 22 23 VID5 VID4 24 VID6 3 UMA@ PR268 4.7_1206_5% UMA@ PQ41 AO4456_SO8 2 21 UMA@ PQ40 AO4456_SO8 19 20 +VGFX_COREP 5 6 7 8 5 6 7 8 13 IMON 11 9 10 12 VIN VDD RTN BOOT 17 1 UMA@ PC200 150P_0402_50V8J DCR=1.1 mOHM UMA@ PL10 0.45UH_PCMB104T-R45MN_25A_20% 4 1 18 DL_GFX VID1 VR_ON UMA@ PR276 8.06K_0402_1% 2 1 DPRSLPVR UMA@ PC201 22P_0402_50V8J 1 2 CLK_EN# C 4 16 LX_GFX VID0 PGOOD 25 2 UMA@ PR275 17.8K_0402_1% 1 2 1 1 +VGFX_COREP UMA@ PQ39 TPCA8030-H_SOP-ADV8-5 2 15 DH_GFX VCCP RBIAS 26 147K for CPU 47K for GPU UMA@ PC196 100P_0402_50V8J 2 VSSP LGATE 27 2 UMA@ PC197 1000P_0402_50V7K 2 1 VW 3 UGATE UMA@ PU12 ISL62881HRZ-T_QFN28_4X4 PHASE 28 UMA@ PR272 825K_0402_1% 1 2 1 COMP 4 UMA@ PR271 8.66K_0402_1% 2 1 FB 5 UMA@ PR294 2 1 47K_0402_1% VSEN 6 1 UMA@ PC193 0.22U_0603_25V7K 3 2 1 7 ISUM AGND UMA@ PC195 330P_0402_50V7K 1 UMA@ PR293 10_0402_1% ISUM+ UMA@ PC194 330P_0402_50V7K 29 2 8 1 2 8 VCC_AXG_SENSE +VGFX_COREP 2 UMA@ PR266 0_0603_5% 2 8 VSS_AXG_SENSE 5 ISUM+ UMA@ PC192 1000P_0402_50V7K 1 2 C 2 UMA@ PR265 22.6K_0402_1% 3 2 1 UMA@ PR292 2 1 10_0402_1% VSS_AXG_SENSE 1 UMA@ PC189 1U_0402_6.3V6K 2 1 1 1 UMA@ PR263 0_0603_5% UMA@ PR264 1_0603_5% 2 1 2 +5VALW UMA@ PC190 0.22U_0603_25V7K 1 @ PC188 0.1U_0402_25V6 2 1 2 2 GFX_B+ 1 1 UMA@ PC126 10U_1206_25V6M 2 1 2 JUMP_43X118 UMA@ PC125 10U_1206_25V6M 2 1 2 UMA@ PC187 2200P_0402_50V7K D UMA@ PC203 .1U_0402_16V7K 1 2 GFXVR_VID_0 8 GFXVR_VID_1 8 GFXVR_VID_2 8 GFXVR_VID_3 8 GFXVR_VID_4 8 GFXVR_VID_5 8 GFXVR_VID_6 8 GFXVR_EN 8 GFXVR_DPRSLPVR UMA@ PR283 UMA@ PR288 1.69K_0402_1% 82.5_0402_1% 1 2 1 2 UMA@ PC204 0.01U_0402_16V7K 8 ISUM+ 1 2 B @ PR284 100_0402_1% 1 PR280 PR281 PR282 PR285 PR286 PR287 PR289 PR290 PR291 2 UMA@ 1 UMA@ 1 UMA@ 1 UMA@ 1 UMA@ 1 UMA@ 1 UMA@ 1 UMA@ 1 UMA@ 1 1 2 2 2 2 2 2 2 2 2 1 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 2 36 GFX_CORE_PWRGD B @ PC205 180P_0402_50V8J ISUM- @ PR300 1K_0402_1% 2 reduce system idle power +1.05VS_VTTP A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 SCHEMATICS,MB A5893 Document Number Rev C 401869 Sheet Wednesday, June 30, 2010 1 52 of 56
  • 53.
    8 7 6 5 4 3 2 1 +5VS HFM_Icc LL Icc_TDC Auburndale 45W 1.075 50 1.9m 37 35 Auburndale 35W 0.975 38 1.9m 29 27 ClarksfieldSV 0.95 51 1.9m 38 39 Clarksfield XE 0.95 65 TBD 48 TBD 1 PH0 7 H_DPRSLPVR PR565 0_0805_5% H_PSI# CPU_VID6 CPU_VID5 CPU_VID4 CPU_VID3 CPU_VID2 CPU_VID1 CPU_VID0 1 2 1 1 3 +5VS_3212 +5VS_3212 1 7 7 7 7 7 7 7 # of PH 0 2 7 PH1 Icc_Dyn H +CPU_B+ PL39 FBMA-L18-453215-900LMA90T_1812 PR481 10_0603_5% 2 SW2 26 PR515 69.8K_0402_1% 1 2 PC341 10U_1206_25V6M 1 2 2 3 2 1 5 CSREF PL41 0.36UH_ETQP4LR36WFC_24A_20% 4 1 3 2 1 SWFB3 3 2 1 @ PQ93 TPCA8028-H_SOP-ADVANCE8-5 1 4 D PR513 10_0402_5% 1 2 3212_DRVL2 4 3 2 1 PWM3 24 OD3 23 ILIM 21 3212_DRVL2 PR519 2.05K_0402_1% PC359 680P_0603_50V7K @ PQ92 TPCA8028-H_SOP-ADVANCE8-5 2 Place PH1 close to PHASE 1 inductor on the same layer PR523 165K_0402_1% 1 2 2 PH6 100K_0402_1%_NCP15WF104F03RC PH7 100K_0402_1%_NCP15WF104F03RC PC364 1U_0603_16V6K 1 2 2 CSREF PR522 73.2K_0402_1% 2 1 1 PC361 1000P_0402_50V7K PC363 1200P_0402_50V7K 1 2 C 1 PC362 680P_0402_50V7K 2 1 2 PR521 0_0402_5% 2 PR520 1K_0402_1% 2 2 1 1 +CPU_B+ PC360 0.01U_0402_50V7K 3212_SW2 PR512 4.7_1206_5% @ 2 TTSense C @ PQ91 TPCA8030-H_SOP-ADV8-5 PC358 0.1U_0603_25V7K 2 1 2.05K PR517 649K_0402_1% Connect to input caps 22 CSCOMP 20 CSSUM 19 CSREF 18 LLINE 3212_CSCOMP PR514 80.6K_0402_1% 3212_CSCOMP 2 1 PR516 162K_0402_1% 1 17 RT 14 1 2 16 13 1 2 1 3212_VRTT 2 G S BST2 2 PR518 7.32K_0402_1% RPM 1 1 +5VS_3212 D 3 PQ94 2 2N7002W-T/R7_SOT323-3 1 5 H_PROCHOT# 15 AGND RAMP GND 49 PR510 @ 499_0402_1% IREF PR511 0_0402_5% D 25 1 1 4 3 2 1 2 1 12 Avoid high dV/dt 2 2 3212_DRVH2 4 5 TTSNS 3212_DRVH2 PR509 0_0603_5% 2 1 PC339 10U_1206_25V6M 5 3 2 1 5 3 2 1 5 1 3212_DRVH2 +3VS PR508 0_0402_5% 1 5 3212_SW2 27 DRVH2 VRTT PQ90 TPCA8030-H_SOP-ADV8-5 @ PC356 0.1U_0603_25V7K 2 11 3212_CS_PH2 E PC355 10U_1206_25V6M 1 2 10 TTSENSE VARFR 3212_DRVL2 PR506 100_0402_1% 1 2 2 9 3212_VRTT 2 28 +CPU_B+ 30 29 SWFB2 1 8 5.11K_0402_1% TRDET +5VS_3212 PR507 0_0402_5% PGND DRVL2 COMP @ PQ89 TPCA8028-H_SOP-ADVANCE8-5 PC350 4.7U_0603_6.3V6K CSREF 7 PQ88 TPCA8028-H_SOP-ADVANCE8-5 1 E 3212_DRVL1 PC347 680P_0603_50V7K @ 3212_CS_PH2 1 ADP3212MNR2G_QFN48_7X7 +5VS 2 PR503 1.65K_0402_1% 1 2 4 3212_CS_PH1 31 F PR500 10_0402_5% 1 DRVL1 3212_CS_PH1 32 FB 3212_DRVL1 4 +CPU_CORE 3 2 PVCC 2 DCR=1.1m OHM 1 FBRTN 2 PL40 0.36UH_ETQP4LR36WFC_24A_20% 1 4 2 33 G + 1 2 3212_DRVL1 3212_SW1 PR502 100_0402_1% 1 2 1 SWFB1 5 PC353 PR504 150P_0402_50V8J 39.2K_0402_1% 1 2 1 2 2 PR505 5 34 B+ 1 PR499 4.7_1206_5% @ 3212_DRVH1 3 2 1 SW1 PC346 0.1U_0603_25V7K 2 1 PC354 10U_1206_25V6M 36 35 CLKEN 12P_0402_50V8J 3212_FB PC352 6 PC351 150P_0402_50V8J 1 2 @ PQ86 TPCA8030-H_SOP-ADV8-5 PR498 0_0603_5% 2 1 1 4 5 VCC BST1 DRVH1 4 3212_FBRTN 2 3212_DRVH1 4 3 2 1 2 1 38 IMON @ 3212_SW1 2 1 1 PC349 1000P_0402_50V7K CLK_EN# PC348 0.068U_0402_16V7K~N 2 PR501 5.49K_0402_1% PQ87 TPCA8030-H_SOP-ADV8-5 PGND AGND 37 PH1 39 40 PSI PH0 0_0402_5% 1 499_0402_1% 1 PR490 2 41 0_0402_5% 1 PR489 2 VID6 42 0_0402_5% 1 PR488 2 VID5 43 0_0402_5% 1 PR487 2 VID4 44 0_0402_5% 1 PR486 2 VID3 45 0_0402_5% 1 PR485 2 46 0_0402_5% 1 PR484 2 PR491 0_0603_5% 2 1 1 PWRGD 3 IMVP_IMON 2 7 IMVP_IMON PC344 1U_0603_16V6K 3212_DRVH1 EN 2 PR496 0_0402_5% 2 @ 48 1 1 F 2 DPRSLP 1 12,15 VGATE VID2 +1.05VS_VTT VID0 12 CLK_ENABLE# CLK_EN# PR497 0_0402_5% 2 PU27 PR494 2 1 0_0402_5% 1 1 2 PR493 3K_0402_5% 1 PR495 0_0402_5% VID1 2 +3VS PR492 3K_0402_5% PR483 2 +3VS 47 0_0402_5% 1 PR482 2 G PC342 2200P_0402_50V7K 2 1 PC345 0.1U_0603_25V7K 2 1 2 36,38 VR_ON PC343 220U_25V_M HFM_VID H PR524 2 1 2 B PR525 @ PR526 100_0402_1% 2 1 VCCSENSE 3212_CS_PH1 3212_CS_PH2 1 B 130K_0603_1% +CPU_CORE VCCSENSE 7 VSSSENSE 2 130K_0603_1% 1 VSSSENSE 7 1 @ PR527 100_0402_1% A A Compal Secret Data Security Classification 2009/02/04 Issued Date Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 8 7 6 5 4 3 2 Compal Electronics, Inc. SCHEMATICS,MB A5893 Document Number Rev C 401869 Wednesday, June 30, 2010 Sheet 53 1 of 56
  • 54.
    5 4 3 2 Version change list(P.I.R. List) Item D 1 2 3 4 5 6 Fixed Issue Reason for change Modify VGA_COREP circuit Reduce component quantity Modify CPU_COREP circuit Rev. PG# Modify List 1 Page 1 of 1 for PWR Date Change PL9 to SH12036BM00(S COIL .36UH +-20% ETQP4LR36WFC 24A) Phase 2009-1222 PVT D 0.1 50 Arrandale CPU commond design(1 HS, 1LS MOS) 0.1 53 Modify VGA_COREP circuit PVT-2 add N11P-GE1 VGA, change VID setting. 0.2 50 Modify +VSBP circuit Add PC224 for 3VS spike issue 0.2 44 Modify +1.05VS_VTTP circuit Change voltage level from 1.061V to 1.072V. 0.2 51 Change PR476 to SD034649180(S RES 1/16W 6.49K +-1% 0402) 2010-0201 PVT-2 Modify +0.75VSP circuit Change RC for HW timing.(S3 shutdown issue) 0.2 48 Change PR409 to SD034280280(S RES 1/16W 28K +1% 0402) 2010-0201 PVT-2 Change PC287 to SE076104K80(S CER CAP .1U 16V K X7R 0402) Change PQ89/PQ93 SB00000GL00(S TR TPCA8028-H 1N SOP ADVANCE) BOM structure to @ Change PR136/PR138 BOM structure to GV2H@ Change PR137/139/141/143/147/149, PC110 and PQ38/76 BOM structure to GE1@ 2009-1222 PVT add PC224 to SE000000K80(S CER CAP 1U 6.3V K X5R 0402) 2010-0113 PVT-2 2010-0113 PVT-2 7 C 8 C 9 10 11 12 13 14 B 15 B 16 17 18 19 20 21 22 A A 23 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 54 of 56
  • 55.
    5 4 3 2 1 A -->Modify item D D C C B B A A IssuedDate Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS,MB A5893 Rev C 401869 Date: 5 4 3 2 Wednesday, June 30, 2010 Sheet 1 55 of 56
  • 56.
    A B C D E BOM Config PEW71 SKUN11P-GE DISCRETE ONLY without 3G BT@,DIS@,DIS ONLY@,NonSG@,71@,X7621@,GE@,NonOPT@ 431869BOL21 PEW71 SKU N11P-GV2H-A3 DISCTETE ONLY without 3G 1 BT@,DIS@,DIS ONLY@,NonSG@,71@,X7621@,GV2H@,GV2HA3@,NonOPT@,NonGE@ 431869BOL22 1 2 2 3 3 PCB GV2HA2@ GV2HA3@ GE1@ GE@ ZZZ U51 U51 U51 U51 LA-5893P REV0 M/B N11P-GV2H-A2_BGA969 N11P-GV2H-A3_BGA969 N11P-GE1-A3 BGA 969P N11P-GE-A1 BGA 969P ZZZ2 ZZZ1 X7622@ X76198BOL22 4 ALT. GROUP PARTS 2G HYN X7621@ X76198BOL21 ALT. GROUP PARTS 1G HYN 4 ALT. GROUP PARTS 1G SAM Compal Electronics, Inc. Compal Secret Data Security Classification 2008/08/10 Issued Date Deciphered Date 2010/08/01 Title SCHEMATICS,MB A5893 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C 401869 Date: A B C D Wednesday, June 30, 2010 Sheet E 56 of 56