This document describes the architecture of a processor that includes multiple functional units like a bulk memory, working stores, data transfer, control units, an I/O selector, floating point multiplier and reciprocal units, arithmetic controllers, floating point adders, and a sine/cosine pipeline for processing angles. The processor also interfaces with a host computer through an I/O channel and is controlled by a microprogram.

1. BulkMemory
Working
Store(right)
Working
Store(left)
Data Transfer
Control
Control
Processor
I/O
Selector
Floating
Point
Multiplier(4
-stage
Pipeline)
Reciprocal(5 Stages)
Arithmetic unit
controller
Writable control
stage
FLP Adder
(4 Stages)
FLP Adder
(4 Stages)
Sin/Cos in
pipeline
(3 stages)
Address
Angles
Microprogram
Control
I/O Channel(To host Computer)
Data(4-Stage Pipe)