Autonomous 4 Axis Planar Manipulator Robot for Grapping stuff at offline market.
This is made of gradient based path-planning and Odometry using matlab bluetooth communication and arduino spi internal communication
Autonomous 4 Axis Planar Manipulator Robot for Grapping stuff at offline market.
This is made of gradient based path-planning and Odometry using matlab bluetooth communication and arduino spi internal communication
The document discusses different methods for representing numeric data in binary form, including binary, decimal, hexadecimal, and octal number systems. It explains how binary numbers are used to represent data in computers and how different data types can be converted between number bases through translation. Key concepts covered include binary digits (bits), bytes, signed and unsigned integer representation, and binary arithmetic operations.
11. Steps of a machine cycle
The CPU uses repeating
machine cycles to
execute instructions in
the program, one by one,
from beginning to end.
A simplified cycle can
consist of three steps:
fetch, decode, and
execute.
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Example: adding two integers
Contents of memory and register before execution
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12. PC（Program Counter，程式計數器）
：用於存放下一條要執行的指令的地址。
I（Instruction Register，指令暫存器）
：暫存目前執行的指令。
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Example: first operation
Contents of memory and registers after first operation
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13. Example: second operation
Contents of memory and registers after second operation
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Example: third operation
Contents of memory and registers after third operation
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14. Example: fourth operation
Contents of memory and registers after fourth operation
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生產線技術(pipelining)
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17. Note:
Memory addresses are defined using
unsigned binary integers.
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Example
A computer has 128 MB of memory. Each word
in this computer is 8 bytes. How many bits are
needed to address any single word in memory?
Solution
The memory address space is 128 MB, which
means 227. However, each word is 8 (23) bytes,
which means that you have 224 words. This
means you need log2 224 or 24 bits, to address
each word.
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18. 記憶體的容量、速度與價位
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Memory hierarchy
Small amount of high-speed memory: register
Moderate amount of medium-speed memory: cache
memory
Large amount of low-speed memory: main memory.
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22. 靜態隨機存取記憶體
快取記憶體可加速系統效能
一般我們所用的主記憶體(DRAM)的速度較慢，所以在
CPU和DRAM之間會多了一個速度較快的快取記憶體
(cache memory)，用快取記憶體取代主記憶體的角色，
可加快CPU的處理速度
快取記憶體也可存放一些CPU常會用到的程式或資料，
所以CPU要資料時，先向快取記憶體要資料，如果要不
到才會向DRAM要資料。
儲存經常使用的資料或指令
Cache DRAM
速度快
CPU 備份
速度慢
儲存一般使用的資料或指令
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Cache
Cache memory is placed between the CPU and main memory.
At any time cache memory contains a copy of a portion of main
memory.
80-20 rule: It has been observed that most computers typically
spend 80% of the time accessing only 20% of the data. Cache
memory can hold this 20% data to make access faster at least
80 % of the time.
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23. 動態隨機存取記憶體
架構和特性
動態隨機存取記憶體(Dynamic Random Access Memory,
DRAM)相對於靜態隨機存取記憶體(SRAM)的特性為存取速
度較慢(60-70ns以上)、成本較低
DRAM可隨時寫入或讀出資料，關閉電源時，存放在RAM的
內容會消失，不可永久保存資料。電腦系統的DRAM容量
可擴充
D RAM
速度快 全部載入
完整的程式 A
CPU
硬碟
部份的程式 B
速度慢 程式 A
程式 B
切換
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記憶體和儲存媒體比較
在個人電腦會使用到ROM、SRAM、DRAM和輔助記憶體
等四種，一般是比較四者的單位價格、容量和速
單位價格：ROM > SRAM > DRAM > 輔助記憶體
容 量：ROM < SRAM < DRAM < 輔助記憶體
速 度：ROM > SRAM > DRAM > 輔助記憶體
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25. Connecting I/O devices to the buses
A controller handles the I/O operations between the
CPU/memory and the much slower I/O devices.
FireWire and USB are common controllers.
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USB
USB（Universal Serial Bus；通用序列匯流排）
針對電腦的外接週邊設備（鍵盤、滑鼠、遊戲控
制器、攝影機、儲存裝置、掃描器和其他周邊）
所設計，讓使用者安裝特定裝置時，能夠省去開
啟電腦機箱及重開機的麻煩，隨插即用，為一般
使用者提供了操作簡便、擴充性和快速等優點
USB 2.0傳輸速度最高每秒可達480MB（早期版本
USB 1.0每秒1.5MB；USB 1.1每秒12MB）
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27. Isolated I/O addressing
There are two methods to handle the addressing of I/O devices:
isolated I/O and memory-mapped I/O
The instructions used to read/write memory are different from
the instructions used to read/write input/output device
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Memory-mapped I/O addressing
CPU treats each register in the input/output controller as a
word in memory. In other words, CPU does not have separate
instructions for transferring data from memory or input/output
device
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28. Programmed I/O
When the CPU encounters an
I/O instruction, it waits for the
I/O device and does nothing
else until the data transfer is
complete.
The CPU constantly checks the
status of the I/O device until the
I/O device is ready.
The big issue is that the CPU
time is wasted by checking the
status of the I/O device.
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Interrupt-driven I/O
The CPU informs the I/O
device that a data transfer is
going to happen, but it does
not test the status of the I/O
device continuously. The
I/O device informs
(interrupts) the CPU when
it is ready. During the time,
the CPU cab do other jobs.
The CPU time is wasted.
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30. Direct Memory Access (DMA)
DMA transfers a large block of data between a high speed I/O
device, such as a disk, and memory directly.
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輸出入周邊設備
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