2. Test Bench
module alu_8bit_sagartb_v;
// Inputs
reg [7:0] x;
reg [7:0] y;
reg [3:0] ctrl;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
alu_8bit_sagar uut (
.x(x),
.y(y),
.ctrl(ctrl),
.out(out)
);
initial begin
// Initialize Inputs
x = 25;
y = 20;
ctrl = 0;
#2
repeat(16)
begin
#2
ctrl=ctrl+1;
end
#50 $stop;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule