KTN ran a collaborators' workshop on 26 September 2019 in London to explain more about the Digital Security by Design Challenge announced by the government. The Digital Security by Design challenge has been recently announced by the Department for Business, Energy & Industrial Strategy (BEIS). This challenge, amounting to £70 million of government funding over 5 years, was delivered by UK Research and Innovation (UKRI) through the Industrial Strategy Challenge Fund (ISCF). This Collaborators' Workshop provides an opportunity to hear more details of the challenge and forthcoming competitions. A Scoping Workshop for this challenge was held on 30th May: http://ow.ly/oz6230pHlGl Find out more about the Defence and Security Interest Group at https://ktn-uk.co.uk/interests/defence-security Join the Defence and Security Interest Group at https://www.linkedin.com/groups/8584397 or Follow KTN_UK Defence group on Twitter https://twitter.com/KTNUK_Defence

1. Designing cybersecurity in at the
bottom: embedding it into the chip
below the OS!
October 2019
Aileen Ryan
Aileen.ryan@ultrasoc.com
www.ultrasoc.com
@UltraSoC

2. Electronic systems in vehicles today are becoming
dangerously complex…
October 2019 2Confidential
UltraSoC ensures systems do what they are supposed to do
Cost of automotive recalls
expected to reach $20Bn by
2023
High risk to civilian and
national defense applications
Insurers calling for clarity on “who is
responsible for securing connected
devices” – owner, vendor, system
integrator, component designer etc.

3. We solve the problem of systemic complexity
3
TE
Message Infrastructure
DRAM
Controller
LCD
Controller
GPIO
LockStep
BM
Analytics
Subsys
USB 2.0
Hub Communicator
PHY
DMA
Security
Subsys
Status
Mon
SRAM
System Interconnect (AXI)
UtraSoc Component
RISCV RISCV
JTAG
AXI
Mon
1 0 1 0
LockStep
SM JPAMBPAM
PHY
APB
AXI
Guard
Peripherals
System
Buffer
TE
ARC
Bus Filter
Gateway
Message Lock
Knowledge
Information
Data
UltraSoC delivers
actionable insights
With system-wide
understanding
From rich data
across the
whole SoC
UltraSoC enables full visibility of SoC
Value
October 2019 Confidential
UltraSoC monitors are designed into
the chip, gathering data:
- from the entire system
- in real time
- without perturbing normal performance
We provide unparalleled insight into
what’s happening inside the chip to
inform decision making, enabling:
- faster time to market, higher quality levels and
greater profitability
- better, more rapid decisions, critical for
security and safety applications
- focused information to ensure performance is
optimized

4. Examples of what can be achieved
Commercial in Confidence
HW “stuck pixel” detect Rule-based attack detect
Hashing implemented in
HW
- Detection time is
microseconds rather
than milliseconds!
“Learned” HW-based
attack detect
Anomaly detection against
“learned” behavioral signature
- Normal latency differs
across CPUs
- Deviations could indicate
DDOS or other interference
Anomaly detection against pre-
defined rules
- Thread switching time falls
outside accepted period
- Could indicate DDOS,
Ransom or other
interference
October 2019

5. • The world’s first on-chip monitoring solution to rapidly detect cyber security threats in
Connected and Autonomous Vehicles (CAVs) – and potentially beyond that, to wider IoT
• This will ensure in-vehicle systems function as they were designed and intelligently
protect citizens and infrastructure
July 2019 £2M InnovateUK Grant Award
5Commercial in Confidence
UltraSoC roadmap items include:
- Analytics sub-system – on-chip platform ML algorithms
and code will run on
- Bus Guardian – filter and “smart” response to detected
events and transactions
- Lockstep Manager – check that redundant systems are
functioning correctly for *any* systems
- Forensic Trace – cycle-accurate record of what has
happened on-chip (on chip “black box”)
October 2019