The document discusses different types of single-bit adders and multi-bit adders built from them. It describes half adders, full adders, ripple carry adders and their delay properties. It then discusses different advanced adder circuits like carry lookahead adders, carry skip adders, carry select adders and carry save adders to reduce the delay. Verilog code examples are provided for full adders, ripple carry adders, carry lookahead adders and carry skip adders.
3. Full Adder
Computes one-bit sum, carry
si = ai XOR bi XOR ci
ci+1 = aibi + aici + bici
Adder delay is dominated by carry chain
Ripple-carry adder: n-bit adder built from full adders.
Delay of ripple-carry adder goes through all carry bits
Ripple carry adder delay is propotional to no of stages, in worst case it goes to thru all the stages.
A clacan reduce the delay. In principle the delay can be reduced so that it is proportional to logn, but for large numbers this is no longer the case, because even when carry look-ahead is implemented, the distances that signals have to travel on the chip increase in proportion to n, and propagation delays increase at the same rate .
If the adder is required to add two numbers and produce a result, carry-save addition is useless, since the result still has to be converted back into binary and this still means that carries have to propagate from right to left. But in large-integer arithmetic, addition is a very rare operation, and adders are mostly used to accumulate partial sums in a multiplication. 0 or 1, from the number we are adding.0 if the digit in our store is 0 or 2, or 1 if it is 1 or 3.0 if the digit to its right is 0 or 1, or 1 if it is 2 or 3.