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Main Memory (Part I)
Amir H. Payberah
amir@sics.se
Amirkabir University of Technology
(Tehran Polytechnic)
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 1 / 47
Motivation and Background
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Motivation
Main memory is a large array of bytes, each with its own address.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 3 / 47
Motivation
Main memory is a large array of bytes, each with its own address.
Program must be brought (from disk) into memory and placed
within a process for it to be run.
• Machine instructions may take memory addresses as arguments, but
not disk addresses.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 3 / 47
Motivation
Main memory is a large array of bytes, each with its own address.
Program must be brought (from disk) into memory and placed
within a process for it to be run.
• Machine instructions may take memory addresses as arguments, but
not disk addresses.
The CPU fetches instructions from memory according to the value
of the program counter.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 3 / 47
Motivation
Main memory is a large array of bytes, each with its own address.
Program must be brought (from disk) into memory and placed
within a process for it to be run.
• Machine instructions may take memory addresses as arguments, but
not disk addresses.
The CPU fetches instructions from memory according to the value
of the program counter.
These instructions may cause additional loading from and storing to
specific memory addresses.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 3 / 47
Basic Hardware
Main memory and registers are the only storage that the CPU can
access directly.
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Basic Hardware
Main memory and registers are the only storage that the CPU can
access directly.
Register access in one CPU clock (or less)
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 4 / 47
Basic Hardware
Main memory and registers are the only storage that the CPU can
access directly.
Register access in one CPU clock (or less)
Main memory can take many cycles, causing a stall.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 4 / 47
Basic Hardware
Main memory and registers are the only storage that the CPU can
access directly.
Register access in one CPU clock (or less)
Main memory can take many cycles, causing a stall.
Cache sits between main memory and registers.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 4 / 47
Address Protection
We must protect the OS from access by user processes.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 5 / 47
Address Protection
We must protect the OS from access by user processes.
We must protect user processes from one another.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 5 / 47
Address Protection
We must protect the OS from access by user processes.
We must protect user processes from one another.
This protection is provided by the hardware.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 5 / 47
Address Protection
We must protect the OS from access by user processes.
We must protect user processes from one another.
This protection is provided by the hardware.
A separate memory space for each process.
• Determining the range of legal addresses that the process may
access.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 5 / 47
Base and Limit Registers
A pair of base and limit registers
define the logical address space.
CPU must check every memory
access generated in user mode to
be sure it is between base and limit
for that user.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 6 / 47
Hardware Address Protection
Any attempt by a user program to access OS memory or other
users’ memory results in a trap to the OS, which treats the
attempt as a fatal error.
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Address Binding
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 8 / 47
Address Binding (1/2)
Programs on disk, ready to be brought into memory to execute
form an input queue.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 9 / 47
Address Binding (1/2)
Programs on disk, ready to be brought into memory to execute
form an input queue.
A user process can reside in any part of the physical memory.
• Without support, must be loaded into address 00000.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 9 / 47
Address Binding (2/2)
A user program goes through several steps before being executed.
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Address Binding (2/2)
A user program goes through several steps before being executed.
Addresses may be represented in different ways during these steps.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 10 / 47
Address Binding (2/2)
A user program goes through several steps before being executed.
Addresses may be represented in different ways during these steps.
• Source code addresses usually symbolic.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 10 / 47
Address Binding (2/2)
A user program goes through several steps before being executed.
Addresses may be represented in different ways during these steps.
• Source code addresses usually symbolic.
• A compiler typically binds these symbolic addresses to relocatable
addresses, e.g., 14 bytes from beginning of this module.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 10 / 47
Address Binding (2/2)
A user program goes through several steps before being executed.
Addresses may be represented in different ways during these steps.
• Source code addresses usually symbolic.
• A compiler typically binds these symbolic addresses to relocatable
addresses, e.g., 14 bytes from beginning of this module.
• Linker or loader will bind relocatable addresses to absolute
addresses, e.g., 74014.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 10 / 47
Binding of Instructions and Data to Memory (1/3)
Address binding of instructions and data
to memory addresses can happen at three
different stages.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 11 / 47
Binding of Instructions and Data to Memory (1/3)
Address binding of instructions and data
to memory addresses can happen at three
different stages.
Compile time: if memory location known
a priori, absolute code can be generated.
• Must recompile code if starting location
changes.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 11 / 47
Binding of Instructions and Data to Memory (2/3)
Load time: must generate relocatable code
if memory location is not known at compile
time.
• Final binding is delayed until load time.
• If the starting address changes, we need
only reload the user code to incorporate
this changed value.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 12 / 47
Binding of Instructions and Data to Memory (3/3)
Execution time: binding delayed until
run time if the process can be moved
during its execution from one memory
segment to another.
• Need hardware support
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 13 / 47
Logical vs. Physical Address Space (1/2)
Logical address (virtual address): address generated by the CPU.
• Logical address space is the set of all logical addresses generated by
a program.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 14 / 47
Logical vs. Physical Address Space (1/2)
Logical address (virtual address): address generated by the CPU.
• Logical address space is the set of all logical addresses generated by
a program.
Physical address: address seen by the memory unit.
• Physical address space is the set of all physical addresses generated
by a program.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 14 / 47
Logical vs. Physical Address Space (1/2)
Logical address (virtual address): address generated by the CPU.
• Logical address space is the set of all logical addresses generated by
a program.
Physical address: address seen by the memory unit.
• Physical address space is the set of all physical addresses generated
by a program.
The concept of a logical address space that is bound to a separate
physical address space is central to proper memory management.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 14 / 47
Logical vs. Physical Address Space (2/2)
Logical and physical addresses are the same in compile-time and
load-time address-binding schemes.
Logical and physical addresses differ in execution-time
address-binding scheme.
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Memory-Management Unit (MMU) (1/2)
Hardware device that at run time maps virtual to physical address.
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Memory-Management Unit (MMU) (1/2)
Hardware device that at run time maps virtual to physical address.
As a simple scheme, the value in the relocation register is added to
every address generated by a user process at the time it is sent to
memory.
• Base register now called relocation register.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 16 / 47
Memory-Management Unit (MMU) (2/2)
Two different types of addresses:
• Logical addresses: range 0 to max
• Physical addresses: range R + 0 to R + max for a base value R
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 17 / 47
Memory-Management Unit (MMU) (2/2)
Two different types of addresses:
• Logical addresses: range 0 to max
• Physical addresses: range R + 0 to R + max for a base value R
The user program generates only logical addresses and thinks that
the process runs in locations 0 to max.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 17 / 47
Memory-Management Unit (MMU) (2/2)
Two different types of addresses:
• Logical addresses: range 0 to max
• Physical addresses: range R + 0 to R + max for a base value R
The user program generates only logical addresses and thinks that
the process runs in locations 0 to max.
These logical addresses must be mapped to physical addresses
before they are used.
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Dynamic Linking and Loading
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Dynamic Loading (1/2)
Routine/library is not loaded until it is called.
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Dynamic Loading (1/2)
Routine/library is not loaded until it is called.
The main program is loaded into memory and is executed.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 19 / 47
Dynamic Loading (1/2)
Routine/library is not loaded until it is called.
The main program is loaded into memory and is executed.
When a routine is needed, if it has not been loaded, the loader
loads the desired routine into memory and to update the program’s
address tables to reflect this change.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 19 / 47
Dynamic Loading (1/2)
Routine/library is not loaded until it is called.
The main program is loaded into memory and is executed.
When a routine is needed, if it has not been loaded, the loader
loads the desired routine into memory and to update the program’s
address tables to reflect this change.
Then control is passed to the newly loaded routine.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 19 / 47
Dynamic Loading (1/2)
Routine/library is not loaded until it is called.
The main program is loaded into memory and is executed.
When a routine is needed, if it has not been loaded, the loader
loads the desired routine into memory and to update the program’s
address tables to reflect this change.
Then control is passed to the newly loaded routine.
All routines kept on disk in relocatable load format.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 19 / 47
Dynamic Loading (2/2)
Better memory-space utilization; unused routine is never loaded.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 20 / 47
Dynamic Loading (2/2)
Better memory-space utilization; unused routine is never loaded.
Useful when large amounts of code are needed to handle
infrequently occurring cases.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 20 / 47
Dynamic Loading (2/2)
Better memory-space utilization; unused routine is never loaded.
Useful when large amounts of code are needed to handle
infrequently occurring cases.
No special support from the OS is required.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 20 / 47
Dynamic Loading (2/2)
Better memory-space utilization; unused routine is never loaded.
Useful when large amounts of code are needed to handle
infrequently occurring cases.
No special support from the OS is required.
Implemented through program design.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 20 / 47
Dynamic Loading (2/2)
Better memory-space utilization; unused routine is never loaded.
Useful when large amounts of code are needed to handle
infrequently occurring cases.
No special support from the OS is required.
Implemented through program design.
OS can help by providing libraries to implement dynamic loading.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 20 / 47
Dynamic Liking (1/2)
Static linking: system libraries and program code combined by the
loader into the binary program image.
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Dynamic Liking (1/2)
Static linking: system libraries and program code combined by the
loader into the binary program image.
Dynamic linking: linking postponed until execution time.
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Dynamic Liking (1/2)
Static linking: system libraries and program code combined by the
loader into the binary program image.
Dynamic linking: linking postponed until execution time.
Stub: small piece of code, used to locate the appropriate
memory-resident library routine.
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Dynamic Liking (1/2)
Static linking: system libraries and program code combined by the
loader into the binary program image.
Dynamic linking: linking postponed until execution time.
Stub: small piece of code, used to locate the appropriate
memory-resident library routine.
Stub replaces itself with the address of the routine, and executes
the routine.
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Dynamic Liking (2/2)
OS checks if routine is in processes memory address.
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Dynamic Liking (2/2)
OS checks if routine is in processes memory address.
If not in address space, add to address space.
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Dynamic Liking (2/2)
OS checks if routine is in processes memory address.
If not in address space, add to address space.
Dynamic linking is particularly useful for shared libraries.
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Swapping
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Swapping (1/3)
A process can be swapped temporarily out of memory to a backing
store, and then brought back into memory for continued execution.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 24 / 47
Swapping (1/3)
A process can be swapped temporarily out of memory to a backing
store, and then brought back into memory for continued execution.
Backing store: fast disk large enough to accommodate copies of all
memory images for all users; must provide direct access to these
memory images.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 24 / 47
Swapping (1/3)
A process can be swapped temporarily out of memory to a backing
store, and then brought back into memory for continued execution.
Backing store: fast disk large enough to accommodate copies of all
memory images for all users; must provide direct access to these
memory images.
Total memory space of processes can exceed physical memory.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 24 / 47
Swapping (2/3)
Does the swapped out process need to swap back in to same
physical addresses?
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 25 / 47
Swapping (2/3)
Does the swapped out process need to swap back in to same
physical addresses?
• Depends on address binding method.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 25 / 47
Swapping (2/3)
Does the swapped out process need to swap back in to same
physical addresses?
• Depends on address binding method.
Pending I/O: cannot swap out as I/O would occur to wrong
process.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 25 / 47
Swapping (2/3)
Does the swapped out process need to swap back in to same
physical addresses?
• Depends on address binding method.
Pending I/O: cannot swap out as I/O would occur to wrong
process.
• Or always transfer I/O to kernel space, then to I/O device.
• Known as double buffering, adds overhead.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 25 / 47
Swapping (3/3)
Standard swapping not used in modern OSs, but modified version
is common.
Swap only when free memory extremely low.
Disabled again once memory demand reduced below threshold.
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Swapping Cost
Major part of swap time is transfer time; which is proportional to
the amount of memory swapped.
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Swapping Cost
Major part of swap time is transfer time; which is proportional to
the amount of memory swapped.
If next processes to be put on CPU is not in memory, need to swap
out a process and swap in target process.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 27 / 47
Swapping Cost
Major part of swap time is transfer time; which is proportional to
the amount of memory swapped.
If next processes to be put on CPU is not in memory, need to swap
out a process and swap in target process.
Example:
• 100MB process swapping to hard disk with transfer rate of
50MB/sec.
• Swap out time of 2s + swap in of same sized process.
• Total context switch swapping component time of 4s.
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Swapping on Mobile Systems (1/2)
Not typically supported.
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Swapping on Mobile Systems (1/2)
Not typically supported.
Flash memory based
• Small amount of space
• Limited number of write cycles
• Poor throughput between flash memory and CPU on mobile
platform
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Swapping on Mobile Systems (2/2)
Instead use other methods to free memory if low.
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Swapping on Mobile Systems (2/2)
Instead use other methods to free memory if low.
iOS asks apps to voluntarily relinquish allocated memory.
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Swapping on Mobile Systems (2/2)
Instead use other methods to free memory if low.
iOS asks apps to voluntarily relinquish allocated memory.
Read-only data thrown out and reloaded from flash if needed.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 29 / 47
Swapping on Mobile Systems (2/2)
Instead use other methods to free memory if low.
iOS asks apps to voluntarily relinquish allocated memory.
Read-only data thrown out and reloaded from flash if needed.
Failure to free can result in termination.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 29 / 47
Swapping on Mobile Systems (2/2)
Instead use other methods to free memory if low.
iOS asks apps to voluntarily relinquish allocated memory.
Read-only data thrown out and reloaded from flash if needed.
Failure to free can result in termination.
Android terminates apps if low free memory, but first writes
application state to flash for fast restart.
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Contiguous Memory Allocation
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Contiguous Allocation (1/2)
Main memory must support both OS and user processes.
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Contiguous Allocation (1/2)
Main memory must support both OS and user processes.
Limited resource, must allocate efficiently.
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Contiguous Allocation (1/2)
Main memory must support both OS and user processes.
Limited resource, must allocate efficiently.
Contiguous allocation is one early method.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 31 / 47
Contiguous Allocation (1/2)
Main memory must support both OS and user processes.
Limited resource, must allocate efficiently.
Contiguous allocation is one early method.
Main memory usually into two partitions:
• Resident OS, usually held in low memory with interrupt vector.
• User processes then held in high memory.
• Each process contained in single contiguous section of memory.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 31 / 47
Contiguous Allocation (2/2)
Relocation registers used to protect user processes from each
other, and from changing OS code and data.
• Base register contains value of smallest physical address.
• Limit register contains range of logical addresses.
• MMU maps logical address dynamically.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 32 / 47
Multiple-Partition Allocation (1/2)
Memory is to divide memory into several fixed-sized partitions.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 33 / 47
Multiple-Partition Allocation (1/2)
Memory is to divide memory into several fixed-sized partitions.
Each partition may contain exactly one process.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 33 / 47
Multiple-Partition Allocation (1/2)
Memory is to divide memory into several fixed-sized partitions.
Each partition may contain exactly one process.
Degree of multiprogramming limited by number of partitions.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 33 / 47
Multiple-Partition Allocation (1/2)
Memory is to divide memory into several fixed-sized partitions.
Each partition may contain exactly one process.
Degree of multiprogramming limited by number of partitions.
When a partition is free, a process is selected from the input queue
and is loaded into the free partition.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 33 / 47
Multiple-Partition Allocation (2/2)
Variable-partition sizes for efficiency (sized to a given process’
needs).
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 34 / 47
Multiple-Partition Allocation (2/2)
Variable-partition sizes for efficiency (sized to a given process’
needs).
Hole: block of available memory.
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Multiple-Partition Allocation (2/2)
Variable-partition sizes for efficiency (sized to a given process’
needs).
Hole: block of available memory.
When a process arrives, it is allocated memory from a hole large
enough to accommodate it.
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Multiple-Partition Allocation (2/2)
Variable-partition sizes for efficiency (sized to a given process’
needs).
Hole: block of available memory.
When a process arrives, it is allocated memory from a hole large
enough to accommodate it.
Process exiting frees its partition, adjacent free partitions combined
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 34 / 47
Multiple-Partition Allocation (2/2)
Variable-partition sizes for efficiency (sized to a given process’
needs).
Hole: block of available memory.
When a process arrives, it is allocated memory from a hole large
enough to accommodate it.
Process exiting frees its partition, adjacent free partitions combined
OS maintains information about: allocated partitions and free
partitions (hole)
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 34 / 47
Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 35 / 47
Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?
First-fit: allocate the first hole that is big enough
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 35 / 47
Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?
First-fit: allocate the first hole that is big enough
Best-fit: allocate the smallest hole that is big enough
• Must search entire list, unless ordered by size.
• Produces the smallest leftover hole.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 35 / 47
Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?
First-fit: allocate the first hole that is big enough
Best-fit: allocate the smallest hole that is big enough
• Must search entire list, unless ordered by size.
• Produces the smallest leftover hole.
Worst-fit: allocate the largest hole
• Must also search entire list.
• Produces the largest leftover hole.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 35 / 47
Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?
First-fit: allocate the first hole that is big enough
Best-fit: allocate the smallest hole that is big enough
• Must search entire list, unless ordered by size.
• Produces the smallest leftover hole.
Worst-fit: allocate the largest hole
• Must also search entire list.
• Produces the largest leftover hole.
First-fit and best-fit better than worst-fit in terms of speed and
storage utilization.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 35 / 47
Fragmentation (1/3)
External fragmentation: total memory space exists to satisfy a
request, but it is not contiguous.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 36 / 47
Fragmentation (1/3)
External fragmentation: total memory space exists to satisfy a
request, but it is not contiguous.
Internal fragmentation: allocated memory may be slightly larger
than requested memory; this size difference is memory internal to a
partition, but not being used.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 36 / 47
Fragmentation (1/3)
External fragmentation: total memory space exists to satisfy a
request, but it is not contiguous.
Internal fragmentation: allocated memory may be slightly larger
than requested memory; this size difference is memory internal to a
partition, but not being used.
First fit analysis reveals that given N blocks allocated, 0.5N blocks
lost to fragmentation: 50-percent rule
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 36 / 47
Fragmentation (2/3)
Compaction: a solution to the problem of external fragmentation.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 37 / 47
Fragmentation (2/3)
Compaction: a solution to the problem of external fragmentation.
Shuffle memory contents to place all free memory together in one
large block.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 37 / 47
Fragmentation (2/3)
Compaction: a solution to the problem of external fragmentation.
Shuffle memory contents to place all free memory together in one
large block.
Compaction is possible only if relocation is dynamic, and is done at
execution time.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 37 / 47
Fragmentation (2/3)
Compaction: a solution to the problem of external fragmentation.
Shuffle memory contents to place all free memory together in one
large block.
Compaction is possible only if relocation is dynamic, and is done at
execution time.
I/O problem
• Latch job in memory while it is involved in I/O
• Do I/O only into OS buffers.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 37 / 47
Fragmentation (3/3)
Another possible solution to the external fragmentation problem:
permit the logical address space of the processes to be
noncontiguous.
Two techniques:
• Segmentation
• Paging
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 38 / 47
Segmentation
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 39 / 47
Fragmentation (2/2)
Memory-management scheme that supports user view of memory.
A program is a collection of segments.
A segment is a logical unit such as:
• Main program
• Procedure
• Function
• Object
• ...
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 40 / 47
Logical View of Segmentation
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 41 / 47
Segmentation Architecture
Logical address consists of a tuple: segment number, offset
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 42 / 47
Segmentation Architecture
Logical address consists of a tuple: segment number, offset
Segment table: maps two-dimensional user-defined addresses into
one-dimensional physical address.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 42 / 47
Segmentation Architecture
Logical address consists of a tuple: segment number, offset
Segment table: maps two-dimensional user-defined addresses into
one-dimensional physical address.
Each table entry has:
• Base: contains the starting physical address where the segments
reside in memory
• Limit: specifies the length of the segment
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 42 / 47
Segmentation Hardware
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 43 / 47
Segmentation Example
A reference to byte 53 of segment 2:
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 44 / 47
Segmentation Example
A reference to byte 53 of segment 2: 4300 + 53 = 4353
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 44 / 47
Segmentation Example
A reference to byte 53 of segment 2: 4300 + 53 = 4353
A reference to byte 852 of segment 3:
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 44 / 47
Segmentation Example
A reference to byte 53 of segment 2: 4300 + 53 = 4353
A reference to byte 852 of segment 3: 3200 + 852 = 4052
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 44 / 47
Segmentation Example
A reference to byte 53 of segment 2: 4300 + 53 = 4353
A reference to byte 852 of segment 3: 3200 + 852 = 4052
A reference to byte 1222 of segment 0:
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 44 / 47
Segmentation Example
A reference to byte 53 of segment 2: 4300 + 53 = 4353
A reference to byte 852 of segment 3: 3200 + 852 = 4052
A reference to byte 1222 of segment 0: trap to OS
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 44 / 47
Summary
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 45 / 47
Summary
Main memory
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
Summary
Main memory
Address protection: base + limit
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
Summary
Main memory
Address protection: base + limit
Address binding: compile time, load time, execution time
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
Summary
Main memory
Address protection: base + limit
Address binding: compile time, load time, execution time
Logical and physical address, MMU
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
Summary
Main memory
Address protection: base + limit
Address binding: compile time, load time, execution time
Logical and physical address, MMU
Swapping: backing store, swapping cost
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
Summary
Main memory
Address protection: base + limit
Address binding: compile time, load time, execution time
Logical and physical address, MMU
Swapping: backing store, swapping cost
Contiguous memory allocation: partitions, holes, first-fit, best-fit,
worst-fit
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
Summary
Main memory
Address protection: base + limit
Address binding: compile time, load time, execution time
Logical and physical address, MMU
Swapping: backing store, swapping cost
Contiguous memory allocation: partitions, holes, first-fit, best-fit,
worst-fit
External and internal fragmentation: compaction, segmentation,
paging
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
Summary
Main memory
Address protection: base + limit
Address binding: compile time, load time, execution time
Logical and physical address, MMU
Swapping: backing store, swapping cost
Contiguous memory allocation: partitions, holes, first-fit, best-fit,
worst-fit
External and internal fragmentation: compaction, segmentation,
paging
Segmentation: noncontiguous address, user view of memory
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
Questions?
Acknowledgements
Some slides were derived from Avi Silberschatz slides.
Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 47 / 47

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Main Memory - Part1

  • 1. Main Memory (Part I) Amir H. Payberah amir@sics.se Amirkabir University of Technology (Tehran Polytechnic) Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 1 / 47
  • 2. Motivation and Background Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 2 / 47
  • 3. Motivation Main memory is a large array of bytes, each with its own address. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 3 / 47
  • 4. Motivation Main memory is a large array of bytes, each with its own address. Program must be brought (from disk) into memory and placed within a process for it to be run. • Machine instructions may take memory addresses as arguments, but not disk addresses. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 3 / 47
  • 5. Motivation Main memory is a large array of bytes, each with its own address. Program must be brought (from disk) into memory and placed within a process for it to be run. • Machine instructions may take memory addresses as arguments, but not disk addresses. The CPU fetches instructions from memory according to the value of the program counter. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 3 / 47
  • 6. Motivation Main memory is a large array of bytes, each with its own address. Program must be brought (from disk) into memory and placed within a process for it to be run. • Machine instructions may take memory addresses as arguments, but not disk addresses. The CPU fetches instructions from memory according to the value of the program counter. These instructions may cause additional loading from and storing to specific memory addresses. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 3 / 47
  • 7. Basic Hardware Main memory and registers are the only storage that the CPU can access directly. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 4 / 47
  • 8. Basic Hardware Main memory and registers are the only storage that the CPU can access directly. Register access in one CPU clock (or less) Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 4 / 47
  • 9. Basic Hardware Main memory and registers are the only storage that the CPU can access directly. Register access in one CPU clock (or less) Main memory can take many cycles, causing a stall. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 4 / 47
  • 10. Basic Hardware Main memory and registers are the only storage that the CPU can access directly. Register access in one CPU clock (or less) Main memory can take many cycles, causing a stall. Cache sits between main memory and registers. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 4 / 47
  • 11. Address Protection We must protect the OS from access by user processes. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 5 / 47
  • 12. Address Protection We must protect the OS from access by user processes. We must protect user processes from one another. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 5 / 47
  • 13. Address Protection We must protect the OS from access by user processes. We must protect user processes from one another. This protection is provided by the hardware. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 5 / 47
  • 14. Address Protection We must protect the OS from access by user processes. We must protect user processes from one another. This protection is provided by the hardware. A separate memory space for each process. • Determining the range of legal addresses that the process may access. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 5 / 47
  • 15. Base and Limit Registers A pair of base and limit registers define the logical address space. CPU must check every memory access generated in user mode to be sure it is between base and limit for that user. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 6 / 47
  • 16. Hardware Address Protection Any attempt by a user program to access OS memory or other users’ memory results in a trap to the OS, which treats the attempt as a fatal error. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 7 / 47
  • 17. Address Binding Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 8 / 47
  • 18. Address Binding (1/2) Programs on disk, ready to be brought into memory to execute form an input queue. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 9 / 47
  • 19. Address Binding (1/2) Programs on disk, ready to be brought into memory to execute form an input queue. A user process can reside in any part of the physical memory. • Without support, must be loaded into address 00000. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 9 / 47
  • 20. Address Binding (2/2) A user program goes through several steps before being executed. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 10 / 47
  • 21. Address Binding (2/2) A user program goes through several steps before being executed. Addresses may be represented in different ways during these steps. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 10 / 47
  • 22. Address Binding (2/2) A user program goes through several steps before being executed. Addresses may be represented in different ways during these steps. • Source code addresses usually symbolic. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 10 / 47
  • 23. Address Binding (2/2) A user program goes through several steps before being executed. Addresses may be represented in different ways during these steps. • Source code addresses usually symbolic. • A compiler typically binds these symbolic addresses to relocatable addresses, e.g., 14 bytes from beginning of this module. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 10 / 47
  • 24. Address Binding (2/2) A user program goes through several steps before being executed. Addresses may be represented in different ways during these steps. • Source code addresses usually symbolic. • A compiler typically binds these symbolic addresses to relocatable addresses, e.g., 14 bytes from beginning of this module. • Linker or loader will bind relocatable addresses to absolute addresses, e.g., 74014. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 10 / 47
  • 25. Binding of Instructions and Data to Memory (1/3) Address binding of instructions and data to memory addresses can happen at three different stages. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 11 / 47
  • 26. Binding of Instructions and Data to Memory (1/3) Address binding of instructions and data to memory addresses can happen at three different stages. Compile time: if memory location known a priori, absolute code can be generated. • Must recompile code if starting location changes. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 11 / 47
  • 27. Binding of Instructions and Data to Memory (2/3) Load time: must generate relocatable code if memory location is not known at compile time. • Final binding is delayed until load time. • If the starting address changes, we need only reload the user code to incorporate this changed value. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 12 / 47
  • 28. Binding of Instructions and Data to Memory (3/3) Execution time: binding delayed until run time if the process can be moved during its execution from one memory segment to another. • Need hardware support Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 13 / 47
  • 29. Logical vs. Physical Address Space (1/2) Logical address (virtual address): address generated by the CPU. • Logical address space is the set of all logical addresses generated by a program. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 14 / 47
  • 30. Logical vs. Physical Address Space (1/2) Logical address (virtual address): address generated by the CPU. • Logical address space is the set of all logical addresses generated by a program. Physical address: address seen by the memory unit. • Physical address space is the set of all physical addresses generated by a program. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 14 / 47
  • 31. Logical vs. Physical Address Space (1/2) Logical address (virtual address): address generated by the CPU. • Logical address space is the set of all logical addresses generated by a program. Physical address: address seen by the memory unit. • Physical address space is the set of all physical addresses generated by a program. The concept of a logical address space that is bound to a separate physical address space is central to proper memory management. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 14 / 47
  • 32. Logical vs. Physical Address Space (2/2) Logical and physical addresses are the same in compile-time and load-time address-binding schemes. Logical and physical addresses differ in execution-time address-binding scheme. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 15 / 47
  • 33. Memory-Management Unit (MMU) (1/2) Hardware device that at run time maps virtual to physical address. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 16 / 47
  • 34. Memory-Management Unit (MMU) (1/2) Hardware device that at run time maps virtual to physical address. As a simple scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. • Base register now called relocation register. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 16 / 47
  • 35. Memory-Management Unit (MMU) (2/2) Two different types of addresses: • Logical addresses: range 0 to max • Physical addresses: range R + 0 to R + max for a base value R Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 17 / 47
  • 36. Memory-Management Unit (MMU) (2/2) Two different types of addresses: • Logical addresses: range 0 to max • Physical addresses: range R + 0 to R + max for a base value R The user program generates only logical addresses and thinks that the process runs in locations 0 to max. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 17 / 47
  • 37. Memory-Management Unit (MMU) (2/2) Two different types of addresses: • Logical addresses: range 0 to max • Physical addresses: range R + 0 to R + max for a base value R The user program generates only logical addresses and thinks that the process runs in locations 0 to max. These logical addresses must be mapped to physical addresses before they are used. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 17 / 47
  • 38. Dynamic Linking and Loading Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 18 / 47
  • 39. Dynamic Loading (1/2) Routine/library is not loaded until it is called. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 19 / 47
  • 40. Dynamic Loading (1/2) Routine/library is not loaded until it is called. The main program is loaded into memory and is executed. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 19 / 47
  • 41. Dynamic Loading (1/2) Routine/library is not loaded until it is called. The main program is loaded into memory and is executed. When a routine is needed, if it has not been loaded, the loader loads the desired routine into memory and to update the program’s address tables to reflect this change. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 19 / 47
  • 42. Dynamic Loading (1/2) Routine/library is not loaded until it is called. The main program is loaded into memory and is executed. When a routine is needed, if it has not been loaded, the loader loads the desired routine into memory and to update the program’s address tables to reflect this change. Then control is passed to the newly loaded routine. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 19 / 47
  • 43. Dynamic Loading (1/2) Routine/library is not loaded until it is called. The main program is loaded into memory and is executed. When a routine is needed, if it has not been loaded, the loader loads the desired routine into memory and to update the program’s address tables to reflect this change. Then control is passed to the newly loaded routine. All routines kept on disk in relocatable load format. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 19 / 47
  • 44. Dynamic Loading (2/2) Better memory-space utilization; unused routine is never loaded. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 20 / 47
  • 45. Dynamic Loading (2/2) Better memory-space utilization; unused routine is never loaded. Useful when large amounts of code are needed to handle infrequently occurring cases. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 20 / 47
  • 46. Dynamic Loading (2/2) Better memory-space utilization; unused routine is never loaded. Useful when large amounts of code are needed to handle infrequently occurring cases. No special support from the OS is required. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 20 / 47
  • 47. Dynamic Loading (2/2) Better memory-space utilization; unused routine is never loaded. Useful when large amounts of code are needed to handle infrequently occurring cases. No special support from the OS is required. Implemented through program design. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 20 / 47
  • 48. Dynamic Loading (2/2) Better memory-space utilization; unused routine is never loaded. Useful when large amounts of code are needed to handle infrequently occurring cases. No special support from the OS is required. Implemented through program design. OS can help by providing libraries to implement dynamic loading. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 20 / 47
  • 49. Dynamic Liking (1/2) Static linking: system libraries and program code combined by the loader into the binary program image. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 21 / 47
  • 50. Dynamic Liking (1/2) Static linking: system libraries and program code combined by the loader into the binary program image. Dynamic linking: linking postponed until execution time. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 21 / 47
  • 51. Dynamic Liking (1/2) Static linking: system libraries and program code combined by the loader into the binary program image. Dynamic linking: linking postponed until execution time. Stub: small piece of code, used to locate the appropriate memory-resident library routine. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 21 / 47
  • 52. Dynamic Liking (1/2) Static linking: system libraries and program code combined by the loader into the binary program image. Dynamic linking: linking postponed until execution time. Stub: small piece of code, used to locate the appropriate memory-resident library routine. Stub replaces itself with the address of the routine, and executes the routine. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 21 / 47
  • 53. Dynamic Liking (2/2) OS checks if routine is in processes memory address. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 22 / 47
  • 54. Dynamic Liking (2/2) OS checks if routine is in processes memory address. If not in address space, add to address space. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 22 / 47
  • 55. Dynamic Liking (2/2) OS checks if routine is in processes memory address. If not in address space, add to address space. Dynamic linking is particularly useful for shared libraries. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 22 / 47
  • 56. Swapping Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 23 / 47
  • 57. Swapping (1/3) A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 24 / 47
  • 58. Swapping (1/3) A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store: fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 24 / 47
  • 59. Swapping (1/3) A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store: fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Total memory space of processes can exceed physical memory. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 24 / 47
  • 60. Swapping (2/3) Does the swapped out process need to swap back in to same physical addresses? Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 25 / 47
  • 61. Swapping (2/3) Does the swapped out process need to swap back in to same physical addresses? • Depends on address binding method. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 25 / 47
  • 62. Swapping (2/3) Does the swapped out process need to swap back in to same physical addresses? • Depends on address binding method. Pending I/O: cannot swap out as I/O would occur to wrong process. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 25 / 47
  • 63. Swapping (2/3) Does the swapped out process need to swap back in to same physical addresses? • Depends on address binding method. Pending I/O: cannot swap out as I/O would occur to wrong process. • Or always transfer I/O to kernel space, then to I/O device. • Known as double buffering, adds overhead. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 25 / 47
  • 64. Swapping (3/3) Standard swapping not used in modern OSs, but modified version is common. Swap only when free memory extremely low. Disabled again once memory demand reduced below threshold. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 26 / 47
  • 65. Swapping Cost Major part of swap time is transfer time; which is proportional to the amount of memory swapped. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 27 / 47
  • 66. Swapping Cost Major part of swap time is transfer time; which is proportional to the amount of memory swapped. If next processes to be put on CPU is not in memory, need to swap out a process and swap in target process. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 27 / 47
  • 67. Swapping Cost Major part of swap time is transfer time; which is proportional to the amount of memory swapped. If next processes to be put on CPU is not in memory, need to swap out a process and swap in target process. Example: • 100MB process swapping to hard disk with transfer rate of 50MB/sec. • Swap out time of 2s + swap in of same sized process. • Total context switch swapping component time of 4s. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 27 / 47
  • 68. Swapping on Mobile Systems (1/2) Not typically supported. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 28 / 47
  • 69. Swapping on Mobile Systems (1/2) Not typically supported. Flash memory based • Small amount of space • Limited number of write cycles • Poor throughput between flash memory and CPU on mobile platform Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 28 / 47
  • 70. Swapping on Mobile Systems (2/2) Instead use other methods to free memory if low. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 29 / 47
  • 71. Swapping on Mobile Systems (2/2) Instead use other methods to free memory if low. iOS asks apps to voluntarily relinquish allocated memory. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 29 / 47
  • 72. Swapping on Mobile Systems (2/2) Instead use other methods to free memory if low. iOS asks apps to voluntarily relinquish allocated memory. Read-only data thrown out and reloaded from flash if needed. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 29 / 47
  • 73. Swapping on Mobile Systems (2/2) Instead use other methods to free memory if low. iOS asks apps to voluntarily relinquish allocated memory. Read-only data thrown out and reloaded from flash if needed. Failure to free can result in termination. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 29 / 47
  • 74. Swapping on Mobile Systems (2/2) Instead use other methods to free memory if low. iOS asks apps to voluntarily relinquish allocated memory. Read-only data thrown out and reloaded from flash if needed. Failure to free can result in termination. Android terminates apps if low free memory, but first writes application state to flash for fast restart. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 29 / 47
  • 75. Contiguous Memory Allocation Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 30 / 47
  • 76. Contiguous Allocation (1/2) Main memory must support both OS and user processes. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 31 / 47
  • 77. Contiguous Allocation (1/2) Main memory must support both OS and user processes. Limited resource, must allocate efficiently. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 31 / 47
  • 78. Contiguous Allocation (1/2) Main memory must support both OS and user processes. Limited resource, must allocate efficiently. Contiguous allocation is one early method. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 31 / 47
  • 79. Contiguous Allocation (1/2) Main memory must support both OS and user processes. Limited resource, must allocate efficiently. Contiguous allocation is one early method. Main memory usually into two partitions: • Resident OS, usually held in low memory with interrupt vector. • User processes then held in high memory. • Each process contained in single contiguous section of memory. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 31 / 47
  • 80. Contiguous Allocation (2/2) Relocation registers used to protect user processes from each other, and from changing OS code and data. • Base register contains value of smallest physical address. • Limit register contains range of logical addresses. • MMU maps logical address dynamically. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 32 / 47
  • 81. Multiple-Partition Allocation (1/2) Memory is to divide memory into several fixed-sized partitions. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 33 / 47
  • 82. Multiple-Partition Allocation (1/2) Memory is to divide memory into several fixed-sized partitions. Each partition may contain exactly one process. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 33 / 47
  • 83. Multiple-Partition Allocation (1/2) Memory is to divide memory into several fixed-sized partitions. Each partition may contain exactly one process. Degree of multiprogramming limited by number of partitions. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 33 / 47
  • 84. Multiple-Partition Allocation (1/2) Memory is to divide memory into several fixed-sized partitions. Each partition may contain exactly one process. Degree of multiprogramming limited by number of partitions. When a partition is free, a process is selected from the input queue and is loaded into the free partition. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 33 / 47
  • 85. Multiple-Partition Allocation (2/2) Variable-partition sizes for efficiency (sized to a given process’ needs). Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 34 / 47
  • 86. Multiple-Partition Allocation (2/2) Variable-partition sizes for efficiency (sized to a given process’ needs). Hole: block of available memory. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 34 / 47
  • 87. Multiple-Partition Allocation (2/2) Variable-partition sizes for efficiency (sized to a given process’ needs). Hole: block of available memory. When a process arrives, it is allocated memory from a hole large enough to accommodate it. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 34 / 47
  • 88. Multiple-Partition Allocation (2/2) Variable-partition sizes for efficiency (sized to a given process’ needs). Hole: block of available memory. When a process arrives, it is allocated memory from a hole large enough to accommodate it. Process exiting frees its partition, adjacent free partitions combined Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 34 / 47
  • 89. Multiple-Partition Allocation (2/2) Variable-partition sizes for efficiency (sized to a given process’ needs). Hole: block of available memory. When a process arrives, it is allocated memory from a hole large enough to accommodate it. Process exiting frees its partition, adjacent free partitions combined OS maintains information about: allocated partitions and free partitions (hole) Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 34 / 47
  • 90. Dynamic Storage-Allocation Problem How to satisfy a request of size n from a list of free holes? Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 35 / 47
  • 91. Dynamic Storage-Allocation Problem How to satisfy a request of size n from a list of free holes? First-fit: allocate the first hole that is big enough Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 35 / 47
  • 92. Dynamic Storage-Allocation Problem How to satisfy a request of size n from a list of free holes? First-fit: allocate the first hole that is big enough Best-fit: allocate the smallest hole that is big enough • Must search entire list, unless ordered by size. • Produces the smallest leftover hole. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 35 / 47
  • 93. Dynamic Storage-Allocation Problem How to satisfy a request of size n from a list of free holes? First-fit: allocate the first hole that is big enough Best-fit: allocate the smallest hole that is big enough • Must search entire list, unless ordered by size. • Produces the smallest leftover hole. Worst-fit: allocate the largest hole • Must also search entire list. • Produces the largest leftover hole. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 35 / 47
  • 94. Dynamic Storage-Allocation Problem How to satisfy a request of size n from a list of free holes? First-fit: allocate the first hole that is big enough Best-fit: allocate the smallest hole that is big enough • Must search entire list, unless ordered by size. • Produces the smallest leftover hole. Worst-fit: allocate the largest hole • Must also search entire list. • Produces the largest leftover hole. First-fit and best-fit better than worst-fit in terms of speed and storage utilization. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 35 / 47
  • 95. Fragmentation (1/3) External fragmentation: total memory space exists to satisfy a request, but it is not contiguous. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 36 / 47
  • 96. Fragmentation (1/3) External fragmentation: total memory space exists to satisfy a request, but it is not contiguous. Internal fragmentation: allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 36 / 47
  • 97. Fragmentation (1/3) External fragmentation: total memory space exists to satisfy a request, but it is not contiguous. Internal fragmentation: allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used. First fit analysis reveals that given N blocks allocated, 0.5N blocks lost to fragmentation: 50-percent rule Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 36 / 47
  • 98. Fragmentation (2/3) Compaction: a solution to the problem of external fragmentation. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 37 / 47
  • 99. Fragmentation (2/3) Compaction: a solution to the problem of external fragmentation. Shuffle memory contents to place all free memory together in one large block. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 37 / 47
  • 100. Fragmentation (2/3) Compaction: a solution to the problem of external fragmentation. Shuffle memory contents to place all free memory together in one large block. Compaction is possible only if relocation is dynamic, and is done at execution time. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 37 / 47
  • 101. Fragmentation (2/3) Compaction: a solution to the problem of external fragmentation. Shuffle memory contents to place all free memory together in one large block. Compaction is possible only if relocation is dynamic, and is done at execution time. I/O problem • Latch job in memory while it is involved in I/O • Do I/O only into OS buffers. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 37 / 47
  • 102. Fragmentation (3/3) Another possible solution to the external fragmentation problem: permit the logical address space of the processes to be noncontiguous. Two techniques: • Segmentation • Paging Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 38 / 47
  • 103. Segmentation Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 39 / 47
  • 104. Fragmentation (2/2) Memory-management scheme that supports user view of memory. A program is a collection of segments. A segment is a logical unit such as: • Main program • Procedure • Function • Object • ... Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 40 / 47
  • 105. Logical View of Segmentation Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 41 / 47
  • 106. Segmentation Architecture Logical address consists of a tuple: segment number, offset Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 42 / 47
  • 107. Segmentation Architecture Logical address consists of a tuple: segment number, offset Segment table: maps two-dimensional user-defined addresses into one-dimensional physical address. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 42 / 47
  • 108. Segmentation Architecture Logical address consists of a tuple: segment number, offset Segment table: maps two-dimensional user-defined addresses into one-dimensional physical address. Each table entry has: • Base: contains the starting physical address where the segments reside in memory • Limit: specifies the length of the segment Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 42 / 47
  • 109. Segmentation Hardware Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 43 / 47
  • 110. Segmentation Example A reference to byte 53 of segment 2: Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 44 / 47
  • 111. Segmentation Example A reference to byte 53 of segment 2: 4300 + 53 = 4353 Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 44 / 47
  • 112. Segmentation Example A reference to byte 53 of segment 2: 4300 + 53 = 4353 A reference to byte 852 of segment 3: Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 44 / 47
  • 113. Segmentation Example A reference to byte 53 of segment 2: 4300 + 53 = 4353 A reference to byte 852 of segment 3: 3200 + 852 = 4052 Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 44 / 47
  • 114. Segmentation Example A reference to byte 53 of segment 2: 4300 + 53 = 4353 A reference to byte 852 of segment 3: 3200 + 852 = 4052 A reference to byte 1222 of segment 0: Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 44 / 47
  • 115. Segmentation Example A reference to byte 53 of segment 2: 4300 + 53 = 4353 A reference to byte 852 of segment 3: 3200 + 852 = 4052 A reference to byte 1222 of segment 0: trap to OS Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 44 / 47
  • 116. Summary Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 45 / 47
  • 117. Summary Main memory Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
  • 118. Summary Main memory Address protection: base + limit Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
  • 119. Summary Main memory Address protection: base + limit Address binding: compile time, load time, execution time Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
  • 120. Summary Main memory Address protection: base + limit Address binding: compile time, load time, execution time Logical and physical address, MMU Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
  • 121. Summary Main memory Address protection: base + limit Address binding: compile time, load time, execution time Logical and physical address, MMU Swapping: backing store, swapping cost Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
  • 122. Summary Main memory Address protection: base + limit Address binding: compile time, load time, execution time Logical and physical address, MMU Swapping: backing store, swapping cost Contiguous memory allocation: partitions, holes, first-fit, best-fit, worst-fit Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
  • 123. Summary Main memory Address protection: base + limit Address binding: compile time, load time, execution time Logical and physical address, MMU Swapping: backing store, swapping cost Contiguous memory allocation: partitions, holes, first-fit, best-fit, worst-fit External and internal fragmentation: compaction, segmentation, paging Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
  • 124. Summary Main memory Address protection: base + limit Address binding: compile time, load time, execution time Logical and physical address, MMU Swapping: backing store, swapping cost Contiguous memory allocation: partitions, holes, first-fit, best-fit, worst-fit External and internal fragmentation: compaction, segmentation, paging Segmentation: noncontiguous address, user view of memory Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 46 / 47
  • 125. Questions? Acknowledgements Some slides were derived from Avi Silberschatz slides. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/5 47 / 47