Neurons On Wheels - Status Update
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The document discusses an FPGA implementation of a neural network for smart vehicles. It describes implementing a model in TensorFlow, using a dataset of 11 videos with 1000 frames each. It then details the C code implementation of the convolutional layer, intermediate layers, and fully connected output layers of the neural network model. The presentation provides contact information for the presenters for any questions.
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Normal Labour/ Stages of Labour/ Mechanism of Labour
Normal labor is also termed spontaneous labor, defined as the natural physiological process through which the fetus, placenta, and membranes are expelled from the uterus through the birth canal at term (37 to 42 weeks
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Stress is a psycho-physical response to very different loads, of an emotional, cognitive or social nature, which is perceived as excessive thus having severe implications on wellbeing both in the short and in the long term. Different physiological manifestations occur during stressful events which, if detected promptly, can help in managing the situation. Therefore, the objective of this project is to develop a small portable device for psychological stress detection. This includes design of machine learning framework for stress detection and a prototype of a low-cost portable device for recording the physiological data. The ML framework is including the model together with the heuristic and knowledge based feature engineering from physiological time series. As a result EMoCy system is achieving accuracy of 97.2 ± 2% on stress/baseline binary classification task.
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Personalized Pagerank (PPR) is a common building block of Recommender Systems. In this setting, the computation of the topmost ranked vertices needs to be executed extremely fast, with low latency and possibly for multiple elements concurrently.
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Furthermore, Artificial Neural Networks are becoming the base of many of these applications, both in embedded and in server-class contexts. While Graphics Processing Units (GPUs) are predominantly used for training, solutions for inference often rely on Field Programmable Gate Arrays (FPGAs) since they are more flexible and cost-efficient in many scenarios.
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A Methodology for Automatic GPU Kernel Optimization - NECSTTechTalk 4/06/2020NECST Lab @ Politecnico di Milano
Abstract inglese:
In recent years Graphic Processing Units have seen widespread adoption in many scientific fields, from Machine Learning (ML) to Genomics. Their use makes it possible to achieve significant speedups and improvements in power efficiency over computationally intensive algorithms compared to General Purpose Central Processing Units. However, algorithms require specific knowledge of the GPU architecture and expertise to achieve significant results. In this work, we describe a methodology for automatic GPU kernel optimization. Our methodology exploits the Berkeley Roofline Model to perform a performance analysis of the algorithm considered and aims to increase the accessibility of GPU programming automatizing the optimization process of the kernel. We provide an in-depth analysis of this methodology, an overview on the state of the art, and a description of a tool we developed that automatically applies our methodology to obtain a highly optimized GPU version of two of the most popular algorithms used in computational biology, the X-drop and Smith-Waterman algorithms. The Smith-Waterman algorithm is one of the most used algorithms in genomics pipelines. The algorithm finds the optimal local alignment between two genomic sequences, at the cost of being particularly compute-intensive. The popular X-drop algorithm reduces the time required by the alignment by searching only for high-quality alignments. The algorithms accelerated using our methodology achieve more than 6x and 3x speed-up, for the X-drop and Smith-Waterman algorithms respectively, with respect to the state of the art implementation of these algorithms.DRACO - NECSTTechTalk 28/05/2020
In recent years, there has been a shift in the computer architecture landscape. Moore’s Law and Dennard’s Scaling has driven for 40 years the research on General Purpose RISC-based architectures and their optimizations, thanks to scaling in transistor count and power budget. However, with the end of these laws, the researchers are close to the boundary for technological and architectural reasons. Hence, computer architects have to consider a new way to think computer architectures narrowing the domain of the targeted computations, focusing on Domain Specific Architectures (DSAs) to harvest more energy-efficient calculations.DSAs are architectures not particularly suited for general computations, but engines that perform few tasks efficiently. Nonetheless, for a long time, developing a full custom ASIC has been an effort and time-consuming process where the time to market and the Non-Recurrent engineering costs (NRE) are critical and not negligible. Indeed, in this scenario, productivity becomes a crucial point. This is why both companies and the academic world are trying to apply iterative approaches (e.g., Agile) to fast hardware development. Therefore, fast prototyping architectures and adaptable computing platform are becoming more and more important. Indeed, Field Programmable Gate Arrays (FPGAs) are the state of the art platform for reconfigurable computing. They can provide a generic system, and recently also heterogeneous, able to be reprogrammed at the circuit level after manufacturing. In fact, FPGAs are mainly used for fast prototyping of digital systems and architectures that need to be reprogrammed easily, e.g., telecommunication field and many others.
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Energy proportionality is the key in order to reduce the Total Cost of Ownership (TCO) of Warehouse Scale Computer (WSC) systems, yet is difficult to achieve in practice. Typical WSC hardware usually does not meet this principle. Furthermore, critical services (e.g. billing) require all servers to remain up regardless the current traffic intensity. These two issues make existing power management technique ineffective at reducing energy use in a WSC dimension. We present Hybrid Performance-aware Power-capping Orchestrator (HyPPO), a distributed Observe Decide Act (ODA) control loop for optimizing energy proportionality of a distribute containerized infrastructures. This first version of HyPPO uses Kubernetes resource metrics (e.g. milli-cpus consumption) in order to dynamically adjust node power consumption, while respecting the Service Level Agreement (SLA) agreement defined by the containerized application owners.
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